JPH04116973A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To increase the area of a lower electrode of a capacitor and to prevent damage of a gate electrode by eliminating planar superposition of an opening of a film for forming a signal charge storage capacitor to connect a signal transmission line to an impurity region and the gate electrode. CONSTITUTION:Since an opening is, to form the opening in films 10, 11 for constituting a signal charge storage capacitor to connect a signal transmission line 14 to an impurity region 6b, so formed as not to have a planar superposition with gates 4a, 4b, the gates 4a, 4b are not lost when the opening is formed at the films 10, 11 for forming the capacitor and when protective films 13 of sidewalls of the upper electrode 11 and the film 10 of the capacitor. As a result, the areas of lower electrodes 9a, 9b of the capacitor can be increased.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device and a method for manufacturing the same, and particularly to a highly integrated semiconductor device capable of random input/output of arbitrary storage information. It is.

[Conventional technology]

In recent years, the demand for semiconductor storage devices has been rapidly expanding due to the remarkable spread of information devices such as computers. Furthermore, in terms of functionality, it is required to have a large storage capacity and be capable of high-speed operation. Along with this,
2. Description of the Related Art Technological developments regarding higher integration, high-speed response, and high reliability of semiconductor memory devices are underway.

Among semiconductor memory devices, DRAM (Dynamic Random) is a type of semiconductor memory device that allows random input/output of stored information.
domAccess Memory) 〇Generally D
A RAM is composed of a memory cell array, which is a storage area that stores a large amount of stored information, and peripheral circuits necessary for input/output with the outside. FIG. 4 is a block diagram showing the configuration of a general RAM. The DRAM 50 includes a memory cell array 51 for accumulating data signals of stored information;
A row and column address buffer 52 for externally receiving an address signal for selecting a memory cell constituting a unit memory circuit, and a row decoder 5 for specifying a memory cell by decoding the address signal.
3 and a column decoder 54, a sense refresh amplifier 55 that amplifies and reads the signal stored in a designated memory cell, a data in buffer 56 and a data out buffer 57 for data input/output, and generates a clock signal. A clock generator 58 is included.

The memory cell array 51, which occupies a large area on a semiconductor chip, is formed by arranging a plurality of memory cells in a matrix for storing unit storage information. Fifth
The figure shows an equivalent circuit diagram for 4 bits of memory cells constituting this memory cell array 51. This memory cell consists of one MOS (Metal-Oxide-
This is a so-called l-transistor l-capacitor type memory cell, which is composed of a transistor and one capacitive element connected to it.This type of memory cell has a simple structure, so it is easy to use in a memory cell array. It is easy to improve the degree of integration and is widely used in large-capacity DRAMs.

Furthermore, DREM memory cells can be divided into several types depending on the structure of the capacitor for storing signal charges. One of them is a so-called stacked type memory cell, which is disclosed in Japanese Patent Publication No. 60-2784, for example. FIG. 6 is a cross-sectional view of this stacked cell. In this type of memory cell, a two-layer conductive film 9b is formed extending over the word line 4b or the element isolation region 2.
, 11 and the dielectric film lO between them constitute a capacitor.

[Invention or problem to be solved]

The conventional semiconductor device is configured as described above, and the DRA
If the memory cell size is reduced due to the high integration of M, the capacitor area will also be reduced at the same time, or from the viewpoint of stable operation and reliability of DRAM as a storage device, even if the memory cell size is reduced. The amount of charge that can be stored in a 1-bit memory cell needs to be maintained approximately constant, so in the conventional stacked type memory cell shown in FIG. 6, an opening is formed in a part of the upper electrode 11 of the capacitor. Further, an opening was formed in the interlayer insulating film 13 to connect the bit line 14 and the impurity region 6C on the semiconductor substrate 1. However, in the above structure, variations in the manufacturing process are absorbed between the opening in the interlayer insulating film 13 and the upper electrode 11 of the capacitor, and between the opening of the upper electrode 11 and the lower electrode 9b of the capacitor. Therefore, there is a limit to increasing the area of the capacitor.

As a solution, for example,
As shown in No. 3555, an insulating film 13 is formed in the opening of the upper electrode 11 of the capacitor in a self-aligned manner on the side wall of the upper electrode, and the distance between the bit line and the upper electrode 11 of the capacitor is minimized. There have been attempts to narrow the area, but if the end of the upper electrode 11 of the capacitor is located above the gate electrode 4a, if an attempt is made to form an insulating film on the sidewalls of the upper electrode 11 in a self-aligned manner, the narrowing of the gate electrode 4a There are problems in that the upper insulating film 13 becomes thinner and the insulating film on the side wall of the upper electrode 11 cannot be made thicker.

This invention was made in order to solve the above-mentioned problems, and it is possible to secure capacitor capacity in a stacked capacitor even if the memory cell size is reduced without causing difficulties in pattern formation. The object of the present invention is to obtain a semiconductor device suitable for high integration and a method for manufacturing the same.

[Means to solve the problem]

A semiconductor device according to the present invention includes forming a plurality of second conductivity type impurity regions in an element formation region of a first conductivity type semiconductor substrate,
A lower conductive film in which a gate electrode is formed between the adjacent regions via an insulating film, and a portion of the gate electrode is connected to an impurity region on one side of the gate electrode.

An insulating film and an upper conductive film are sequentially formed to form a signal charge storage capacitor, an opening is formed in both the conductive films and the insulating film, and the gate electrode is connected to the impurity region on the other side of the gate electrode through the opening. In the semiconductor device in which a signal transmission line is formed, the opening is patterned so that it does not overlap the gate electrode in a plane.

Further, a method for manufacturing a semiconductor device according to the present invention includes a step of forming an element isolation region in a first conductivity type semiconductor substrate;
a step of forming a plurality of second conductive impurity regions in an element formation region of a conductive type semiconductor substrate; a step of forming a gate electrode made of a first conductive film with an insulating film interposed between the adjacent regions; A lower electrode consisting of a second conductive film connected to an impurity region on one side of the gate electrode, an insulating film and a third
a step of sequentially forming an upper electrode made of a conductive film to form a signal charge storage capacitor; forming a signal transmission line connected to an impurity region on the other side of the gate electrode through an opening formed in a third conductive film and an insulating film; Now, after sequentially forming a second conductive film, an insulating film, and a third conductive film, an insulating film is formed thereon, and these films are selectively removed to form a layer on the impurity region on one side of the gate electrode. The opening is formed so as not to overlap with the gate electrode in plane, and in the step of forming the signal transmission line, an insulating film is formed to cover the entire surface of the opening, and an impurity on one side of the gate electrode of the insulating film is formed. A central portion of the region is selectively removed to expose a portion thereof, and a signal transmission line made of the fourth conductive film is connected to the exposed impurity region.

[Effect]

In this invention, since the opening of the film constituting the signal charge storage key capacitor formed to connect the signal transmission line (bit line) to the impurity region does not overlap the gate electrode in plan, The gate electrode is not damaged when forming an opening in a film constituting the capacitor and when forming a protective film for the upper electrode of the capacitor and the side wall portion of the insulating film thereof.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a cross-sectional structural diagram of a stacked type memory cell of a DRAM according to an embodiment of the present invention, and FIGS.
The same reference numerals as in the figure indicate the same or corresponding parts, and the memory cell is composed of one access transistor 19a (19b) and one capacitor 20a (20b),
Each memory cell is insulated and isolated from adjacent memory cells by an element isolation region 2 formed on the surface of a semiconductor substrate 1. The access transistor 19a (19b) includes impurity regions 6a (6b) and 6c formed on the surface of the semiconductor substrate l, and a thin gate oxide film (first insulating film) located between the impurity regions 6a (6b) and 60. membrane) 3a (3b
) formed via the gate electrode (first conductive film) 4a
(4b).

Further, the capacitor 20a (20b) has a lower electrode (first electrode) 9a (9b) made of a conductive material such as polycrystalline silicon.
and an upper electrode 11, and a dielectric film (second insulating film) lO made of a dielectric material such as a laminated film of a nitride film and an oxide film or a tantalum oxide film between them, and the lower electrode 9a (9b) is the access transistor 19a (19
b) is connected to the source or train region 6a (6b). Bit line (fourth conductive film) 1 made of a conductive film
4 is located on the interlayer film made of the insulating film 13, and is connected to the source or drain region 6C of the access transistor 19a (19b). Further, in the part where the bit line 14 is connected to the impurity region 6c, the upper electrode 11 of the capacitor sufficiently covers the upper part of the gate pole 4a (4b), and is used to protect the side wall of the upper electrode 11 of the capacitor. When the insulating film 13 is formed in a self-aligned manner, it plays a role of protecting the lower gate electrode 4a (4b).

Next, a method of manufacturing the above memory cell will be explained with reference to FIG. 2(a) (1) to FIG. 2(k).

First, as shown in FIG. 1A, an element isolation region 2 is formed in a predetermined region of the surface of a semiconductor substrate 1 using, for example, the LOCO3 method.

Next, as shown in FIG. 1B, the surface of the semiconductor substrate 1 is thermally oxidized to form an oxide film (first oxide film) 3 on the surface of the semiconductor substrate 1 surrounded by the element isolation region 2.

Next, a conductive film (second conductive film) 4 such as polycrystalline silicon doped with phosphorus is continuously formed by, for example, a low pressure CVD method, and an insulating film 5 such as an oxide film is further formed by, for example, a low pressure CVD method. and deposit.

These are then removed using normal photolithography and dry etching, leaving only predetermined portions, to form gate electrodes 4a, 4a of access transistors and word lines.
”, 4b, 4b- are formed (Figure (C)).

Next, using the gate electrodes 4a, 4a-, 4b, 4b' and the insulating film 5 above them as a mask, impurity regions 6a, '6b are implanted into the surface of the semiconductor substrate 1 by, for example, ion implantation.
, 6c (Figure (d)).

Thereafter, for example, an insulating film 7 such as an oxide film is deposited on the entire surface of the semiconductor substrate l by, for example, a low pressure CVD method (Figure (e)).
).

Next, the insulating film 7 is selectively removed by an anisotropic etching method, and an insulating film 8 is formed on the upper and side wall portions of the gate electrodes 4a, 4a-, 4b, and 4b' (FIG. (f)).

Next, a conductive film 9 made of polycrystalline silicon is deposited by, for example, low pressure CVD, and lower electrodes 9a and 9b of the capacitor are formed by ordinary photolithography and dry etching (Figure (g)). ).

Subsequently, a nitride film is deposited on the entire surface of the semiconductor substrate 1 by, for example, a low pressure CVD method, and then a part of the nitride film is oxidized by heat treatment in an oxygen atmosphere to form the dielectric film 1 of the capacitor.
0 (Figure (h)).

Next, a conductive film 11 such as polycrystalline silicon is deposited on the entire surface of the semiconductor substrate by, for example, a low pressure CVD method, and then an insulating film 12 such as an oxide film is deposited on the entire surface of the semiconductor substrate by, for example, a low pressure CVD method. Insulating film 1 above region 6b
2 and the conductive film 11 are removed in a range narrower than the width of the impurity region 6b to form the upper electrode 11 of the capacitor (see FIG.
i)).

Next, an insulating film such as an oxide film is deposited over the entire surface by, for example, a CVD method, and the insulating film 13 above the center of the impurity region 6b is removed by an anisotropic etching method. A predetermined portion of the semiconductor substrate 1 is exposed (FIG. (j)).

Next, a conductive film such as polycrystalline silicon is deposited on the entire surface by, for example, a low pressure CVD method, followed by a tungsten silicide film by, for example, a snow vine method, and the bit lines are etched using ordinary photolithography and dry etching methods. 14 (Figure (kl)).

Further, FIG. 3 shows a cross-sectional view along the line A-A of the DRAM memory cell according to the above embodiment. You can see that it is covered.

In this way, according to this embodiment, the signal transmission line (bit line)
When forming an opening in the film 10.11 constituting the signal charge storage capacitor for connecting the signal charge storage capacitor 14 to the impurity region 6b, the opening is formed so as not to have a planar overlap with the gate electrodes 4a and 4b. Therefore, when forming an opening in the film 10.11 constituting the capacitor and when forming the upper electrode 11 of the capacitor and the protective film 13 on the side wall portion of the insulating film 10, the gate electrodes 4a and 4b can be formed without damaging them. As a result, the area of the lower electrodes 9a, 9b of the capacitor can be increased.

In the above embodiment, an example of a polycide structure of a tungsten silicide film and polycrystalline silicon is shown as the bit line 14, but the bit line is not limited to this structure. , T
An iN film or a composite film in which these films are stacked alternately may be used.

Further, in the above embodiment, an example of the LOCO3 method is shown in which a thick oxide film is formed in the element isolation region 2, but other isolation methods may be used, and for example, a field shield isolation method can also produce the same effect.

〔Effect of the invention〕

As described above, according to the semiconductor device of the present invention, the opening of the film constituting the signal charge storage capacitor for connecting the signal transmission line (bit line) and the impurity region and the gate electrode overlap in plane. This makes it possible to increase the area of the lower electrode of the signal charge storage capacitor, and also prevents damage to the gate electrode when forming the opening for the upper electrode of the signal charge storage capacitor. It has the effect of being able to do so.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing a DRAM memory cell according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view showing a DRAM memory cell according to an embodiment of the present invention.
3 is a sectional view showing the manufacturing flow of a RAM, FIG. 3 is a sectional view of a DRAM memory cell according to another embodiment of the present invention, FIG. 4 is a block diagram of a general RAM, and FIG. 5 is a 4-bit memory cell. 6 and 7 are cross-sectional views of conventional memory cells. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Element isolation region, 3a, 3
b... Gate oxide film (first insulating film), 4a, 4b.
...Gate electrode (first conductive film), 4a-, 4b-...
・Word line, 5... Insulating film, 6a, 6b, 6c...
Impurity region, 7... Insulating film, 8... Insulating film, 9a,
9b... Capacitor lower electrode (second conductive film), 10
...Capacitor dielectric film (second insulating film), 11...
Capacitor upper electrode (third conductive film), 12... insulating film, 13... third insulating film (insulating film), 14... fourth conductive film (bit line). In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Figure 1

Claims (2)

[Claims] (1) A plurality of second conductivity type impurity regions are formed in the element formation region of the first conductivity type semiconductor substrate, and a gate electrode is formed between the adjacent regions with an insulating film interposed therebetween, and a part of the impurity region forms the gate electrode. A signal charge storage capacitor is formed by sequentially forming a lower conductive film, an insulating film, and an upper conductive film connected to the impurity region on one side, and forming an opening in both the conductive films and the insulating film, and forming an opening in both the conductive films and the insulating film. A semiconductor device comprising a signal transmission line connected to an impurity region on the other side of the gate electrode through the opening, characterized in that the opening is patterned so as not to overlap with the gate electrode in plan view. Semiconductor equipment. (2) forming an element isolation region in the first conductivity type semiconductor substrate; forming a plurality of second conductivity type impurity regions in the element formation region of the first conductivity type semiconductor substrate; and forming a plurality of second conductivity type impurity regions between the adjacent regions. forming a gate electrode made of a first conductive film via an insulating film; a lower electrode made of a second conductive film, a part of which is connected to an impurity region on one side of the gate electrode; A step of sequentially forming an upper electrode made of a conductive film to form a signal charge storage capacitor, and an impurity region on the other side of the gate electrode through the openings formed in the second and third conductive films and the insulating film. and forming a signal transmission line connected to the capacitor. forming a film and selectively removing these films to form the opening on the impurity region on one side of the gate electrode so as not to overlap with the gate electrode in a plane, and forming the signal transmission line. In the step, an insulating film is formed to cover the entire surface of the opening, a central portion of the impurity region on one side of the gate electrode of the insulating film is selectively removed to expose a part of the insulating film, and a third layer is formed in the exposed impurity region. A semiconductor device characterized in that a signal transmission line made of four conductive films is connected.