JPH04116918A - Pattern forming method of semiconductor substrate - Google Patents
Pattern forming method of semiconductor substrateInfo
- Publication number
- JPH04116918A JPH04116918A JP2237633A JP23763390A JPH04116918A JP H04116918 A JPH04116918 A JP H04116918A JP 2237633 A JP2237633 A JP 2237633A JP 23763390 A JP23763390 A JP 23763390A JP H04116918 A JPH04116918 A JP H04116918A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- semiconductor substrate
- resist
- pattern
- thickness
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 50
- 239000004065 semiconductor Substances 0.000 title claims abstract description 49
- 238000000034 method Methods 0.000 title claims description 18
- 238000005498 polishing Methods 0.000 claims description 8
- 238000000059 patterning Methods 0.000 claims description 2
- 239000007788 liquid Substances 0.000 abstract description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052681 coesite Inorganic materials 0.000 abstract description 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 2
- 229910052682 stishovite Inorganic materials 0.000 abstract description 2
- 229910052905 tridymite Inorganic materials 0.000 abstract description 2
- 238000003754 machining Methods 0.000 abstract 2
- 238000005299 abrasion Methods 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- YXFVVABEGXRONW-UHFFFAOYSA-N Toluene Chemical compound CC1=CC=CC=C1 YXFVVABEGXRONW-UHFFFAOYSA-N 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 230000031700 light absorption Effects 0.000 description 3
- VLKZOEOYAKHREP-UHFFFAOYSA-N n-Hexane Chemical compound CCCCCC VLKZOEOYAKHREP-UHFFFAOYSA-N 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- QTBSBXVTEAMEQO-UHFFFAOYSA-M Acetate Chemical compound CC([O-])=O QTBSBXVTEAMEQO-UHFFFAOYSA-M 0.000 description 1
- CTQNGGLPUBDAKN-UHFFFAOYSA-N O-Xylene Chemical compound CC1=CC=CC=C1C CTQNGGLPUBDAKN-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000004090 dissolution Methods 0.000 description 1
- 125000001495 ethyl group Chemical group [H]C([H])([H])C([H])([H])* 0.000 description 1
- 229930195733 hydrocarbon Natural products 0.000 description 1
- 150000002430 hydrocarbons Chemical class 0.000 description 1
- QSHDDOUJBYECFT-UHFFFAOYSA-N mercury Chemical compound [Hg] QSHDDOUJBYECFT-UHFFFAOYSA-N 0.000 description 1
- 229910052753 mercury Inorganic materials 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- -1 polymethylsiloxane Polymers 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 239000008096 xylene Substances 0.000 description 1
Landscapes
- Preparing Plates And Mask In Photomechanical Process (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
Description
【発明の詳細な説明】
［発明の目的］
（産業上の利用分野）
この発明は半導体基板に複数のレジスト層を設け、最上
層のレジスト層から半導体基板へ順次パターンを転写す
るパターン形成方法に関する。[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) This invention relates to a pattern forming method in which a plurality of resist layers are provided on a semiconductor substrate and a pattern is sequentially transferred from the uppermost resist layer to the semiconductor substrate. .
（従来の技術）
半導体基板に大規模集積回路素子（ＬＳＩ）を形成する
場合、上記半導体基板に回路パターンを転写する工程が
ある。このようなバターニング技術においては、現在、
超高圧水銀から出力されるｇ線（λ−４３６ｎｍ ）お
よびｉ線（λ−３６５ｎｏ＋ ）を光源とした露光装置
が主流となっている。これらｇ線や１線の波長では焦点
深度が比較的深いから、半導体基板の表面にＡＩ配線な
どによって生じた段差でレジスト層の表面にうねりがあ
っても、その厚さを１〜２μｍと厚めにすることで、上
記段差の影響を避けることができる。(Prior Art) When forming a large scale integrated circuit element (LSI) on a semiconductor substrate, there is a step of transferring a circuit pattern to the semiconductor substrate. Currently, in such buttering technology,
Exposure apparatuses that use g-line (λ-436 nm) and i-line (λ-365 no+) output from ultra-high pressure mercury as light sources have become mainstream. Since the depth of focus is relatively deep for these G-line and 1-line wavelengths, even if there is a waviness on the surface of the resist layer due to a step caused by AI wiring on the surface of the semiconductor substrate, the thickness can be kept as thick as 1 to 2 μm. By doing so, the influence of the above-mentioned step can be avoided.
しかしながら、近年、ＬＳＩの微細化が進むにつれて光
源は上記ｇ線やｉ線よりも波長の短いエキシマレーザ（
λ−１５７〜２４８ ｎｍ）やＸ線が主流となりつつあ
る。光源の波長が短くなると、半導体基板に形成された
段差の上下でレジスト膜厚が変化する。その厚さの変化
によって波長の短い光は、焦点深度やレジスト層の光吸
収の影響を受けるから、上記半導体一基板にパターンを
精密に形成することができないという問題が生じる。However, in recent years, as the miniaturization of LSI has progressed, the light source has become an excimer laser (
λ-157 to 248 nm) and X-rays are becoming mainstream. As the wavelength of the light source becomes shorter, the resist film thickness changes above and below a step formed on a semiconductor substrate. Due to changes in the thickness, short-wavelength light is affected by the depth of focus and light absorption of the resist layer, resulting in the problem that a pattern cannot be precisely formed on the semiconductor substrate.
このような問題を除去する手段として、半導体基板にレ
ジスト層を多層に設ける多層レジストプロセスが考えら
れている。多層レジストプロセスとしては、半導体基板
上に平坦化層、中間層および上層の三層を順次積層し、
上層を湿式のリソグラフィー技術でパターン処理する。As a means to eliminate such problems, a multilayer resist process in which multiple resist layers are provided on a semiconductor substrate has been considered. The multilayer resist process involves sequentially stacking three layers: a flattening layer, an intermediate layer, and an upper layer on a semiconductor substrate.
The upper layer is patterned using wet lithography technology.
上層にパターンが転写されたなら、ドライエツチングに
よって上記上層をマスクとして中間層にパターンを転写
したのち、この中間層をマスクとして平坦化層にパター
ン転写し、最後に、この平坦化層をマスクとして半導体
基板にパターンを転写する。Once the pattern has been transferred to the upper layer, the pattern is transferred to the intermediate layer by dry etching using the upper layer as a mask, then the pattern is transferred to the flattening layer using this intermediate layer as a mask, and finally, the flattening layer is used as a mask to transfer the pattern to the intermediate layer. Transfer the pattern to the semiconductor substrate.
このような多層レジストプロセスによれば、反応性イオ
ンエツチングによってパターンを転写していくことから
、半導体基板の段差の上下で寸法差が生じずらいと言わ
れている。According to such a multilayer resist process, since the pattern is transferred by reactive ion etching, it is said that dimensional differences are unlikely to occur above and below the step of the semiconductor substrate.
第６図に多層レジストプロセスによってパターン形成さ
れる半導体基板１を示す。この半導体基板１の上面には
ＡＲ配線２によって段差３が形成されている。また、半
導体基板１の上面には平坦化層４、中間層５および上層
６のレジスト層が順次積層塗布されている。FIG. 6 shows a semiconductor substrate 1 patterned by a multilayer resist process. A step 3 is formed on the upper surface of this semiconductor substrate 1 by AR wiring 2 . Further, on the upper surface of the semiconductor substrate 1, a flattening layer 4, an intermediate layer 5, and an upper layer 6, which are resist layers, are sequentially laminated and coated.
しかしながら、このようにレジスト層を三層に設けても
、上記段差３の影響によって各層にうねりか生じること
が避けられない。そのため、上記段差３による膜厚のバ
ラツキは上層６では軽減されるだけであり、なくすこと
ができないから、そのバラツキにより、波長の短い光源
を用いた場合には焦点深度の影響やレジスト層の光吸収
の影響によってパターンを一定の状態で転写することが
できなくなるということが生じる。However, even if three resist layers are provided in this way, it is inevitable that each layer will have undulations due to the influence of the step 3. Therefore, the variation in film thickness due to the step 3 is only reduced in the upper layer 6, but cannot be eliminated. Therefore, due to this variation, when a light source with a short wavelength is used, the influence of the depth of focus and the light of the resist layer Due to the influence of absorption, the pattern cannot be transferred in a constant state.
（発明が解決しようとする課題）
このように、従来の多層レジストプロセスによるパター
ン形成方法では、半導体基板の上面にＡｊ７配線などに
よって段差が形成されていると、その段差の影響によっ
てレジスト層にうねりが生じ、そのうねりによってレジ
スト層の厚さが不均一になるから、半導体基板にパター
ンを所定の形状に精密に形成することができないという
ことがある。(Problems to be Solved by the Invention) As described above, in the pattern forming method using the conventional multilayer resist process, when a step is formed on the upper surface of a semiconductor substrate by Aj7 wiring, etc., the resist layer is undulated due to the effect of the step. This occurs and the thickness of the resist layer becomes non-uniform due to the waviness, which may make it impossible to precisely form a pattern in a predetermined shape on a semiconductor substrate.
この発明は上記事情にもとずきなされたもので、その目
的とするところは、半導体基板に多層レジストプロセス
によってパターンを形成する場合、そのパターンを所定
の形状に形成することができるようにした半導体基板の
パターン形成方法を提供することにある。This invention was made based on the above circumstances, and its purpose is to enable the pattern to be formed into a predetermined shape when forming a pattern on a semiconductor substrate by a multilayer resist process. An object of the present invention is to provide a method for forming a pattern on a semiconductor substrate.
［発明の構成］
（課題を解決するための手段及び作用）上記課題を解決
するためにこの発明は、半導体基板の段差を有する上面
に複数のレジスト層を順次積層し、最上層のレジスト層
から上記半導体基板へパターンを順次転写するパターン
形成方法において、上記複数のレジスト層のうち、少な
くとも１つのレジスト層の上面を平坦面に研磨加工する
ことを特徴とする。[Structure of the Invention] (Means and Effects for Solving the Problems) In order to solve the above problems, the present invention sequentially stacks a plurality of resist layers on the stepped upper surface of a semiconductor substrate, and The pattern forming method for sequentially transferring a pattern onto a semiconductor substrate is characterized in that the upper surface of at least one resist layer among the plurality of resist layers is polished into a flat surface.
このような方法によれば、半導体基板の上面がら最上層
のレジスト層の上面までの厚さを、うねりのない状態で
均一にすることができる。According to such a method, the thickness from the top surface of the semiconductor substrate to the top surface of the uppermost resist layer can be made uniform without waviness.
（実施例）
以下、この発明の一実施例を第１図乃至第５図を参照し
て説明する。Ｍ１図は半導体基板１１の上面１１ａに最
下層のレジスト層である平坦化層１２をスピンコードし
た状態を示す。この半導体基板１１の上面にはＡｌ配線
１３よって段差１４が形成されている。したがって、ス
ピンコードされた平坦化層１２は上記段差１４の影響を
受けてうねりが生じた状態にあり、半導体基板１１の上
面１１ａからの厚さが一定となっていない。(Embodiment) An embodiment of the present invention will be described below with reference to FIGS. 1 to 5. Figure M1 shows a state in which a flattening layer 12, which is the lowest resist layer, is spin-coded on the upper surface 11a of the semiconductor substrate 11. A step 14 is formed on the upper surface of this semiconductor substrate 11 by Al wiring 13 . Therefore, the spin-coded planarization layer 12 is in a undulating state due to the influence of the step 14, and the thickness from the top surface 11a of the semiconductor substrate 11 is not constant.
なお、平坦化層１２は１．３〜１．６μｍの厚さで設け
られる。Note that the planarization layer 12 is provided with a thickness of 1.3 to 1.6 μm.
半導体基板１１の上面１１ｇに平坦化層１２をスピンコ
ードしたならば、この平坦化層１２を研磨加工する。第
２図に上記平坦化層１２を研磨加工する装置を示す。す
なわち、同図中１５は半導体基板１１の下面側、すなわ
ち平坦化層１２が形成すしていない面を接合保持したホ
ルダーである。After the planarization layer 12 is spin-coated on the upper surface 11g of the semiconductor substrate 11, the planarization layer 12 is polished. FIG. 2 shows an apparatus for polishing the planarization layer 12. That is, 15 in the figure is a holder that holds the lower surface side of the semiconductor substrate 11, that is, the surface on which the planarizing layer 12 is not formed.
このホルダー１５は、たとえばすず（Ｓ ｎ）などによ
って形成された回転定盤１６の上面に対向して配置され
ている。この回転定ｌ１１６と上記半導体基板１１との
間には研磨液りが供給される。この研磨液りは、たとえ
ばレジストシンナであるエチルソルブアセテートに炭化
水素であるヘキサン、トルエン、キシレンなどを混合し
、溶解速度を遅くしたものが用いられている。上記ホル
ダー１５と回転定盤１６とはともに図示しない駆動機構
によって矢印方向に回転駆動されるとともに、ホルダー
１５は上下方向にも駆動されるようになっている。This holder 15 is arranged to face the upper surface of a rotating surface plate 16 made of, for example, tin (Sn). A polishing liquid is supplied between the rotation constant 116 and the semiconductor substrate 11. The polishing liquid used is, for example, a mixture of resist thinner ethyl solve acetate and hydrocarbons such as hexane, toluene, and xylene to slow the dissolution rate. Both the holder 15 and the rotating surface plate 16 are driven to rotate in the direction of the arrow by a drive mechanism (not shown), and the holder 15 is also driven in the vertical direction.
上記構成の研磨装置において、研磨液りを供給しながら
ホルダー１５と回転定盤１６とを回転駆動させるととも
に、ホルダー１５を下降させて平坦化層１２を上記回転
定盤１６の上面に接触させる。そして、上記半導体基板
１１の上面ＩＬａに設けられた平坦化層１２の上面が第
３図に示すように半導体基板１１の上面１１ａと平行な
平坦面１２ａとなるまで研磨加工する。すなわち、上記
平坦化層１２に現れた段差１４によるうねりを除去する
。それによって、上記平坦化層１２の厚さである半導体
基板１１の上面１１ｇから平坦化層１２の平坦面１２ａ
までの厚さを一定にすることができる。In the polishing apparatus configured as described above, the holder 15 and the rotating surface plate 16 are driven to rotate while supplying the polishing liquid, and the holder 15 is lowered to bring the flattening layer 12 into contact with the upper surface of the rotating surface plate 16. Then, polishing is performed until the upper surface of the planarization layer 12 provided on the upper surface ILa of the semiconductor substrate 11 becomes a flat surface 12a parallel to the upper surface 11a of the semiconductor substrate 11, as shown in FIG. That is, the waviness caused by the step 14 appearing on the planarization layer 12 is removed. Thereby, from the upper surface 11g of the semiconductor substrate 11, which is the thickness of the planarization layer 12, to the flat surface 12a of the planarization layer 12.
The thickness can be kept constant.
平坦化層１２の上面を平坦面１２ｇに加工したならば、
第４図に示すようにこの平坦面１２ａ上に５ｉ０２層で
あるポリメチルシロキサンからなる中間層１７を０．３
μｍ程度の厚さで設け、ついでこの中間層１７上に第５
図に示すようにレジスト層であるバターニングレジスト
からなる上層１８を０．５μｍ程度の厚さで設ける。上
記平坦化層１２を平坦面１２Ｈに加工してから、中間層
１７および上層１８を順次積層すれば、半導体基板１１
の上面に設けられたＡＩ配線１３により生じた段差１４
の影響が中間層１７および上層１８に及ぶことがない。If the upper surface of the flattening layer 12 is processed into a flat surface 12g,
As shown in FIG. 4, an intermediate layer 17 made of polymethylsiloxane, which is a 5i02 layer, is placed on this flat surface 12a at a thickness of 0.3
A fifth layer is provided on this intermediate layer 17 with a thickness of approximately μm.
As shown in the figure, an upper layer 18 made of a patterning resist, which is a resist layer, is provided with a thickness of about 0.5 μm. After processing the flattening layer 12 into a flat surface 12H, if the intermediate layer 17 and the upper layer 18 are sequentially laminated, the semiconductor substrate 11
Step 14 caused by AI wiring 13 provided on the top surface of
This does not affect the middle layer 17 and the upper layer 18.
したがって、上層１８にうねりが生じることがない。つ
まり、半導体基板１１の上面１１ａから上層１８の上面
までの厚さを一定にすることができる。Therefore, no undulations occur in the upper layer 18. In other words, the thickness from the upper surface 11a of the semiconductor substrate 11 to the upper surface of the upper layer 18 can be made constant.
このように、半導体基板１１上に平坦化層１２、中間層
１７および上層１８を順次積層したなら、まず、上層１
８を湿式のリソグラフィー技術でパターン処理（ウェッ
ト現像）したのち、この上層１８をマスクとして中間層
１８にドライエツチングによってパターン転写し、つい
で中間層１７をマスクとして平坦化層１２に同じくドラ
イエツチングによってパターン転写する。そして、最後
に平坦化層１２をマスクとして半導体基板１１にパター
ン転写することで、この半導体基板１１の上面１１ａに
回路パターンを形成することができる。In this way, after the planarization layer 12, intermediate layer 17, and upper layer 18 are sequentially laminated on the semiconductor substrate 11, first, the upper layer 1
8 is subjected to pattern processing (wet development) using wet lithography technology, a pattern is transferred to the intermediate layer 18 by dry etching using this upper layer 18 as a mask, and then a pattern is transferred to the flattening layer 12 by dry etching using the intermediate layer 17 as a mask. Transcribe. Finally, by transferring the pattern onto the semiconductor substrate 11 using the planarization layer 12 as a mask, a circuit pattern can be formed on the upper surface 11a of the semiconductor substrate 11.
上記平坦化層１２、中間層１７および上層１８がなす半
導体基板１１の上面１１ａからの厚さは、上述したよう
に平坦化層１２の上面を平坦面１２ａに研磨加工してか
ら中間層１７、上層１８を設けることで均一とすること
ができる。そのため、パターン転写の光源にｇ線やｉ線
に比べて波長の短いエキシマレーザなどを用いても、焦
点深度や光吸収の影響を受けることなく半導体基板１１
に回路パターンを形成することができる。The thickness of the planarizing layer 12, the intermediate layer 17, and the upper layer 18 from the upper surface 11a of the semiconductor substrate 11 is determined by polishing the upper surface of the planarizing layer 12 into a flat surface 12a as described above. By providing the upper layer 18, uniformity can be achieved. Therefore, even if an excimer laser or the like, which has a shorter wavelength than G-line or I-line, is used as a light source for pattern transfer, the semiconductor substrate 11 is not affected by the depth of focus or light absorption.
It is possible to form a circuit pattern.
なお、上記一実施例では平坦化層を平坦面に加工してか
ら中間層と上層とを順次積層することで上層の平坦化を
計るようにしたが、中間層あるいは上層を平坦面に研磨
加工しても同様の効果を得ることかできる。In the above embodiment, the planarization layer is processed into a flat surface, and then the intermediate layer and the upper layer are sequentially laminated to planarize the upper layer. You can also get the same effect.
また、半導体基板に積層するレジスト層は三層に限られ
ず、二層であってもよい。Further, the number of resist layers stacked on the semiconductor substrate is not limited to three layers, but may be two layers.
［発明の効果］
以上述べたようにこの発明によれば、半導体基板の段差
を有する上面に複数のレジスト層を順次積層し、最上層
のレジスト層から上記半導体基板へパターンを順次転写
する場合に、上記複数のレジスト層のうち、少な（とも
１つのレジスト層の上面を平坦面に研磨加工するように
した。そのため、半導体基板の上面から最上層のレジス
ト層までの厚さを均一にすることができるから、パター
ン形成に用いられる光源の波長が短くなっても、焦点深
度や光吸収の影響を受けることなく均一の深さでパター
ンを形成することができる。[Effects of the Invention] As described above, according to the present invention, when a plurality of resist layers are sequentially stacked on the stepped upper surface of a semiconductor substrate and a pattern is sequentially transferred from the uppermost resist layer to the semiconductor substrate, Among the plurality of resist layers, the upper surface of one resist layer is polished to a flat surface. Therefore, the thickness from the upper surface of the semiconductor substrate to the uppermost resist layer must be made uniform. Therefore, even if the wavelength of the light source used for pattern formation becomes shorter, a pattern can be formed with a uniform depth without being affected by depth of focus or light absorption.
第１図乃至第５図はこの発明によるパターンの形成方法
を順次水した説明図、第６図はうねりの生じた状態で積
層された従来のレジスト層を示す説明図である。
〕
・・・半導体基板、
・・・平坦化層
（レ
ン
ス
上層）
４・・・段差、
７・・・中間層
（Ｓ１０２
層）
８・・・上層
（レジスト層）。FIGS. 1 to 5 are explanatory diagrams sequentially explaining the pattern forming method according to the present invention, and FIG. 6 is an explanatory diagram showing conventional resist layers laminated with undulations. ]... Semiconductor substrate,... Flattening layer (lens upper layer) 4... Step, 7... Intermediate layer (S102 layer) 8... Upper layer (resist layer).
Claims (2)
層を順次積層し、最上層のレジスト層から上記半導体基
板へパターンを順次転写するパターン形成方法において
、上記複数のレジスト層のうち、少なくとも１つのレジ
スト層の上面を平坦面に研磨加工することを特徴とする
半導体基板のパターン形成方法。(1) A pattern forming method in which a plurality of resist layers are sequentially laminated on a stepped upper surface of a semiconductor substrate, and a pattern is sequentially transferred from the uppermost resist layer to the semiconductor substrate, in which at least one of the plurality of resist layers 1. A method for forming a pattern on a semiconductor substrate, the method comprising polishing the top surface of two resist layers into a flat surface.
層構造であることを特徴とする請求項（１）記載の半導
体基板のパターン形成方法。(2) There are three resist layers: a flattening layer, an intermediate layer, and an upper layer.
The method for forming a pattern on a semiconductor substrate according to claim 1, wherein the patterning method is a layered structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2237633A JPH04116918A (en) | 1990-09-07 | 1990-09-07 | Pattern forming method of semiconductor substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2237633A JPH04116918A (en) | 1990-09-07 | 1990-09-07 | Pattern forming method of semiconductor substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04116918A true JPH04116918A (en) | 1992-04-17 |
Family
ID=17018219
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2237633A Pending JPH04116918A (en) | 1990-09-07 | 1990-09-07 | Pattern forming method of semiconductor substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04116918A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005099655A (en) * | 2003-08-21 | 2005-04-14 | Toppan Printing Co Ltd | Method for manufacturing photomask, the photomask, and exposing method thereof |
-
1990
- 1990-09-07 JP JP2237633A patent/JPH04116918A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005099655A (en) * | 2003-08-21 | 2005-04-14 | Toppan Printing Co Ltd | Method for manufacturing photomask, the photomask, and exposing method thereof |
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