JPH04114525A - Radio communication unit - Google Patents

Abstract

PURPOSE:To prevent the deterioration of a radio characteristic by preventing the high harmonic component of a clock from entering into a radio channel band as an interference wave. CONSTITUTION:When the frequency of a high harmonic clock is set to K and a frequency to M, the frequency fCL of the high harmonics is expressed by fCL=n.K/M (n is natural number). When the frequency f1 of respective radio channels is expressed by f1=f0+1.T when the frequency of the radio channel whose frequency is the lowest is set to be f0 and a channel interval to T. For setting the frequency of the high frequency clock so that it can be generated in a position dislocated from the radio channel frequency by T/2, n.K/M=f0+T (1/2+1) can be realized. Consequently, the high frequency clock frequency K comes to K=1/n.M (f0+T(1/2+1)). Thus the deterioration of the radio characteristic is securely prevented if a ceramic vibrator 44 generating the high frequency clock satisfying the expression is selected.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention is applicable to circuits such as microcomputers that operate in synchronization with a clock, such as selective call receivers, mobile phones, and cordless telephones. The present invention relates to a wireless communication device equipped with.

(Prior art) In recent years, with the increase in communication needs and the development of communication circuit technology, various wireless communication devices have been developed, and many of them, such as microcomputers, operate in synchronization with clocks. .

FIG. 3 shows an example of the configuration of a selective call receiver. In the figure, a selective calling signal transmitted from a base station (not shown) is first received by a radio circuit 2 via an antenna 1, then demodulated by a demodulation circuit 3, and introduced into a control circuit 4.

The control circuit 4 is an integrated circuit (L) that performs high-speed signal processing such as establishing synchronization with the selective call signal and error correction processing.
SI) 4a and a microcomputer 4b. In this microcomputer 4b, the individual number code (hereinafter abbreviated as ID code) included in the reception selection call signal is the same as the individual number code of the own machine, which is stored in advance in the individual number code memory (ID-ROM) 5. Verified. If the two codes match as a result of this comparison, it is determined that a call to the own machine has occurred, and a drive signal is output from the control circuit 4 to the drive circuit 6. Therefore, a sound is generated from the speaker 7, and a light emitting diode (LED)
) 8 blinks. Therefore, the holder can know the occurrence of a call by the ringing sound and the flashing of the LED 8.

(Problem to be Solved by the Invention) Incidentally, in recent selective call receivers, the operation of the microcomputer 4b used in the control circuit 4 has been changed in order to cope with higher transmission speeds and higher functionality of selective call signals. The clock frequency is set high, which enables high-speed processing. However, if the clock frequency is set high in this way, the resulting harmonic components may enter the radio channel band that is not intended to transmit the selective call signal, and in this case, they become harmonics or interference waves that interfere with selective call reception. This was extremely undesirable as it deteriorated the radio characteristics of the device.

Therefore, the present invention has focused on the above-mentioned circumstances, and an object of the present invention is to provide a wireless communication device that prevents harmonic components of a clock from entering a wireless channel band as interference waves, thereby preventing deterioration of wireless characteristics.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the present invention provides a circuit that operates in synchronization with a timing signal obtained by frequency-dividing a clock generated from a clock generation means. In a wireless communication device that performs wireless communication by selectively using a plurality of preset wireless channels having a constant frequency interval, the clock oscillation frequency of the clock generation means is K, and the frequency division number is K. M, the frequency of the wireless channel with the lowest frequency among the plurality of wireless channels is f0, and the frequency interval of each of the wireless channels is T, then the clock oscillation frequency K of the clock generation means is K = 1 / n- M(f o + T ・I )(
(n and l are natural numbers) except t: set to any value.

Further, the present invention provides the clock oscillation frequency K of the clock generating means as K −1/n−M (f o + T (1/2
+ 1 ) ) (n and I are natural numbers) is also set to a value that satisfies the following.

(Function) As a result, according to the present invention, by setting the clock oscillation frequency K of the clock generation means to a frequency other than the frequency value obtained by the above formula, the harmonic generation position due to the above clock can be shifted from the radio channel band. It is possible to remove the radio channel and prevent it from entering the wireless channel band. Therefore, the problem that harmonic components of the clock become interference waves and adversely affect the wireless channel is reduced, and thereby it is possible to prevent deterioration of the wireless characteristics.

Also, the clock oscillation frequency K is K-1/n-M (fo+T (1/2+l))(n,
(l is a natural number) By setting the value to a value that satisfies the following, harmonics caused by the clock will be generated at a central position between a plurality of wireless channels. Therefore, the influence of harmonics on the radio channel is minimized, and as a result, deterioration of radio characteristics can be most reliably prevented.

(Embodiment) Next, an embodiment in which the present invention is applied to a selective call receiver will be described.

FIG. 1 is a circuit block diagram showing the configuration of a selective calling receiver in this embodiment. In this figure, the same parts as those in FIG. 3 are given the same reference numerals and detailed explanations will be omitted.

The control circuit 40 is an integrated circuit (LSI) 4 that performs high-speed arithmetic processing such as establishing synchronization and error correction for selective call signals.
0a, a microcomputer 40b that performs control related to ID code verification and call notification, and a ceramic vibrator 44.

The microcomputer 40b includes a CPU 41, a timing generation circuit 42, and a clock generation circuit 43. The CPU 41 includes an arithmetic unit (ALU), an accumulator, an instruction decoder, a program counter, various registers, an I10 port, a program ROM, and a data R
Equipped with AM. The clock generation circuit 43 has a pair of external connection terminals XIN and X0UT, and the ceramic resonator 44 is connected to the external connection terminals XIN and X0UT. The clock generation circuit 43 then energizes the ceramic resonator 44 to generate a high frequency clock. The timing generation circuit 42 generates a plurality of types of system clocks required by the CPU 41 by, for example, dividing the high frequency clock, and supplies these system clocks to the CPU 41.

By the way, the selective calling receiver of this embodiment is configured to be able to selectively use a plurality of radio channels arranged at constant frequency intervals by using a frequency synthesizer. On the other hand, when a high frequency clock is generated, harmonics determined by the frequency of this high frequency clock and the frequency division number of the timing generation circuit 42 are generated. Therefore, depending on the relationship between the frequency value of each of the above radio channels, the value of the high frequency clock frequency and the value of the frequency division number, the harmonic frequency may match or be close to the frequency of each of the above radio channels, resulting in It is quite conceivable that the radio channel signal will be interfered with by the above-mentioned harmonics.

Therefore, in this embodiment, the frequency of the high-frequency clock is adjusted so that the harmonics generated by the clock do not match the frequencies of each radio channel, specifically, so that the harmonics are generated at the center position between each radio channel. I'm trying to set it up. That is, for example, if the frequency of the high-frequency clock is K
, where the frequency division number is M, the harmonic frequency fcL is expressed as fo, -n-K/M (n is a natural number).

On the other hand, the frequency fl of each wireless channel is the frequency of the lowest frequency wireless channel f. If the closing and channel spacing is T, it is expressed as f,=fo+l-T (1 is a natural number).

Now, in order to set the frequency of the high-frequency clock so that the harmonic is generated at a central position between each radio channel, that is, at a position shifted by T/2 from the radio channel frequency, n-K/M- f o 10T/2 +l reference T-
f. It is sufficient if 10T (1/2+l) holds true.

Therefore, from this formula, the high frequency clock frequency is: K = 1/n-M (f o + T (1/
2 + l )). By selecting a ceramic resonator 44 that generates a high-frequency clock that satisfies this equation, it is possible to prevent harmonics generated by the clock from coinciding with each radio channel frequency.

Because of this configuration, the position of the harmonic generated by the high-frequency clock is always at the center position between the two radio channels, that is, at a position separated by T/2 from the radio channel frequency, as shown in Figure 2, for example. become. Therefore, there is no need to worry about harmonics entering the radio channel as interference waves, thereby reliably preventing deterioration of radio characteristics. In addition, by setting the harmonics to be generated at the center position between the two wireless channels as described above, even if the band of each wireless channel is wide, the effect of harmonics on each wireless channel is minimized. can be suppressed to

However, the present invention is not limited to the above embodiments. For example, in the above embodiment, the frequency of the high frequency clock is set so that harmonics are generated at the center position between two wireless channels, or when the interval between wireless channels is wide, or when the band of a wireless channel is narrow. In this case, the frequency of the high-frequency clock may be set so that harmonics are generated at an arbitrary position shifted toward the radio channel frequency from the center position between the two radio channels.

Further, in the above embodiments, the present invention has been explained by taking as an example a case where the present invention is applied to a selective call receiver, but for example, a mobile telephone, a car telephone, a cordless telephone, a wireless terminal device for a teleterminal system, a wireless communication system for a multi-channel access system, etc. The present invention may also be applied to other wireless communication devices using a microcomputer such as a wireless communication device.

In addition, the configuration of the clock generating means, the type of clock oscillator, etc. can be modified in various ways without departing from the spirit of the present invention.

[Effects of the Invention] As detailed above, according to the present invention, the clock oscillation frequency of the clock generation means is K, the frequency division number is M, and the frequency of the lowest frequency radio channel among the plurality of radio channels is fo. , where T is the frequency interval of each of the radio channels, the clock oscillation frequency K of the clock generation means is
k −1/n−M(fo 1T ・l)(n
By setting it to any value except l (where l is a natural number),
It is possible to prevent clock harmonic components from entering the wireless channel band as interference waves, thereby providing a wireless communication device that can prevent deterioration of wireless characteristics.

[Brief explanation of drawings]

FIG. 1 is a circuit block diagram showing the configuration of a selective call receiver which is a wireless communication device in an embodiment of the present invention, and FIG. 2 is a circuit block diagram showing the position of harmonics generated by the selective call receiver. 3 are circuit block diagrams showing an example of the configuration of a conventional selective call receiver. 1. Antenna, 2. Radio circuit, 3. Demodulation circuit, 5
...Individual number code memory (ID-ROM), 6..Drive circuit, 7..Speaker, 8..Light emitting diode (LE)
D), 40...control circuit, 40a...integrated circuit (
LS I), 40b・Microcomputer, 41・
...CPU, 42...Timing generation circuit, 43...
- Clock generation means, 44...ceramic resonator. Applicant's agent Patent attorney Takehiko Suzue

Claims (2)

[Claims] (1) Equipped with a circuit that operates in synchronization with a timing signal obtained by frequency-dividing the clock generated from a clock generation means, and selectively operates a plurality of preset wireless channels with constant frequency intervals. In the wireless communication device used for wireless communication, the clock oscillation frequency of the clock generation means is K, the frequency division number is M, and the frequency of the lowest frequency wireless channel among the plurality of wireless channels is f_0.
When the frequency interval of each wireless channel is T, the clock oscillation frequency K of the clock generation means is set to any value except K=1/n・M(f_0+T・l) (n, l are natural numbers). A wireless communication device characterized by being configured. (2) Set the clock oscillation frequency K of the clock generating means to K=1/n・M(f_0+T(1/2+l))(n,l
is a natural number).