JPS6346829A - Clock generating circuit for control circuit of multi-channel receiver - Google Patents

Abstract

PURPOSE:To eliminate the need for a strict shield device between a reception circuit and a control circuit by deviating a clock signal frequency so as to avoid harmonics of a clock signal frequency from being invaded in using a channel onto which the harmonics are invaded. CONSTITUTION:In using 15MHz for a frequency of a clock signal 7 and selecting a reception frequency range of 800-820MHz of a reception circuit 1, since a frequency 810MHz being 54 times the frequency of the signal 7 is invaded in the reception frequency range of the circuit 1, if a channel using 810MHz is received, the channel is subject to disturbance. In this case, the system is preset so as to send a clock frequency switching signal 6 only when the set signal of the channel is sent to activate a switch element S of a frequency switching circuit 4b and to connect a capacitor C thereby varying the oscillated frequency of the clock frequency oscillation circuit 4a. In the multi-channel receiver of the constitution above, the disturbance is not exerted by deviating the frequency by nearly 25kHz. Thus, no tight shield structure between the circuit 1 and a control circuit 2 is required.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a control circuit for a multi-channel receiving device for mobile stations such as car telephones in the extremely high frequency band.

(Prior Art) A control circuit of a multi-channel receiving device used in a mobile station such as a car telephone in the ultra-high frequency band is provided to decode various data transmitted from a base station and perform various controls, and is equipped with a CPU, etc. It is composed of logic circuits. These logic circuits operate based on a clock signal from a clock generation circuit, and the frequency of the clock signal is determined taking into consideration the processing capacity of the control circuit, but is generally between several MHz and 10-odd MHz.
It is z.

On the other hand, since the reception frequency bandwidth of a multi-channel receiver in the extremely high frequency band extends over 20 MHz, if such a control circuit is provided in such a multi-channel receiver, the high-order harmonics of the clock signal frequency will be It matches the receiving frequency of a specific channel of the receiving device, and causes sensitivity degradation in that channel. If the value of the clock signal frequency is smaller than the value of the receiving frequency bandwidth of the receiving device, no matter how the clock signal frequency is selected, higher harmonics of the clock signal frequency are always transmitted to the receiving device. It will fall within the receiving frequency range of the device.

In such a case, even if a clock generation circuit with few harmonics is used, since harmonics are generated in the logic circuit, it is unavoidable that high-order harmonics fall into the receiving frequency range.

In order to avoid this, conventionally, receiving apparatuses have been constructed using a structure that strictly shields between the control circuit and the receiving circuit.

(Problem to be Solved by the Invention) However, as mentioned above, in order to prevent high-order harmonics of the clock signal frequency from entering the receiving circuit, a strict shield is provided between the control circuit and the receiving circuit. However, there was a problem in that it was difficult to make the receiving device ultra-small and lightweight.

An object of the present invention is to provide a control circuit that does not cause deterioration in the sensitivity of the receiving circuit even without the above-mentioned strict shielding structure.

(Means for Solving the Problem) The present invention uses a specific channel in which high-order harmonics of the clock signal frequency, which is the output frequency of the clock generation circuit, are received close to the receiving frequency of the receiving circuit. When doing so, a clock frequency switching signal is sent in conjunction with the specific channel setting signal sent from the logic circuit, and the frequency switching circuit of the clock generation circuit is driven to slightly change the clock signal frequency. This is to prevent high-order harmonics from falling into the set specific channel.

(Function) Since the output frequency of the clock generation circuit is obtained from the crystal oscillation circuit, frequency deviation and frequency stability are maintained well, but it is possible to change the capacitance of the capacitor connected in series with the crystal resonator. The oscillation frequency can be changed by

Also, it is possible to determine by simple calculation which channel within the receiving frequency range the high-order harmonics of the clock signal frequency fall on, so when using that channel, it is linked to the channel setting signal sent by the logic circuit. A clock frequency switching signal is preset so as to be sent out, and the frequency switching circuit is driven by the switching signal to switch the capacitance of the capacitor connected in series to the crystal resonator to change the clock signal frequency. can be switched so that higher harmonics of the clock signal frequency do not fall into the set channel.

(Embodiment) FIG. 1A is a block diagram of a multi-channel receiving apparatus using an embodiment of the present invention, and FIG. 1A is a circuit diagram of a clock generation circuit according to an embodiment of the present invention.

In FIG. 1a, 1 is a receiving device, 2 is a control circuit, 3 is a logic circuit, 4 is a clock generation circuit, 5 is a channel setting signal, 6 is a clock frequency switching signal, and 7 is a clock signal.

In Figure 1, 4a is a clock frequency oscillation circuit, 4b
is a frequency switching circuit, C is a capacitor, S is a switch element, and X is a crystal resonator.

An embodiment of the invention will be described with reference to FIGS. 1a and 1b. The receiving circuit 1 receives and demodulates radio signals transmitted from the base station, and uses a large number of channels by switching between them. The control circuit 2 consists of a logic circuit 3 and a clock generation circuit 4, and automatically searches for a control channel for line setting, receives the demodulated signal from the receiver circuit 1, and decodes the data.
In addition to transmitting a channel setting signal 5 for setting a communication channel according to instructions from the base, it also performs various controls. The clock generation circuit 4 is a circuit that is necessary for the operation of the logic circuit 3 and generates a lock signal 7. As shown in FIG. By operating the switching element S of the frequency switching circuit 4b, the frequency of the υ clock signal 7 is changed by connecting the capacitor C connected in series to the crystal resonator X.

Hereinafter, specifically, the frequency of the clock signal 7 is set to 15M1 (z
and the receiving frequency range of receiving circuit 1 is 800 to 820.
The case of MHz will be explained.

Harmonic 1 which is 54 times the frequency of clock signal 7 in this case
5 FviHz
When receiving a channel containing 0 Ml(z), the harmonics will interfere and cause interference.

Since the reception channel is set according to the designation from the base station, it is natural that it may be set to the channel that is subject to the above-mentioned 810 MHz interference.

In such a case, the logic circuit 3 is reset so that the clock frequency switching signal 6 is sent out only when the setting signal of the channel is sent out, and the switching element S of the frequency switching circuit 4b is operated KJh. , capacitor C
The oscillation frequency of the clock frequency oscillator circuit 4a is changed by using . The amount of change in the oscillation frequency depends on the single signal selectivity characteristics of the receiving circuit 1, but in a multi-channel receiving device such as the one according to the present invention, the interference wave that causes sensitivity deterioration is approximately 25 KHz. By shifting it, it will not be affected at all. Therefore, if we shift 25 KHz at 81 Q MHz, then 25 KHz7810 MH
It is sufficient to change z curvature by 3 x 10-5. When applied to clock frequency 15 MHz, 15X106X3X10
==450Hz. To provide this degree of frequency change, add a small capacitor C (before and after IOPF) in series with the crystal oscillator X of the 4c clock frequency oscillation circuit 4a, as shown in Figure 1. It is possible by or,
The frequency switching circuit 4b shown in FIG. 1 is an example, and the switching element S may be of various known types.The object of the present invention can be achieved by using any type of switching element S.

Note that the lock signal frequency is determined by the processing capacity of the control circuit 2, and as long as frequency stability, output level, etc. are ensured, even if the frequency is changed to the extent described above, the operation of the control circuit will not be affected. There is no problem at all.

(Effects of the Invention) As explained in detail above, according to the present invention, when a frequency switching circuit is added to a clock frequency oscillation circuit and a channel in which high-order harmonics of the clock signal frequency drop is used, the channel A clock frequency switching signal is transmitted in conjunction with the setting signal transmission, and the frequency switching circuit is driven to shift the clock signal frequency to prevent harmonics of the clock signal frequency from falling into the channel. Since there is no need for a strict shielding mechanism between the circuit and the control circuit, a significant effect can be expected in realizing ultra-miniaturization of the receiving device. In addition, the shielding mechanism is not required, and the decoupling circuit that prevents leakage from the connecting cable can be simplified, which greatly reduces the weight and cost of multi-channel receivers in the ultra-high frequency band. effective.

[Brief explanation of the drawing]

FIG. 1A is a block diagram of a multi-channel receiver using an embodiment of the present invention, and FIG. 1A is a circuit diagram of a clock generation circuit according to an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Receiving circuit, 2... Control circuit, 3... Logic circuit, 4... Clock generation circuit, 5... Channel setting signal, 6... Clock frequency switching signal, 7... Clock signal, 4a... Clock frequency oscillation circuit, 4b
...Frequency switching circuit, C...capacitor, S...
Switch element, X...Crystal oscillator. Figure 1a is a circuit diagram of a black/reverse generation circuit in a multi-channel receiving device using an embodiment of the present invention.Figure 1b

Claims (1)

[Scope of Claims] A multi-channel receiving device comprising a control circuit including a logic circuit and a clock generation circuit, and a reception circuit, in which the high-order harmonics of the clock signal frequency output from the clock generation circuit interfere with each other. The logic circuit is provided with means for transmitting a signal for switching the clock signal frequency in conjunction with the transmission of a signal for setting a specific channel of the receiving circuit, and a means for switching the clock signal frequency in response to the switching signal is provided in the logic circuit. A clock generation circuit for a control circuit of a multi-channel receiving device, characterized in that the clock generation circuit is provided in the generation circuit.