KR100388974B1 - A control circuit and a control method of local oscillator for wll system - Google Patents

Abstract

BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a local oscillator control circuit for use in a modulator of a high frequency part of a radio communication device, and more particularly, to a local oscillator control having good noise characteristics and capable of miniaturization. A modulation unit for upconverting and downconverting a signal includes: a clock oscillator for outputting a predetermined allocated fixed clock signal; A controller configured to generate and output a system clock signal, a data signal, and a latch enable signal using the clock signal output from the clock oscillator; When the system clock signal, the data signal, and the latch enable signal output from the control unit are input and the set local oscillation frequency is output, respectively, and the set local oscillation frequency is output, the high level LED signal is output to the control unit. The high frequency local oscillator and the first and second intermediate frequency local oscillator are included to reduce the size of the local oscillator control circuit. Since there is no malfunction caused by this, there is an effect of providing a circuit in which the reliability is improved.

Description

Local oscillator control circuit of wireless communication device and its control method {A CONTROL CIRCUIT AND A CONTROL METHOD OF LOCAL OSCILLATOR FOR WLL SYSTEM}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a local oscillator control circuit for use in a modulator of a high frequency portion of a wireless communication device such as a wireless subscriber network (WLL), and more particularly, to a local oscillator control having good noise characteristics and miniaturization.

Wireless communication devices, such as wireless local loops (WLLs), form a line between a telephone company and subscriber terminals using a wireless system instead of wires. It is proposed to reduce the enormous cost of making a phone call in a less dense area.

The wireless subscriber network as described above has an advantage in that it is easy and simple to establish a subscriber line because it is connected wirelessly, compared to the existing wired network that connects the subscriber terminal to the subscriber terminal by wire, and the time required for starting the service is shortened.

In addition, it has strengths in terms of service continuity, such as being used as an emergency subscriber line in case wired network is damaged due to natural disaster, etc., and can provide various services such as data service, ISDN, etc. in addition to general voice telephone service. .

In addition, the installation cost is almost constant regardless of the installation distance, the investment cost is reduced, the return on investment is fast, and the communication network can be quickly expanded as the number of subscribers increases.

Wireless subscriber network (WLL) is the most promising way for new local telephone operators or new carriers to establish subscriber networks early. Especially, it is widely applied as a base communication system in developing countries where wired network infrastructure is weak. It is becoming.

On the other hand, a wireless communication device such as a wireless subscriber network has characteristics similar to a mobile communication network in terms of using a wireless channel as a communication medium, but has a merit that it is much better than a radio environment of a mobile communication network because of its lack of mobility, and mainly uses a CDMA cellular system. Apply by application.

In Korea, a wireless communication device WLL, commonly referred to as a "wireless subscriber line" or "wireless subscriber network", is a radio in the loop (RITL), fixed radio access (FRA), fixed wireless access (FWA), or fixed cellular (FCS). System) has various names.

As described above, since the wireless subscriber network wirelessly connects each subscriber with a line, an up converter for converting a voice signal into a radio frequency (RF) signal and a down converter for converting a high frequency signal into a voice signal. Is required, and the local oscillator, which is a reference of the modulation frequency, is an essential element of the up-down modulator.

Hereinafter, a local oscillator control circuit of a wireless communication apparatus according to the prior art will be described with reference to the accompanying drawings.

1 is a configuration diagram of a local oscillator control circuit of a wireless communication device according to the prior art.

Referring to FIG. 1, the local oscillator control circuit of a wireless communication device such as a wireless subscriber network according to the prior art controls an entire high frequency unit to which a high frequency signal is processed and simultaneously monitors an operation state, and various control data are stored. A ROM 30; A control unit 10 including a CPU 40 for monitoring and controlling each functional unit by using the control data stored in the ROM 30;

A local oscillator for converting a high frequency signal into a voice signal and a voice signal into a high frequency signal by the control of the control unit 10,

A high frequency local oscillator 50 for up and down modulation of a radio frequency (RF) signal,

The first and second intermediate frequency local oscillators 60 and 70 are configured for uplink and downlink modulation of an intermediate frequency (IF) signal.

The high frequency local oscillator 50 and the first and second intermediate frequency local oscillators 60 and 70 gather together to form a modulation unit 20.

Hereinafter, a local oscillator control circuit of a wireless communication device such as a wireless subscriber network (WLL) according to the related art having the above configuration will be described in detail with reference to FIG.

The modulation unit 20 and the control unit 10 are each composed of a separate unit, and a separate cable 80 is used for transmission of control signals or data signals.

The high frequency local oscillator 50 and the first and second intermediate frequency local oscillators 60 and 70 use a phase locked loop (PLL) circuit to output a corresponding local oscillation frequency, and the allocated local oscillation. In order to generate and output a frequency, a corresponding control signal must be applied from the control unit 10.

The control unit 10 retrieves and processes the data stored in the ROM 30 by the CPU 40 in order to control the output frequencies of the local oscillation units 50, 60, 70 constituting the modulation unit 20. After that, the control signal is output to the local oscillation units 50, 60 and 70 constituting the modulation unit 20.

The control signal output from the control unit 10 is output to the modulation unit 20 through a cable 80, and outputs a clock signal CLK, a data signal DATA, and a latch enable signal.

The modulation unit 20 is said to be locked when outputting the local oscillation signal assigned by the control signal output from the control unit 10. When the lock is made, each of the modulation unit 20 The local oscillators 50, 60 and 70 output LD (Lock Detect) signals to the control unit 10 in a high level state.

When the control unit 10 receives the LD signal in the high state, the control unit 10 no longer outputs the control signal, that is, the clock signal CLK, the data signal DATA, and the LE signal. Do not.

However, in the above-described conventional technology, the control unit 10 and the modulation unit 20 are separated by separate circuit boards, and are connected through a cable 80, thereby transmitting data by noise or the like. There was a problem that an error occurred in the signal.

In addition, the ROM 30 and the CPU 40 constituting the control unit 10 are relatively expensive components, which causes a problem of increasing the price of the control unit 10.

SUMMARY OF THE INVENTION An object of the present invention is to provide a control circuit for outputting an error-free frequency and a control method thereof by configuring a control circuit capable of controlling each of the intermediate frequency oscillators for outputting the assigned intermediate frequency, within the modulation unit.

In order to achieve the above object, the present invention provides a local oscillator control circuit of a wireless subscriber network, wherein a modulation unit for upconverting and downconverting an applied signal includes: a clock oscillator for outputting a predetermined fixed clock signal; Wow; A controller configured to generate and output a system clock signal, a data signal, and a latch enable signal using the clock signal output from the clock oscillator; When the system clock signal, the data signal, and the latch enable signal output from the control unit are input and the set local oscillation frequency is output, respectively, and the set local oscillation frequency is output, the high level LED signal is output to the control unit. A local oscillator control circuit comprising a high frequency local oscillator, first and second intermediate frequency local oscillators, is included.

In addition, in the local oscillator control circuit of a wireless subscriber network, a modulation unit for upconverting and downconverting an applied signal; A first step of receiving a clock signal from the clock oscillator to the controller; The controller may include a second step of determining whether an LED signal is input as a low level signal from the high frequency local oscillator and the first and second intermediate frequency local oscillators; In the case where the LED signal input to the controller is determined at the low level in the second step, the data unit and the latch unit are controlled to output a data signal and a latch enable signal, respectively, and a system clock signal is output. In the case of the high level, a local oscillator control method comprising a third step of blocking output of a data signal, a latch enable signal, and a system clock signal is provided.

1 is a configuration diagram of a local oscillator control circuit of a wireless communication device according to the prior art,

2 is a functional block diagram of a local oscillator control circuit according to the present invention;

3 is a detailed functional block diagram of a control unit according to the present invention;

4 is a timing diagram of signals generated according to an example of the present invention;

5 is a flow chart of a local oscillator control method according to the present invention.

** Explanation of symbols on the main parts of the drawing **

10: control unit 20: modulation unit

30: rom 40: cpu

50,55: high frequency local oscillator 60,65: first intermediate frequency local oscillator

70, 75: Second intermediate frequency local oscillator 80: Cable

90: circuit pattern 100: control unit

102: data part 104: dispensing part

106: latch portion 110: clock generator

Hereinafter, a local oscillator control circuit and its control method of a wireless communication device according to the present invention will be described with reference to the accompanying drawings.

2 is a functional block diagram of a local oscillator control circuit according to the present invention, FIG. 3 is a detailed functional block diagram of a control unit according to the present invention, and FIG. 4 is one of the present invention. 5 is a timing diagram of a signal generated by an example, and FIG. 5 is a flowchart of a local oscillator control method according to the present invention.

2 to 3, the local oscillator control circuit according to the present invention comprises: a local oscillator control circuit of a wireless subscriber network, comprising: a modulation unit for up- and down-converting an applied signal; A crystal clock oscillator 110 which is made of a crystal (X-tal) and outputs a predetermined fixed clock signal (CLK);

The crystal clock oscillator 110 generates and outputs a system clock signal SYS_CLK, a data signal DATA, and a latch enable signal using the clock signal CLK output from the crystal clock oscillator 110. A divider 104 which receives a clock signal CLK input from the clock oscillator 110, divides the signal into half-cycle signals, and outputs a system clock signal SYS_CLK; A data unit 102 for generating and outputting a predetermined set data signal DATA by counting the system clock signal SYS_CLK output from the division unit 104; A latch unit 106 for generating and outputting a predetermined latch enable (LE) signal by receiving and counting the system clock signal SYS_CLK output from the division unit 104 is included. A controller 100 formed of a programmable logic device),

The system clock signal SYS_CLK, the data signal DATA, and the latch enable signal LE output from the controller 100 are respectively input, and the corresponding local oscillation frequencies are respectively output. When outputting normally, a high level (LD) lock output signal is output to the controller 100, and when the set local oscillation frequency cannot be output normally, a low level LED And a high frequency local oscillator 55 and a first and second intermediate frequency local oscillators 65 and 75 for outputting an LD signal to the control unit 100.

4 is an example of timing configuration of signals output from each functional unit according to the configuration of the present invention.

Referring to FIG. 5, the local oscillator control method according to the present invention is a local oscillator control circuit of a wireless subscriber network, by a modulation unit for up- and down-converting an applied signal.

A first step S10 of receiving a clock signal CLK from the crystal clock oscillator 110 to the controller 100,

The controller 100 determines whether an LD signal is input as a low level (0) signal from the high frequency local oscillator 55 and the first and second intermediate frequency local oscillators 65 and 75. Step S20,

In the second step S20, when the LD signal input to the controller 100 is at a low level, the data unit 102 and the latch unit 106 are controlled to respectively control the data. Outputs the signal DATA and the latch enable signal LE, and at the same time outputs the system clock signal SYS_CLK. When the LD signal is at a high level, the data signal DATA and latch-in are output. A third step S30 for blocking output of the enable signal LE and the system clock signal SYS_CLK is included.

Hereinafter, a local oscillator control circuit and a method of controlling the same according to the present invention having the above configuration will be described in detail with reference to the accompanying drawings.

The crystal clock oscillator 110 outputs a clock signal CLK of a predetermined predetermined frequency by using a crystal (X-tal) generally called crystal as an oscillator and applying a constant electrical signal from the outside. .

The clock signal CLK output from the crystal clock oscillator 110 is applied to the controller 100, and the controller 100 inputs the input clock signal CLK to the frequency divider 104 so that 1 //. The clock signal is divided into two cycles and output.

That is, the divider 104 receives the clock signal CLK output from the crystal clock oscillator 110 and outputs a system clock signal SYS_CLK. The high frequency local oscillator 55, the first and the second 2 The system clock signal SYS_CLK is output only when the LD signal output from the intermediate frequency local oscillator 65 or 75 is low level.

The system clock signal SYS_CLK output from the frequency divider 104 is input to the high frequency local oscillator 55 and the first and second intermediate frequency local oscillators 65 and 75, respectively, and the data portion 102 is provided. And input to the latch section 106, respectively.

The data part 102 processes the system clock signal SYS_CLK applied from the frequency divider 104 and transmits a corresponding data signal DATA to the high frequency local oscillator 55 and the first and second intermediate frequencies. Output to the local oscillator 65 and 75, respectively, as an example, the data signal DATA is as shown in FIG.

The latch unit 106 also processes the system clock signal SYS_CLK applied from the divider 104 to generate a corresponding latch enable signal LE to generate the high frequency local oscillator 55, the first and the first and the like. Output to the second intermediate frequency local oscillator 65, 75, respectively, the latch enable (LE) signal, as an example, as shown in Figure 4.

Each of the high frequency local oscillator 55 and the first and second intermediate frequency local oscillators 65 and 75 may include a system clock signal SYS_CLK, a data signal DATA, and a latch enable signal, which are output from the controller 100. LE) is input, and generates and outputs each local oscillation frequency signal assigned thereto.

When the high frequency local oscillator 55 and the first and second intermediate frequency local oscillators 65 and 75 output the assigned predetermined frequency signals by using a built-in phase locked loop, a local frequency signal is output. A High Level (LD) Locking Enable (LD) signal to be outputted is output to the controller 100.

The high level LD signal is applied to the division unit 104 of the controller 100, and the division unit 104 receiving the LED signal is output from the crystal clock oscillator 110. By blocking the input of the clock signal CLK, the system clock signal SYS_CLK generated by dividing the clock signal is not output.

Since the controller 100 receives the LD signal, the control unit 100 receives the data signal Data, the system clock signal SYS_CLK, and the latch-in enable signal LE from the high frequency local oscillator 55 and the first and second signals. Output to the second intermediate frequency local oscillator 65,75 is not possible, respectively.

When the high frequency local oscillator 55 and the first and second intermediate frequency local oscillators 65 and 75 generate and output the corresponding frequency signal, the data signal Data and the system clock signal SYS_CLK are generated. Even without receiving the latch-in enable signal LE, the corresponding frequency signal is continuously output by the PLL configured therein.

The control unit 100 is simply configured by a programmable logic device (PLD), and the crystal clock oscillator 110, the control unit 100, the high frequency local oscillator 55, the first and second intermediate frequency local oscillator The 65 and 75 are configured in one circuit board and transmit each signal by a circuit pattern formed on the circuit board, so that noise is not introduced from the outside and malfunctions are caused. It does not occur.

According to another aspect of the present invention, in the local oscillator control method, as shown in FIG. 5, the controller 100 receives the clock signal CLK from the crystal clock oscillator 110 (S10) and the data signal (Data). ), The system clock signal SYS_CLK and the latch-in enable signal LE are outputted to the high frequency local oscillator 55 and the first and second intermediate frequency local oscillators 65 and 75, respectively. The oscillator 55 and the first and second intermediate frequency local oscillators 65 and 75 output the allocated corresponding frequency signals (S10).

The controller 100 determines whether an LD signal is output at a low level from the high frequency local oscillator 55 and the first and second intermediate frequency local oscillators 65 and 75 (S20). When the LD signal is at a low level, the data signal DATA, the system clock signal SYS_CLK, and the latch enable signal LE are output (S30), and the LED signal is high. When input as a high level signal, output of the data signal DATA, the system clock signal SYS_CLK, and the latch enable signal LE is stopped.

Since the present invention of the above-described configuration does not use expensive ROM 30 and CPU 40 as in the prior art, it is possible to reduce the price, and there is no malfunction or error due to noise, and can be miniaturized. There is this.

The present invention having the above configuration has the effect of making the size of the local oscillator control circuit smaller and lower cost in the up and down modulation apparatus of the wireless subscriber network high frequency device.

In addition, since each signal is transmitted using a circuit pattern, external noise does not flow, and there is no malfunction caused by noise, thereby providing a circuit having improved reliability.

Claims (5)

In the local oscillator control circuit of the wireless communication device, the modulation unit for upconverting and downconverting the applied signal, A clock oscillator for outputting a predetermined fixed clock signal; A controller configured to generate and output a system clock signal, a data signal, and a latch enable signal using the clock signal output from the clock oscillator; When the system clock signal, the data signal, and the latch enable signal output from the control unit are input and the set local oscillation frequency is output, respectively, and the set local oscillation frequency is output, the high level LED signal is output to the control unit. A local oscillator control circuit of a wireless communication device, comprising: a high frequency local oscillation unit, and first and second intermediate frequency local oscillation units. The method of claim 1, wherein the control unit, A divider for receiving a clock signal input from the clock oscillator and dividing the clock signal into a system clock signal at a half cycle and outputting the divided clock signal; A data unit for generating and outputting a predetermined set data signal by receiving and counting a system clock signal output from the division unit; And a latch unit for generating and outputting a predetermined latch enable signal by receiving and counting a system clock signal output from the division unit, the local oscillator control circuit of the wireless communication device. The method of claim 1, wherein the control unit, The local oscillator of the wireless communication device characterized in that the output of the system clock signal, data signal, latch enable signal is blocked by blocking the clock signal input from the clock oscillator when the LED signal is input in the high level state. Control circuit. According to claim 1, The control unit is made of PDL, The control unit, the high frequency local oscillator, the first and second intermediate frequency local oscillator are integrally formed using the same circuit board, Local oscillator control circuit of a wireless communication device, characterized in that for transmitting the respective signals assigned by a plurality of circuit patterns formed on the circuit board. In the local oscillator control circuit of the wireless subscriber network, the modulation unit for up-converting and down-converting the applied signal, A first step of receiving a clock signal from a clock oscillator to a controller; The controller may be configured to determine whether an eld signal is input as a low level signal from the high frequency local oscillator and the first and second intermediate frequency local oscillators; In the case where the LED signal input to the controller is determined at the low level in the second step, the data unit and the latch unit are controlled to output a data signal and a latch enable signal, respectively, and a system clock signal is output. And a third step of interrupting the output of the data signal, the latch enable signal, and the system clock signal in the case of the high level.