JPH04114285A - Picture data processor - Google Patents

Abstract

PURPOSE:To enable a sufficient general picture processing while processing a picture data at a video rate by fetching the picture data in a small area allocated to a module itself by each processor module and defining it as a processing object. CONSTITUTION:This device is composed of plural processor modules 2 to parallelly fetch the picture data outputted from video equipments 1 and 3, to execute the picture processing and to parallelly output the obtained picture data. Each processor module 2 is equipped with an interface means 6 having a means 13 to fetch the picture data of the small area in a picture window, which can be arbitrarily allocated, and a means 14 to output the picture data in the picture window to which the picture processing is executed. Therefore, the picture data in the small area to enable a video rate processing due to a software is fetched and the picture data in the small area, to which the general picture processing is executed by the software, is outputted. Thus, the general picture processing can be executed while processing the picture data at the video rate.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to an image data processing device that processes image data output from video equipment, and aims to process the image data at video rate while performing general-purpose image processing. The image data processing device is configured with a plurality of processor modules that take in image data output from a video device in parallel, perform image processing on the image data, and output the image data obtained through the image processing in parallel. , an ink face means in which each processor module is provided with means for capturing image data of a small area within an image window that can be arbitrarily allocated, and means for outputting image data within the image window subjected to image processing. By being equipped with this feature, the system is configured to import small area image data that can be processed at video rate using software, and to output small area image data that has been subjected to general-purpose image processing using software. Configure.

[Industrial application field]

The present invention relates to an image data processing device that can perform general-purpose image processing while processing image data output from video equipment at a video rate.

In recent years, image processing technology has been used in various fields to perform computer processing on image data captured from image input devices such as TV cameras. This image processing technology requires the execution of video rate processing (a processing method that directly processes image data from an image input device) to enable real-time processing, and is also expected to be applied to various fields. To make this possible, image processing operations must be made more versatile. These two requirements, high speed and versatility, are mutually contradictory requirements due to the extremely large amount of information in image data, but future image data processing devices will meet these contradictory requirements. It is necessary to build an architecture that can meet the two demands of high speed and versatility.

[Prior Art] In conventional image data processing devices, since video rate processing cannot be realized by image processing operations using software, a method has been adopted in which image processing operations are realized by a hardware mechanism. However, in the image processing operation using the hardware mechanism, the content of the image processing operation becomes fixed, so there is a problem that it is not possible to respond to different types of image processing requests at all.

Therefore, as disclosed in Japanese Unexamined Patent Application Publication No. 13379/1982, the present applicant has developed an image data processing device that includes a plurality of hardware modules that perform various image processing operations, and arbitrary communication between these hardware modules. By configuring a network circuit that can be combined with a network circuit and a network control unit that controls this network circuit, pipeline processing of arbitrary image processing operations can be realized, achieving high-speed image processing and versatility. He proposed an image data processing device that could be used as an image data processor.

[Problem to be solved by the invention]

Although it is true that the invention disclosed in Japanese Patent Application Laid-open No. 13379/1983 disclosed by the present applicant was able to achieve high speed and a certain degree of versatility, basically the image processing operation is performed by a hardware mechanism. From the fact that it is running,
It could not be said that it had sufficient versatility.

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a new image data processing device that can perform sufficient general-purpose image processing while processing image data at video rate. be.

[Means to solve the problem]

FIG. 1 is a diagram showing the principle configuration of the present invention.

In the figure, 1 is a video device such as a TV camera, which continuously outputs image data, and 2 is a processor module provided with a plurality of video devices.
A device that executes general-purpose image processing operations in parallel on the image data output by 3, and 3 is a video device such as a TV, which displays the image data that has been subjected to image processing operations. , 4 is the video equipment 1 and the processor module.
A first video bus 5 connects between the video equipment 3 and the processor module 2;

Each processor module 2 is in charge of the process of capturing image data sent from the video equipment 1, and also includes an interface means 6 that is in charge of outputting the image data that has been subjected to image processing, and an interface unit 6 that handles the process of capturing image data sent from the video equipment 1. a first memory 7 for storing data; an image processing execution means 8 configured by software means for performing general-purpose image processing operations on the image data stored in the first memory 7; The second memory 9 stores the image data to be output processed by the means 8.

The interface means 6 includes an address generation means 1° that generates a pulse signal train for displaying pixel position information of image data from an image signal sent from the video equipment 1, and an address generation means 10 in order to execute the interface process. The pixel position in the image window to which the pulse signal train output from the address generation means lo is allocated is inputted by the pulse signal train outputted by the address generating means lo, the reference position information of the image window arbitrarily allocated, and the size information of the image window. A capture signal generation means 11 that generates a signal for capturing image data when displaying the image data, a pulse signal train output from the address generation means 10, reference position information of an arbitrarily allocated image window, and the size of the image window. an output signal generation means 12 that receives information as input and generates an output signal of image data when displaying a pixel position in an image window to which a pulse signal train outputted from the address generation means 10 is allocated; and a capture signal generation means. 11, an image data capturing means 13 captures the image data on the first video bus 4 and transfers it to the first memory 7, and an output signal generated by the output signal generating means 10. In response, the image data output means 14 sends the image data developed in the second memory 9 to the second video bus 5.

Here, the image window information input to the capture signal generation means 11 of the interface means 6 of the same processor module 2 and the image window information input to the output signal generation means 12 are, for example, The image window information input to the output signal generating means 11 may be set to be slightly larger than the image window information input to the output signal generating means 12. Then, either or both of the image window information input to the capture signal generation means 11 and the image window information input to the output signal generation means 12 is changed according to the calculation result of the image processing operation. Sometimes. and the ink face means 6 of each processor module 2.
The image windows allocated to the video devices 1 and 3 are usually obtained by dividing the entire area of the image data handled by the video devices 1 and 3 according to a format that does not overlap with each other or a format that partially overlaps. will be assigned.

[Operation] In the present invention, for example, the processor module 2 serving as a mask deploys in each processor module 2 the image processing execution means 8 used for extracting features of image data to be processed. Then, for example, the image processing execution means 8 of each processor module 2 developed in this way informs the acquisition signal generation means 11 and output signal generation means 12 of the own module of the image window allocated to the own module. The reference position information and size information will be notified.

The address generation means 10 separates the synchronization signal included in the image signal sent from the video equipment 1 to generate a pulse signal train that displays pixel position information of the image data. In response to the pulse signal train generated by the address generating means 10, the take-in signal generating means 11 generates a take-in signal when the pixel position within the image window to which the pulse signal train has been notified is displayed. The image data importing means 13 is instructed to import image data, and according to this instruction, the image data importing means 13 stores the image data information in the allocated image window in the first memory 7.
Store in.

When the image data for the image window is stored in the first memory 7 in this way, the image processing execution means 8 performs image processing at the video rate on the image data developed in the first memory 7. The operations are performed and the processing results are stored in the second memory 9.

On the other hand, the output signal generation means 12 is the address generation means 10.
In response to the pulse signal train generated by the image data output means 1, the image data output means 1 generates an output signal when the pulse signal train is displaying a pixel position within the notified image window.
4 to output the image data, and according to this instruction, the image data output means 14 outputs the image data for the image window that has been subjected to the image processing and is stored in the second memory 9 to the second video. Processing is performed to output the video to the video equipment 3 via the bus 5.

In this way, in the present invention, the image data processing device is configured with a multiprocessor, and each processor module is configured to take in image data of a small area allocated to its own module and process it. , it becomes possible to configure image processing operations performed in video rate processing using software. From now on, by using the present invention, it will be possible to provide an image data processing device that can perform general-purpose image processing while processing image data with the video ray 1.

(Example] Hereinafter, the present invention will be explained in detail according to examples.

FIG. 2 illustrates the system configuration of an image data processing apparatus constructed according to the present invention. As shown in this figure, the image data processing device constructed according to the present invention includes a plurality of processor modules 2 constituting a multi-processor sensor system, and uses the plurality of processor modules 2 to communicate via an input video bus 4a. A configuration is adopted in which image processing operations are performed in parallel on the video signal from the TV camera 1a given by the TV camera 1a, and the image data subjected to the image processing operation is outputted as a video via the output video bus 5a. This configuration adopts a configuration in which the data is output to the device 3a. Here, the image data given via the input video bus 4a may be in either analog format or digital format, and the image data output via the output video bus 5a may also be in analog format. , digital format.

When adopting such a multiprocessor configuration,
In order to enable the processor modules 2 to execute general-purpose image processing operations at video rate processing, in the image data processing apparatus of the present invention, as explained in FIG. Rather than importing the image data of the entire area of the TV image (which changes 30 images per second) sent from the TV, it is configured to import the image data of a small area within the divided image window. The configuration is such that image processing operations such as video rate processing are executed by software on the captured image data of the small area.

The human output interface circuit 20 included in each processor module 2 executes the process of capturing and outputting image data of a small area within this image window.

FIG. 3 illustrates an image window to be processed by the input/output ink face circuit 20 of each pro-sensor module 2. As shown in this figure, each Prosen 4J module 2 has a pixel position A (a, b) of a group f specified inside the entire image area of M×N pixels, a horizontal size pixel number m, The processing target is image data within an image window partitioned by the number n of vertical pixels.

This image window is allocated to each processor module 2 by dividing the entire area of image data in a manner that does not overlap with each other, as shown in FIG. 4, for example.

The allocation of image windows to each processor module 2 may be fixed in advance, or may be variable according to the image processing software developed on each processor module 2. It may also be set. Normally, the image window for input processing and the image window for output processing are set to have the same size and are placed at the same reference position, but image processing operations performed by software It may be set to a different value depending on the content of the calculation, or may be changed in real time depending on the calculation result of the image processing operation.

FIG. 5 shows a C language description of the image data capture process executed by the input/output ink face circuit 2o. That is, as shown in this figure, the input/output interface circuit 20 first, in line (1),
Initialize the parameters M, N, a bm, n, then
In lines (2) and (8), the address y is counted up one by one from "0" to "N", and then,
In lines (3) and (7), address X is set to “0”.
Then, in line (4), the generated x/y address is
It is determined whether or not the image is within the image window ABCD explained in FIG. The image data of the pixel specified by the x/y address is stored in an internal memory (not shown), and if the data is not within the image window, proceed to line (6) to store the image data of the pixel specified by the x/y address. Processing is performed so as not to import pixel image data. Then, in line (9), the position and size of the image window in the next frame cycle are changed as necessary based on the calculation result.

In this way, the input/output interface circuit 20
Since only the image data of the allocated small area of the image data transferred from the V camera 1a is taken in, the amount of image data to be processed by each processor module 2 is made small. I can do it. From now on, each processor module 2 will be able to use software to execute image processing operations performed in video rate processing, making it possible to implement versatile image processing operations while following video rate processing. It is.

The image data import process explained in FIG. 5 can be executed as is using a program means if the output processing speed of the video ML that outputs the image data is slow, but it can be executed as it is using a program means. 640 x 4
If as many as 30 images of approximately 80 pixels are sent per second, it becomes impossible for the programming means to capture them using video rate processing. Therefore, when such high-speed capture processing is required, the input/output interface circuit 20 will be configured with hardware.

FIG. 6 illustrates an example of the input circuit configuration of the input/output interface circuit 20 configured by hardware. Next, according to the embodiment shown in FIG. 6, an input/output interface circuit 2 configured by hardware is constructed.
The process of capturing image data of 0 will be explained.

The image signal from the TV camera 1a is sent to the synchronization signal separation circuit 2.
1, and is also input to the data latch circuit 22 which latches the image data for each pixel. When the synchronization signal separation circuit 21 receives this image signal, it separates the horizontal synchronization signal and vertical synchronization signal included in the image signal, and sends these separated synchronization signals to the X address generation circuit 23. Forward. When this synchronization signal is received, the X address generation circuit 23 performs an AND operation between the input synchronization signal and a clock signal prepared for control, so that the The X address is counted up and output to the comparator 25. Then, when the X address that is being counted and amplified exceeds the size M in the X direction of the input image data given as initial data, the X address generation circuit 23 executes a process of resetting the X address to a zero value. At the same time, an overflow signal is output to the X address generation circuit 24. Note that when the size of the transferred image data is changed, the value of the M value given to the initial data is changed (Z regrettable).

When receiving the overflow signal from the X address generation circuit 23, the X address generation circuit 24 performs an AND operation between the input overflow signal and a clock signal prepared for control. , each time one line of image data is transferred, the X address is counted up and the comparator 25
Output to . This X address generation circuit 24
, an incrementing X address is given as initial data, and when it exceeds the size N in the X direction of the S input image data, it executes a process of resetting the X address to a zero value. Note that when the size of the transferred image data is changed, the initial data and the M value given will be changed.

Upon receiving the X address from the X address generation circuit 23 and the X address from the X address generation circuit 24, the comparator 25 calculates the parameters a, b, m, and n of the image window initialized from the outside. x/
It checks whether the pixel specified by the y address is within the set image window, and if it is within the image window, it sends an enable signal to the data acquisition circuit 26. At the same time, if it is outside the image window, a process is executed in which a disable signal is sent to the data acquisition circuit 26.

FIG. 7 shows a comparator 25 provided to execute this process.
1 illustrates an example of the circuit configuration of FIG. For example, in accordance with this circuit configuration, the comparator 25 detects that the AND gate 251 detects that the input X address is equal to but larger than the parameter a, and the comparator 255 detects that the input X address is detected by the adder 254. The AND gate 256 detects that the input X address is equal to but greater than the parameter b, and the comparator 260 detects that the input The input X address is the adder 25
9, the AND gate 261
The enable signal is sent out according to the AND operation processing.

Upon receiving the enable signal from the comparator 25, the data acquisition circuit 26 processes the image data latched by the data launch circuit 22 and transfers it to an internal memory (not shown). When the enable signal is received, processing is performed so that the image data latched by the data launch circuit 22 is not captured.

In this way, the processor module 2 is able to capture only the image data within the image window allocated to the processor module 2. The captured image data is then subjected to predetermined arithmetic processing according to image processing operations configured by software.

Next, a description will be given of output processing of image data that has been subjected to image processing operations, which will be executed by the input/output interface circuit 20.

FIG. 8 shows the image data output processing executed by the input/output interface circuit 20 described in C language. As shown in this figure, the input/output interface circuit 20
Similar to the import process explained in FIG. 5, the parameters M N, a, b, m, and n are initialized in line (1), and Then, the address y is sequentially counted and amplified by 1 from "0" to "N", and (
In line 3) and line (7), address X is counted up one by one from 0" to "M". Then, (
4) In line 4, the generated x/y address is displayed in the image window AB explained in FIG. 3, which is the output target.
It is determined whether the item is in the CD or not, and if it is in the image window, the x/
The image data of the pixel specified by the y address is read from the internal memory (not shown) and output. However, if the data is not within the image window, proceed to line (6) and read the x/y data of the pixel specified by the y address.
Processing is performed so that the image data of the pixel specified by the address is not output. And in line (9),
Based on the calculation results, the position and size of the image window for the next frame cycle are changed as necessary.9 In this way, the input/output interface circuit 20 allows general-purpose image processing operations to be performed by software. The output process for the image data in the image window is executed.

The image data output processing explained in FIG.

As with import processing, this is usually configured using hardware. FIG. 9 illustrates an example of the output circuit configuration of the input/output interface circuit 20 configured by hardware. This output circuit
A synchronization signal separation circuit 21' (which may be used in common with the synchronization signal separation circuit 21) that performs the same processing as the synchronization signal separation circuit 21 explained in the figure, and a The X address generation circuit 23' (
) and the sixth
An X address generation circuit 24' (X address generation circuit 24) that performs the same processing as the X address generation circuit 24 explained in the figure.
) and the comparator 25 explained in FIG.
The comparator 2327 performs similar processing and outputs an output instruction to the data output circuit 28.

The operation processing of the output circuit included in the input/output interface circuit 20 shown in FIG. 9 is basically the same as the operation processing of the input circuit included in the input/output interface circuit 20 described in FIG. The X address generation circuit 23'
The comparator 27 generates the X addresses of both image pigs according to the synchronization signal separated by the IIJj signal separation circuit 21'.
The X address generation circuit 24' generates an X address of the image data according to the overflow signal detected by the X address generation circuit 23' and outputs it to the comparator 27. The image window parameters a, b, and m are initialized.

n is used to check whether the pixel specified by the input x/X address is within the image window set as the output target, and if it is within the image window, the data is By sending an enable signal to the output circuit 28, an instruction to output the image data of the pixel specified by the χ/y address is issued, and if the data is outside the image window, the data output circuit By sending a disable signal to 28, processing is performed so that an output instruction for the image data of the pixel specified by the χ/y address is not issued.

In this manner, the input/output interface circuit 20 executes output processing of the image data within the image window that has been subjected to general-purpose image processing operations using software.

Although the illustrated embodiment has been described, the present invention is not limited thereto. For example, in the embodiment, the comparator 25 of the input circuit of the input/output interface circuit 20 and the comparator 27 of the output circuit are separate, but the image window assigned to the input circuit and the output When setting the image windows assigned to the circuits to be exactly the same, by making these two comparators common, the signal issued to the data acquisition circuit 26 and the signal issued to the data output circuit 28 can be They may be supplied from exactly the same circuit.

Further, the internal memory to be accessed by the input/output interface circuit 20 is not specifically mentioned because it does not define the present invention, but for example, it is possible to use two of the same memory and place one on the CPU side. By connecting the other side to the input/output interface circuit 20 side, and switching this connection every time image processing for one frame is completed,
A configuration or the like will be adopted that allows image processing operations to be performed while executing the capture process, and allows output processing to the outside to be performed while executing the write process of the calculation result of the image processing operation.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to perform image processing operations using video rate processing using software.

From now on, by using the present invention, it will be possible to provide an image data processing device that can perform general-purpose image processing while processing image data at a video rate, and it will be possible to provide an image data processing device with the same hardware. This makes it possible to respond to image processing requirements in a variety of fields.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the principle configuration of the present invention, FIG. 2 is a system configuration diagram of the image data processing device of the present invention, FIGS. 3 and 4 are explanatory diagrams of the image window, and FIG. 5 is a diagram of the input/output interface circuit. An explanatory diagram of the image data capture process to be executed, FIG. 6 is an example of the input circuit configuration of the input/output interface circuit, FIG. 7 is an example of the circuit configuration of the comparator, and FIG. 8 is the input/output interface. FIG. 9 is an explanatory diagram of image data output processing executed by the circuit. FIG. 9 is an example of an output circuit configuration included in the input/output interface circuit. In the figure, 1 is a video device, 2 is a processor module, and 3 is a video device.
is a video device, 4 is a first video bus, 5 is a second video bus, 6 is an interface means, 7 is a first memory,
8 is an image processing execution means, 9 is a second memory, IO is an address generation means, 11 is an acquisition signal generation means, 12 is an output signal generation means, 13 is an image data acquisition means, and 14 is an image data output means. be.

Claims (5)

[Claims] (1) Consists of a plurality of processor modules (2) that capture image data output from video equipment in parallel, perform image processing on it, and output the image data obtained through the image processing in parallel. The image data processing device is an image data processing device, and each processor module (2) receives an image signal sent from a video device and generates an address from the image signal to generate a pulse signal train that displays pixel position information of the image data. means (10); and the address generating means (1
The address generating means (10) receives as input the pulse signal train outputted by the address generator (10), the reference position information of an arbitrarily allocated image window, and the size information of the image window.
); and a pulse signal output from the address generating means (10). column, reference position information of the image window, and size information of the image window, when the pulse signal train output from the address generating means (10) displays the pixel position within the image window, the image and an output signal generating means (12) for generating an output signal of data, each processor module (2) comprising:
In accordance with the capture signal issued by the interface means (6), the image data in the allocated image window is captured from the image signal sent, and the image processing operation is performed in accordance with the output signal issued by the interface means (6). An image data processing device characterized in that the image data processing device is configured to output image data in the image window subjected to the image processing. (2) In the image data processing device according to claim (1), the image window information input to the capture signal generation means (11) and the image window information input to the output signal generation means (12) are different. An image data processing device characterized in that the image data processing device is configured to be set to (3) In the image data processing device according to claim (1) or (2), image window information input to the capture signal generation means (11) or image window information input to the output signal generation means (12). An image data processing device characterized in that one or both of the pieces of information is configured to be changed according to the calculation result of an image processing operation. (4) In the image data processing apparatus according to any one of claims (1) to (3), the interface means (
6) The image window to be allocated is configured so that the entire area of the image data can be allocated in a format that does not overlap with each other, or in a format that can be obtained by dividing the entire area according to a format that partially overlaps. An image data processing device characterized by: (5) In the image data processing apparatus according to any one of claims (1) to (4), each processor module (2) is configured by software means and is configured to perform image processing for performing general-purpose image processing operations. The image processing apparatus is configured to include an execution means (8), and is configured to perform image processing at a video rate on the image data of a small area taken in by the interface means (6) according to the image processing execution means (8). An image data processing device characterized by: