JPH04113672A - Master slice type semiconductor integrated circuit - Google Patents

Master slice type semiconductor integrated circuit

Info

Publication number
JPH04113672A
JPH04113672A JP23305390A JP23305390A JPH04113672A JP H04113672 A JPH04113672 A JP H04113672A JP 23305390 A JP23305390 A JP 23305390A JP 23305390 A JP23305390 A JP 23305390A JP H04113672 A JPH04113672 A JP H04113672A
Authority
JP
Japan
Prior art keywords
wiring
circuit
semiconductor integrated
type semiconductor
master slice
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23305390A
Other languages
Japanese (ja)
Inventor
Takashi Ono
剛史 大野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC IC Microcomputer Systems Co Ltd
Original Assignee
NEC IC Microcomputer Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC IC Microcomputer Systems Co Ltd filed Critical NEC IC Microcomputer Systems Co Ltd
Priority to JP23305390A priority Critical patent/JPH04113672A/en
Publication of JPH04113672A publication Critical patent/JPH04113672A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To eliminate necessity of connecting a correcting circuit to an exterior and to provide an economical effect by inserting other wiring in parallel with wirings for coupling between a R-string circuit and a reference voltage input terminal through a transfer gate. CONSTITUTION:In a master slice type semiconductor integrated circuit containing a D/A converter 2 including an R-string circuit 21, other wiring is inserted in parallel with wirings for coupling between the circuit 21 and an upper reference voltage input terminal 3 through a transfer gate, i.e., a P-channel transistor 6. Then, if wiring is actually conducted to become a higher wiring resistance value than an expected one, an input signal of a low level is input to a gate input terminal 4. Thus, a P-channel transistor 6 is turned ON, ON resistances of a wiring resistor 12 and the transistor 6 are connected in parallel, and an actual resistance value is reduced.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、マスタスライス方式の半導体累積回路に関し
、特にR−ストリング回路を含むD−A(又はA−D 
>変換回路を内蔵するマスタスライス方式の半導体集積
回路に間する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a master slice type semiconductor accumulation circuit, and in particular to a DA (or A-D) including an R-string circuit.
> Used in master slice type semiconductor integrated circuits with built-in conversion circuits.

〔従来の技術〕[Conventional technology]

近年、CAD技術の著しい進歩により半導体集積回路の
設計自動化が進み、マスタスライス方式の代表例である
ゲートアレイ方式などでは、計算機処理により自動的に
上地配線パターンが作成されるようになってきた。
In recent years, significant advances in CAD technology have led to automation of the design of semiconductor integrated circuits, and in the gate array method, which is a typical example of the master slice method, upper wiring patterns are now automatically created using computer processing. .

この種のゲートアレイ方式の半導体集積回路は自動で配
線が行える反面、同じマクロが含まれた別の回路を配線
した場合、配線パターンが変わってしまう、それによる
配線抵抗の変動は、D−A変換回路の精度に影響するた
め、配置を工夫して、変動を少なくしたり、外部に補正
回路を接続する必要があった。
This type of gate array type semiconductor integrated circuit can be automatically wired, but if another circuit containing the same macro is wired, the wiring pattern will change, and the resulting fluctuation in wiring resistance will be caused by D-A Because it affected the accuracy of the conversion circuit, it was necessary to devise a layout to reduce fluctuations or to connect an external correction circuit.

第2図は従来のD−A変換回路を内蔵するマスタスライ
ス方式の半導体集積回路を示すブロック図である。
FIG. 2 is a block diagram showing a master slice type semiconductor integrated circuit incorporating a conventional DA conversion circuit.

D−A変換回路2AはR−ストリング型D−A変換回路
で多数の抵抗を直列接続したR−ストリング回路21A
を有している。R−ストリング回路21Aの最上位ビッ
トの抵抗7Aと上位基準電圧入力端子3Aとの間に配線
抵抗10Aが存在する。この配線抵抗10Aが一定であ
れば予めそれを見込んで抵抗7Aの値を設定することが
できるが、マスタスライス方式だと品種によって配線パ
ターンが変り、高性能のD−A変換回路を実現すること
ができない。
The DA conversion circuit 2A is an R-string type DA conversion circuit, and is an R-string circuit 21A in which a large number of resistors are connected in series.
have. A wiring resistance 10A exists between the most significant bit resistance 7A of the R-string circuit 21A and the upper reference voltage input terminal 3A. If this wiring resistance of 10 A is constant, the value of the resistor of 7 A can be set in anticipation of it in advance, but with the master slice method, the wiring pattern changes depending on the product, making it difficult to realize a high-performance D-A conversion circuit. I can't.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来のマスタスライス方式の半導体集積回路に
おけるD−A変換回路は、マスタスライス方式を用いる
為に生じる配線抵抗などの変動を補正するには、外部に
補正回路を接続しなければならなく、経済的な設計がで
きない欠点があった。
The D-A conversion circuit in the conventional master slice semiconductor integrated circuit described above requires an external correction circuit to be connected in order to compensate for variations in wiring resistance etc. that occur due to the use of the master slice method. It had the disadvantage that it could not be designed economically.

〔課題を解決するための手段〕[Means to solve the problem]

本発明は、R−ストリング回路を含むD−A(又はA−
D)変換回路を内蔵するマスタスライス方式の半導体集
積回路において、前記R−ストリング回路と基準電圧入
力端子との間を結ぶ配線と並列に他の配線が伝達ゲート
を介して挿入されているというものである。
The present invention provides a D-A (or A-
D) In a master slice type semiconductor integrated circuit incorporating a conversion circuit, another wiring is inserted in parallel with the wiring connecting the R-string circuit and the reference voltage input terminal via a transmission gate. It is.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明する
Next, embodiments of the present invention will be described with reference to the drawings.

第1図は本発明の一実施例を示すブロック図である。FIG. 1 is a block diagram showing one embodiment of the present invention.

この実施例は、R−ストリング回路21を含むD−A変
換回路2を内蔵するマスタスライス方式の半導体集積回
路において、R−ストリング回路21と上位基準電圧入
力端子3との間を結ぶ配線と並列に他の配線が伝達ゲー
ト(Pチャネルトランジスタ6)を介して挿入されてい
るというものである。
This embodiment is implemented in a master slice type semiconductor integrated circuit incorporating a D-A converter circuit 2 including an R-string circuit 21, in parallel with the wiring connecting the R-string circuit 21 and the upper reference voltage input terminal 3. Another wiring is inserted through the transmission gate (P channel transistor 6).

最上位ビットの抵抗7を見がけ上のものと考えた場合、
実際の最上位ビット抵抗は7と配線抵抗10を加えたも
のと考えられる。そこで配線抵抗の変動を考慮し、7と
10を加えた抵抗値を、予想される抵抗値(すなわち典
型的な値)よりやや低めに設定をしておく。そこで、実
際に配線が行われ、予想されたものより高めの抵抗値と
なった場合、ゲート入力端子4にロウレベルの入力信号
を入れる事によりPチャネルトランジスタ6がオン状態
となり配線抵抗10に対し、配線抵抗12とPチャネル
トランジスタ6のオン抵抗が並列に接続され、実際の抵
抗値が低くなる。このようにしてトリミングが可能とな
り、実際の最上位ビットの抵抗の変動幅を小さくできる
If we consider the resistor 7 of the most significant bit to be illusory,
The actual most significant bit resistance is considered to be 7 plus wiring resistance 10. Therefore, in consideration of variations in wiring resistance, the resistance value, which is the sum of 7 and 10, is set to be slightly lower than the expected resistance value (that is, the typical value). Therefore, if wiring is actually performed and the resistance value is higher than expected, by inputting a low-level input signal to the gate input terminal 4, the P-channel transistor 6 is turned on, and the wiring resistance 10 becomes The wiring resistance 12 and the on-resistance of the P-channel transistor 6 are connected in parallel, and the actual resistance value becomes low. In this way, trimming becomes possible, and the range of actual resistance fluctuation of the most significant bit can be reduced.

以上D−A変換回路を内蔵する場合について説明したが
、A−D変換回路の場合においてもR−ストリング回路
を有するものに本発明を適用しうることは明らかである
Although the case in which a D-A conversion circuit is incorporated has been described above, it is clear that the present invention can be applied to an A-D conversion circuit having an R-string circuit.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、R−ストリング回路と基
準電圧入力端子との間を結ぶ配線と並列に他の配線を伝
達ゲートを介して挿入することにより、抵抗トリミング
が可能となるので、D−A(又はA−D )変換回路の
フルスケール調整などを行う場合外部に素子を接続する
事が不要となり、部品点数が削減され、より経済的にで
きる効果がある。また、見方を変えると電圧変動の調整
をデジタル信号により制御する事も可能となり、容易に
高精度を得られる効果もある。
As explained above, the present invention enables resistance trimming by inserting another wire in parallel with the wire connecting the R-string circuit and the reference voltage input terminal via the transmission gate. When performing full scale adjustment of the -A (or A-D) conversion circuit, it is not necessary to connect external elements, the number of parts is reduced, and there is an effect that it can be made more economical. In addition, from a different perspective, it is also possible to control voltage fluctuation adjustment using digital signals, which has the effect of easily achieving high accuracy.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、本発明の一実施例を示すブロック図、第2図
は従来の例を示すブロック図である。 1、IA・・・半導体集積回路、2,2A・・D−A変
換器、21・・・R−ストリング回路、22・・・ディ
ジタル入力線、23・・・アナログ出力線、24・・・
選択部、3,3A・・・上位基準電圧入力端子、4・・
・Pチャネルトランジスタのゲート入力端子、55A・
・・下位基準電圧入力端子、6・・・Pチャネルトラン
ジスタ、7・・・R−ストリング回路の最上位ビットの
抵抗、10.IOA、11.IIA・・・配線抵抗。
FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional example. 1, IA...Semiconductor integrated circuit, 2, 2A...D-A converter, 21...R-string circuit, 22...Digital input line, 23...Analog output line, 24...
Selection section, 3, 3A...Upper reference voltage input terminal, 4...
・P-channel transistor gate input terminal, 55A・
. . . Lower reference voltage input terminal, 6 . . P channel transistor, 7 . . . Resistance of the most significant bit of the R-string circuit, 10. IOA, 11. IIA...Wiring resistance.

Claims (1)

【特許請求の範囲】[Claims] R−ストリング回路を含むD−A(又はA−D)変換回
路を内蔵するマスタスライス方式の半導体集積回路にお
いて、前記R−ストリング回路と基準電圧入力端子との
間を結ぶ配線と並列に他の配線が伝達ゲートを介して挿
入されていることを特徴とするマスタスライス方式の半
導体集積回路。
In a master slice type semiconductor integrated circuit incorporating a D-A (or A-D) conversion circuit including an R-string circuit, another wire is connected in parallel with the wiring connecting the R-string circuit and the reference voltage input terminal. A master slice type semiconductor integrated circuit characterized in that wiring is inserted through a transmission gate.
JP23305390A 1990-09-03 1990-09-03 Master slice type semiconductor integrated circuit Pending JPH04113672A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23305390A JPH04113672A (en) 1990-09-03 1990-09-03 Master slice type semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23305390A JPH04113672A (en) 1990-09-03 1990-09-03 Master slice type semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPH04113672A true JPH04113672A (en) 1992-04-15

Family

ID=16949060

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23305390A Pending JPH04113672A (en) 1990-09-03 1990-09-03 Master slice type semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPH04113672A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001047123A1 (en) * 1999-12-21 2001-06-28 Matsushita Electric Industrial Co., Ltd. High-precision d-a converter circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001047123A1 (en) * 1999-12-21 2001-06-28 Matsushita Electric Industrial Co., Ltd. High-precision d-a converter circuit
US6469647B1 (en) 1999-12-21 2002-10-22 Matsushita Electric Industrial Co., Ltd. High-precision D-A converter circuit

Similar Documents

Publication Publication Date Title
US6147520A (en) Integrated circuit having controlled impedance
US6628223B2 (en) Resistance changeable device for data transmission system
US5635873A (en) Operational amplifier having dummy isolation stage
US6768393B2 (en) Circuit and method for calibrating resistors for active termination resistance, and memory chip having the circuit
JPH0573290B2 (en)
JPH11340810A (en) Semiconductor device
US7345614B2 (en) Analog to digital converter with a series of inverting elements
JPH09502577A (en) CMOS BTL compatible bus and transmission line driver
CA1250349A (en) Phase changing circuit
JPH04113672A (en) Master slice type semiconductor integrated circuit
JP2641641B2 (en) DA converter
CA2053322C (en) Integrated circuit and gate array
JPH01117518A (en) Output circuit for semiconductor device
US4942397A (en) Elimination of linearity superposition error in digital-to-analog converters
JPS6387809A (en) Operational amplifier
JPH0567083B2 (en)
JPH05102831A (en) Output circuit for semiconductor integrated circuit
US20040113652A1 (en) Apparatus and method for precisely controlling termination impedance
JPH0581089B2 (en)
JP2819787B2 (en) Constant current source circuit
JPH01274515A (en) Semiconductor integrated circuit
JP2754637B2 (en) Output buffer circuit
JP2734216B2 (en) Integrated circuit with built-in clock skew adjustment circuit
JP2808754B2 (en) Gate array type integrated circuit
JPH02195716A (en) Logical gate circuit for semiconductor integrated circuit