JPH04113607A - Multilayer ceramic capacitor - Google Patents
Multilayer ceramic capacitorInfo
- Publication number
- JPH04113607A JPH04113607A JP2232864A JP23286490A JPH04113607A JP H04113607 A JPH04113607 A JP H04113607A JP 2232864 A JP2232864 A JP 2232864A JP 23286490 A JP23286490 A JP 23286490A JP H04113607 A JPH04113607 A JP H04113607A
- Authority
- JP
- Japan
- Prior art keywords
- laminated
- baked
- multilayer ceramic
- ceramic capacitor
- ceramic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003985 ceramic capacitor Substances 0.000 title claims description 26
- 239000000919 ceramic Substances 0.000 claims abstract description 18
- 239000011241 protective layer Substances 0.000 claims abstract description 10
- 239000011800 void material Substances 0.000 claims description 4
- 239000003990 capacitor Substances 0.000 abstract description 6
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical group [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 abstract description 5
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 abstract description 4
- 238000000034 method Methods 0.000 abstract description 3
- 229910002092 carbon dioxide Inorganic materials 0.000 abstract description 2
- 239000001569 carbon dioxide Substances 0.000 abstract description 2
- SWELZOZIOHGSPA-UHFFFAOYSA-N palladium silver Chemical compound [Pd].[Ag] SWELZOZIOHGSPA-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052709 silver Inorganic materials 0.000 abstract description 2
- 239000004332 silver Substances 0.000 abstract description 2
- 230000000694 effects Effects 0.000 description 5
- 229910052799 carbon Inorganic materials 0.000 description 3
- 238000010304 firing Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、積層セラミックコンデンサに関し、特に電歪
効果に伴う高周波数領域での機械的共振を抑制した積層
セラミックコンデンサに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multilayer ceramic capacitor, and particularly to a multilayer ceramic capacitor that suppresses mechanical resonance in a high frequency region due to electrostrictive effects.
ＤＣ−ＤＣコンバータのスイッチング周波数は、年々高
くなってきており、現在では５００ｋＨｚまてのものが
汎用化されている。スイ・ンチング周波数の高周波化に
伴い、ＤＣ−ＤＣコンバータの入力側π型ＬＣフィルタ
に高誘電率系積層セラミックコンデンサを用いる場合、
電歪効果によって積層セラミックコンデンサが共振を起
こし、フィルタの役割を果たさなくなることかあること
が最近分ってきた。第４図は従来のチップ形積層セラミ
ックコンデンサの断面図で、セラミックコンデンサ本体
１は、内部電極を有するセラミック積層部２と、これを
上下から包むように形成されたセラミック保護層部４と
、外部電極端子３とから構成されている。The switching frequency of DC-DC converters has been increasing year by year, and currently, DC-DC converters with a switching frequency of up to 500 kHz are commonly used. As the switching frequency becomes higher, when using a high dielectric constant multilayer ceramic capacitor for the π-type LC filter on the input side of the DC-DC converter,
It has recently been discovered that electrostrictive effects can cause multilayer ceramic capacitors to resonate, causing them to no longer function as a filter. FIG. 4 is a sectional view of a conventional chip-type multilayer ceramic capacitor. The ceramic capacitor main body 1 includes a ceramic multilayer part 2 having internal electrodes, a ceramic protective layer part 4 formed to wrap this from above and below, and an external electrode. It consists of terminal 3.
上述のようにＤＣ−ＤＣコンバータの入力側π型ＬＣフ
ィルターに高誘電率系積層セラミックコンデンサを用い
る場合、電歪効果により積層セラミックコンデンサが共
振を起こし、フィルタの役割を果せなくなるのは、ＤＣ
−ＤＣコンバータの基本スイッチング周波数と、その第
２次、第３次、第４次の高調波と、この周波数範囲内で
の積層セラミックコンデンサの電歪による共振周波数（
以下電歪共振点と呼ぶ）が一致した時に起き易い現↑で
ある。基本スイッチング周波数における電歪共振は、積
層セラミックコンデンサの長さおよび幅寸法を最適値に
選ぶことにより、回避できる。しかし、第２次から第４
次高調波の周波数範囲は、積層セラミックコンデンサの
厚さ方向の寸法にかかわる電歪共振点に当たるため容易
に回避できない。厚さを薄くすれば電歪共振点は高周波
側にずれ、厚くすれば低周波側にずれる。しかし、厚さ
を薄くすればコンデンサの静電容量は小さくなり、厚く
すれば製造しにくくなりコストアップにつながる。As mentioned above, when a high dielectric constant multilayer ceramic capacitor is used as the input side π-type LC filter of a DC-DC converter, the multilayer ceramic capacitor resonates due to the electrostrictive effect and cannot fulfill its role as a filter.
- The basic switching frequency of the DC converter, its second, third, and fourth harmonics, and the resonance frequency due to electrostriction of the multilayer ceramic capacitor within this frequency range (
This phenomenon is likely to occur when the electrostrictive resonance points (hereinafter referred to as electrostrictive resonance points) coincide. Electrostrictive resonance at the fundamental switching frequency can be avoided by selecting optimal length and width dimensions of the multilayer ceramic capacitor. However, from the second to the fourth
The frequency range of the next harmonic cannot be easily avoided because it corresponds to the electrostrictive resonance point related to the thickness direction dimension of the multilayer ceramic capacitor. If the thickness is made thinner, the electrostrictive resonance point shifts to the high frequency side, and if the thickness is made thicker, the electrostrictive resonance point shifts to the lower frequency side. However, reducing the thickness reduces the capacitance of the capacitor, while increasing the thickness makes it difficult to manufacture and increases costs.
厚さのコントロール以外の方法で、電歪共振を抑制する
技術が要請されるが、従来技術では、セラミック誘電体
組成を変える以外になく、これは増々容易ではない。A technique for suppressing electrostrictive resonance by a method other than thickness control is required, but with the conventional technique, the only way is to change the ceramic dielectric composition, which is increasingly difficult.
本発明の目的は、積層セラミックコンデンサの厚さ寸法
やセラミック誘電体の組成を変えないで、ＤＣ−ＤＣコ
ンバータの基本スイッチング周波数の第２次から第４次
高調波における積層セラミ・ツクコンデンサの電歪共振
を抑制することができる積層セラミックコンデンサを提
供することにある。It is an object of the present invention to provide a multilayer ceramic capacitor with high voltage at the second to fourth harmonics of the fundamental switching frequency of a DC-DC converter without changing the thickness dimension of the multilayer ceramic capacitor or the composition of the ceramic dielectric. An object of the present invention is to provide a multilayer ceramic capacitor that can suppress strain resonance.
本発明の積層セラミックコンデンサは、内部電極を有す
るセラミック積層部を、上、下から包むように形成した
、内部電極を有しないセラミック保護層部の中に空隙を
設けたことを特徴とする。The multilayer ceramic capacitor of the present invention is characterized in that a void is provided in a ceramic protective layer portion having no internal electrodes, which is formed so as to surround a ceramic laminated portion having internal electrodes from above and below.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例のチップ型積層セラミックコ
ンデンサの断面図である。従来との相違点は、セラミッ
ク保護層′部４の中に、複数の空隙５を設けたことであ
る。第３図（ａ）〜（Ｃ）は本発明の一実施例のチップ
形積層セラミックコンデンサの構造およびその製造方法
を説明するための工程順に示した説明図である。FIG. 1 is a sectional view of a chip-type multilayer ceramic capacitor according to an embodiment of the present invention. The difference from the conventional method is that a plurality of voids 5 are provided in the ceramic protective layer' section 4. FIGS. 3(a) to 3(C) are explanatory diagrams showing the structure of a chip-type multilayer ceramic capacitor according to an embodiment of the present invention and the manufacturing method thereof in order of steps.
第３図（ａ＞に示す如く、焼成前の生シート（以下グリ
ーンシート６と称す）上に銀パラジウム等の内部電極８
を印刷し、これを複数枚積層し、その上に複数のグリー
ンシート６とグリーンシート６の上にカーボン７を複数
個印刷したものを］枚積層する。才な、その下には複数
のグリーンシート６を積層する。これを、熱を加えなが
らプレスし成形して第２図（ｂ）に示す積層体９を作る
。この積層体９をバーンアウト炉て仮焼成し更に本焼成
することによって、カーボン７が炭酸ガスとなって抜け
、その跡が空＃１５として残る。As shown in FIG. 3 (a), internal electrodes 8 made of silver palladium, etc. are placed on the raw sheet (hereinafter referred to as green sheet 6) before firing.
A plurality of green sheets 6 and a plurality of carbon sheets 7 printed on the green sheets 6 are laminated on top of the green sheets 6. A plurality of green sheets 6 are stacked underneath the green sheets. This is pressed and molded while applying heat to form a laminate 9 shown in FIG. 2(b). By pre-firing this laminate 9 in a burnout furnace and then final firing, the carbon 7 is turned into carbon dioxide gas and escapes, leaving a trace as empty #15.
このようにしてセラミック保護層部４の中に空隙５を含
む第３図（Ｃ）に示すコンデンサ素子１０ができる。コ
ンデンサ素子１０の表面を軽く研磨した後、一対の銀な
どの外部電極端子３を焼付は形成して、本発明の一実施
例のチップ形積層セラミックコンデンサが完成する。In this way, the capacitor element 10 shown in FIG. 3(C) including the void 5 in the ceramic protective layer portion 4 is produced. After the surface of the capacitor element 10 is lightly polished, a pair of external electrode terminals 3 made of silver or the like are formed by baking, thereby completing a chip-type multilayer ceramic capacitor according to an embodiment of the present invention.
第３図に本発明の一実施例と従来例の電歪共振の比較デ
ータを示したが、特性が改善されていることがわかる。FIG. 3 shows comparative data of electrostrictive resonance between an embodiment of the present invention and a conventional example, and it can be seen that the characteristics are improved.
以上説明したように本発明はセラミック保護層に複数の
空隙を設けたことにより、厚さ寸法か興なる複数のチッ
プ形積層セラミックコンデンサ力集合体とみなせるなめ
、種々の波長の波を混在させ、干渉させ合うことにより
、特定の周波数で大きな電歪共振を起こさせない効果が
ある。As explained above, the present invention provides a plurality of voids in the ceramic protective layer, so that it can be regarded as a force aggregate of a plurality of chip-type multilayer ceramic capacitors depending on the thickness dimension, and waves of various wavelengths are mixed. By interfering with each other, there is an effect of preventing large electrostrictive resonance from occurring at a specific frequency.
ケミコンレス化ニーズに伴い、今後ますます小型、大容
量化が進む積層セラミックコンテンサは、電歪共振を起
こし易くなる方向にあるか、本発明によって電歪共振問
題を解決できるため、ＤＣ−ＤＣコンバータのＪす才す
の高集波化、小型化に貢献できる。Multilayer ceramic capacitors, which will become smaller and larger in capacity in the future due to the need for chemical contactless devices, are likely to become more prone to electrostrictive resonance, or because the present invention can solve the electrostrictive resonance problem, DC-DC It can contribute to higher wave concentration and miniaturization of converters.
第１図は本発明の一実施例のチップ形積層セラミックコ
ンデンサの断面図、第２図（ａ）〜（ｃ）は本発明の一
実施例のチップ形積層セラミックコンデンサの構造およ
び製造方法を示す図、第３図は電歪共振の改善データを
示す図、第４図は従来のチップ形積層セラミックコンデ
ンサの一例の断面図である。
］・・・チップ形積層セラミックコンデンサ本体、２・
・・内部電極を有するセラミック積層部、３・・外部電
極端子、４・・・セラミック保護層部、５・・・空隙、
６・・・グリーンシート、７・・・カーボン、８・・・
内部電極、９・・・積層体、１０・・・コンデンサ素子
。FIG. 1 is a sectional view of a chip-type multilayer ceramic capacitor according to an embodiment of the present invention, and FIGS. 2(a) to (c) show the structure and manufacturing method of a chip-type multilayer ceramic capacitor according to an embodiment of the present invention. 3 are diagrams showing improvement data on electrostrictive resonance, and FIG. 4 is a cross-sectional view of an example of a conventional chip-type multilayer ceramic capacitor. ]... Chip type multilayer ceramic capacitor body, 2.
... Ceramic laminated part having internal electrodes, 3... External electrode terminal, 4... Ceramic protective layer part, 5... Void,
6...green sheet, 7...carbon, 8...
Internal electrode, 9... Laminated body, 10... Capacitor element.
Claims (1)
むように形成した、内部電極を有しないセラミック保護
層部の中に空隙を設けたことを特徴とする積層セラミッ
クコンデンサ。A multilayer ceramic capacitor, characterized in that a ceramic protective layer section having no internal electrodes is formed to enclose a ceramic multilayer section having internal electrodes from above and below, and a void is provided in the ceramic protective layer section having no internal electrodes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2232864A JPH04113607A (en) | 1990-09-03 | 1990-09-03 | Multilayer ceramic capacitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2232864A JPH04113607A (en) | 1990-09-03 | 1990-09-03 | Multilayer ceramic capacitor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04113607A true JPH04113607A (en) | 1992-04-15 |
Family
ID=16946021
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2232864A Pending JPH04113607A (en) | 1990-09-03 | 1990-09-03 | Multilayer ceramic capacitor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04113607A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106024382A (en) * | 2015-03-27 | 2016-10-12 | Tdk株式会社 | Multilayer ceramic electronic device |
| JP2018157077A (en) * | 2017-03-17 | 2018-10-04 | 京セラ株式会社 | Capacitor |
-
1990
- 1990-09-03 JP JP2232864A patent/JPH04113607A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106024382A (en) * | 2015-03-27 | 2016-10-12 | Tdk株式会社 | Multilayer ceramic electronic device |
| CN106024382B (en) * | 2015-03-27 | 2019-07-30 | Tdk株式会社 | Monolithic ceramic electronic component |
| JP2018157077A (en) * | 2017-03-17 | 2018-10-04 | 京セラ株式会社 | Capacitor |
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