JPH04113595A - Read-only memory - Google Patents

Read-only memory

Info

Publication number
JPH04113595A
JPH04113595A JP2233062A JP23306290A JPH04113595A JP H04113595 A JPH04113595 A JP H04113595A JP 2233062 A JP2233062 A JP 2233062A JP 23306290 A JP23306290 A JP 23306290A JP H04113595 A JPH04113595 A JP H04113595A
Authority
JP
Japan
Prior art keywords
signal
output
circuit
data
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2233062A
Other languages
Japanese (ja)
Inventor
Shinobu Miyata
忍 宮田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC IC Microcomputer Systems Co Ltd
Original Assignee
NEC IC Microcomputer Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC IC Microcomputer Systems Co Ltd filed Critical NEC IC Microcomputer Systems Co Ltd
Priority to JP2233062A priority Critical patent/JPH04113595A/en
Publication of JPH04113595A publication Critical patent/JPH04113595A/en
Pending legal-status Critical Current

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  • Read Only Memory (AREA)

Abstract

PURPOSE:To eliminate a deterioration of logical threshold in an input circuit due to a noise by latching the input signal of an input buffer part by the output signal of a signal change detecting circuit for a certain period. CONSTITUTION:To an asynchronous type read-only memory, a data transition detecting (DTD: data transition detect) circuit 16 detecting the data transition of output signal (dn) of a sense amplifier 14 is provided, and an address buffer 10 of input circuit is made so that the address signal is latched by the output signal (-ae) of this DTD circuit 16 for a certain period (te). That is, the operation of an output buffer 15 is detected beforehand by the DTD circuit 16, 'H' data are outputted to the signal (-ae) during the time (te), then the address signal of address buffer 10 is latched. By this procedure, a malfunction due to the noises of power source Vcc and earth (GND) caused from the transition of output data O0-O1, is not generated during the time (te), and also the generation of delay in the data outputting time due to the malfunction is eliminated.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 〔従来の技術〕 従来、この種の読出専用メモリは、第３図のブロック図
および第４図のその動作波形図により説明される。この
メモリは、アドレス端子人。−Ａｉを入力するアドレス
バッファ１０と、Ｘ−デコーダ１１と、メモリマトリク
ス１２と、Ｙ−セレクタ１３と、センスアンプ１４と、
出力データＯ８〜Ｏ１を出力する出力バッファ１５とか
ら構成される。このメ、そりは、アドレス端子人。−Ａ
ｉや、コントロール端子に供給された入力信号によシ、
メモリマトリクス１２幅のメモリセルが選択されてこの
メモリセルの記憶情報が出力される。この動作方式とし
ては、同期タイプと非同期タイプに分類されるが、同期
信号を必要とせず使用しやすい非同期タイプが広く使わ
れている。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] [Prior Art] Conventionally, this type of read-only memory is explained by the block diagram of FIG. 3 and its operating waveform diagram of FIG. 4. This memory is address terminal person. -Ai input address buffer 10, X-decoder 11, memory matrix 12, Y-selector 13, sense amplifier 14,
The output buffer 15 outputs output data O8 to O1. This method is for address terminals. -A
i or the input signal supplied to the control terminal,
A memory cell having a width of 12 in the memory matrix is selected and the stored information of this memory cell is output. This operation method is classified into synchronous type and asynchronous type, but the asynchronous type is widely used because it does not require a synchronous signal and is easy to use.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の読出専用メモリは、その出力データが変
化する際、電源■Ｃｃ及び接地（ＧＮＤ）配線に瞬間的
に、大電流が流れるため、これら配線■ｃｃ及び接地線
に、ノイズΔＶｃ、、ΔＧＮＤを生じるという問題があ
る。そのため第４図に示す様に、これらノイズΔ■ｃｃ
、ΔＧＮＤによシ、入力回路、例えばアドレス入力回路
の入力信号レベルが論理閾値に対してマージンが少ない
場合、論理レベルが反転して誤ったアドレスを取り込む
ため正規のデータが出力されてから、１６時間後に誤っ
たアドレスに対応したデータが出力される。従って、入
力回路の論理鋤値が悪化し、データ出力時間の遅れを生
じるという問題が生ずる。In the conventional read-only memory described above, when the output data changes, a large current momentarily flows through the power supply ■CC and ground (GND) wires, so noise ΔVc,... There is a problem that ΔGND occurs. Therefore, as shown in Fig. 4, these noises Δcc
, ΔGND, if the input signal level of the input circuit, for example, the address input circuit, has a small margin with respect to the logic threshold, the logic level will be inverted and an incorrect address will be taken in. After some time, data corresponding to the wrong address is output. Therefore, a problem arises in that the logic value of the input circuit deteriorates and the data output time is delayed.

本発明の目的は、このような問題を解決し、ノイズによ
る入力回路の論理閾値の劣化をなくした読出専用メモリ
を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a read-only memory that solves these problems and eliminates deterioration of the logic threshold of an input circuit due to noise.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の読出専用メモリの構成は、メモリマトリクスか
らの出力を増幅したセンスアンプの出力信号あるいはこ
のセンスアンプの出力信号を増幅した出力バッファの駆
動信号の変化を検出する信号変化検出回路を設け、入力
バッファ部の入力信号が、この信号変化検出回路の出力
信号により　−定期間ラッテされるようにしたことを％
黴とする。The configuration of the read-only memory of the present invention includes a signal change detection circuit that detects a change in the output signal of a sense amplifier that amplifies the output from the memory matrix or the drive signal of the output buffer that amplifies the output signal of this sense amplifier. The input signal of the input buffer section is latched by the output signal of this signal change detection circuit for a period of -%.
Make it moldy.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明するっ第１図は
、本発明の一実施例のブロック図、第２図は第１図の動
作を説明する波形図である。本実施例は、従来の非声ｊ
期タイプの読出専用メモリに対して、センスアンプ１４
の出力信号ｄｎのデータ変化を検出するデータ変化検出
（ＤＴＤ；ＤａｔａＴｒａｎｓｊｔｉｏｎ　Ｄｅｔｅｃ
ｔ　）回路１６を設け、入力回路のアドレスバッファ１
０が、とのＤＴＤ回路１６の出力信号ａｅによシ一定期
間ｔｅアドレス信号がラッチされるようになっている。Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a waveform diagram illustrating the operation of FIG. 1. This embodiment uses the conventional non-voice j
For period type read-only memory, the sense amplifier 14
Data transition detection (DTD) detects data changes in the output signal dn of
t) A circuit 16 is provided, and address buffer 1 of the input circuit is provided.
The address signal te is latched for a certain period of time by the output signal ae of the DTD circuit 16, which is zero.

つまシ、ＤＴＤ回路１６により、出力バッファ１５が動
作する事を事前に検出し、信号ａｅに１Ｈ”データをｔ
ｅ待時間聞出力し、アドレスバッファ１０のアドレス信
号をラッチさせる。従って、このアドレスバッファ１０
はｔｅ待時間間、出力データ０゜〜Ｏ１が変化する事に
よる電源ｖｃｃ及び接地（ＧＮＤ）のノイズによる誤動
作が生じなくなシ、この誤動作によるデータ出力時間の
遅れを生じる事もない。The DTD circuit 16 detects in advance that the output buffer 15 operates, and sends 1H" data to the signal ae.
e waiting time is output and the address signal of the address buffer 10 is latched. Therefore, this address buffer 10
During the waiting time te, malfunctions due to noise from the power supply VCC and ground (GND) due to changes in the output data 0° to O1 do not occur, and there is no delay in data output time due to this malfunction.

また、ｔｅ時間後は出力信号ａｅに”Ｌ＃デデーが出力
され、アドレスバッファ１０は、通常通り非同期でデー
タを取シ込む事が可能となる。この時、出力データの変
化は完了しておシ、電源■Ｃｃ及び接地に出力データ変
化によるノイズが生じ々いため、アドレスバッファが誤
動作する事がない。Furthermore, after the time te, "L#dedata" is output to the output signal ae, and the address buffer 10 can receive data asynchronously as usual. At this time, the change in the output data has been completed. Since noise due to changes in output data is not likely to occur in the C, power supply and ground, the address buffer will not malfunction.

なお、ＤＴＤ回路１６が、出力バッファ１５の駆動信号
の変化を検出する様にする事によっても、同様の効果が
得られる事は明らかである。It is clear that the same effect can be obtained by having the DTD circuit 16 detect changes in the drive signal of the output buffer 15.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明は、センスアンプデータ出
力ｄｎの変化を検出するＤＴＤ回路を設け、このＤＴＤ
回路の出力信号ａｅによシ、一定期間アドレス信号がラ
ッチされるアドレスバッファを備えることによシ、入力
回路の論理閾値が安定でデータ出力時間の遅れを生じる
事がないという効果がある。As explained above, the present invention provides a DTD circuit that detects changes in the sense amplifier data output dn, and
By providing an address buffer in which an address signal is latched for a certain period of time based on the output signal ae of the circuit, the logic threshold of the input circuit is stable and there is no delay in data output time.

の読出専用メモリの一例のブロック図およびその動作波
形図である。FIG. 2 is a block diagram of an example of a read-only memory and its operation waveform diagram.

１０．１０ａ・・・アドレスバッファ、１１・・・Ｘ−
デコーダ、１２・・・メモリマトリクス、１３・・・Ｙ
−セレクタ、１４−・・センスアンプ、１５・・・出力
バッファ、１６・・・ＤＴＤ回路。10.10a...address buffer, 11...X-
Decoder, 12...Memory matrix, 13...Y
-Selector, 14--Sense amplifier, 15--Output buffer, 16--DTD circuit.

Claims (1)

【特許請求の範囲】[Claims] メモリマトリクスからの出力を増幅したセンスアンプの
出力信号あるいはこのセンスアンプの出力信号を増幅し
た出力バッファの駆動信号の変化を検出する信号変化検
出回路を設け、入力バッファ部の入力信号がこの信号変
化検出回路の出力信号により一定期間ラッチされるよう
にしたことを特徴とする読出専用メモリ。A signal change detection circuit is provided to detect changes in the output signal of the sense amplifier that amplifies the output from the memory matrix or the drive signal of the output buffer that amplifies the output signal of this sense amplifier, and the input signal of the input buffer section detects this signal change. A read-only memory characterized in that it is latched for a certain period of time by an output signal of a detection circuit.
JP2233062A 1990-09-03 1990-09-03 Read-only memory Pending JPH04113595A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2233062A JPH04113595A (en) 1990-09-03 1990-09-03 Read-only memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2233062A JPH04113595A (en) 1990-09-03 1990-09-03 Read-only memory

Publications (1)

Publication Number Publication Date
JPH04113595A true JPH04113595A (en) 1992-04-15

Family

ID=16949204

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2233062A Pending JPH04113595A (en) 1990-09-03 1990-09-03 Read-only memory

Country Status (1)

Country Link
JP (1) JPH04113595A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6489098A (en) * 1987-09-30 1989-04-03 Toshiba Corp Semiconductor memory device
JPH02177090A (en) * 1988-12-27 1990-07-10 Nec Corp Semiconductor storage device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6489098A (en) * 1987-09-30 1989-04-03 Toshiba Corp Semiconductor memory device
JPH02177090A (en) * 1988-12-27 1990-07-10 Nec Corp Semiconductor storage device

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