JPH0411179Y2 - - Google Patents

Info

Publication number
JPH0411179Y2
JPH0411179Y2 JP1983200706U JP20070683U JPH0411179Y2 JP H0411179 Y2 JPH0411179 Y2 JP H0411179Y2 JP 1983200706 U JP1983200706 U JP 1983200706U JP 20070683 U JP20070683 U JP 20070683U JP H0411179 Y2 JPH0411179 Y2 JP H0411179Y2
Authority
JP
Japan
Prior art keywords
circuit
open
short
threshold
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1983200706U
Other languages
Japanese (ja)
Other versions
JPS60111278U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP20070683U priority Critical patent/JPS60111278U/en
Publication of JPS60111278U publication Critical patent/JPS60111278U/en
Application granted granted Critical
Publication of JPH0411179Y2 publication Critical patent/JPH0411179Y2/ja
Granted legal-status Critical Current

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  • Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)

Description

【考案の詳細な説明】 技術分野 本考案はオープン/シヨートインサーキツトテ
スタに関する。
[Detailed Description of the Invention] Technical Field The present invention relates to an open/short in-circuit tester.

背景技術 第1図は従来のオープン/シヨートインサーキ
ツトテストの回路構成を示している。最初、基準
となる被測定プリント基板1の抵抗2を流れる電
流が演算増幅器3で増幅された後、比較器4で基
準電圧5で、例えば10Ωの閾値と比較され抵抗2
の抵抗値が10Ωより大きければオープン、小さけ
ればシヨートのデータが判定回路6によりメモリ
7に記憶される。そして、以後の実テストで他の
被測定プリント基板の抵抗について同様にして求
められたオープンかシヨートかの結果が、基準と
なる被測定プリント基板1について求められ、メ
モリ7に記憶されたオープンかシヨートかのデー
タと判定回路6で比較され、一致しておれば
“可”、一致していなければ“不可”と判定され
る。
BACKGROUND ART FIG. 1 shows the circuit configuration of a conventional open/short in-circuit test. First, the current flowing through the resistor 2 of the printed circuit board 1 to be measured, which serves as a reference, is amplified by the operational amplifier 3, and then the comparator 4 compares the current flowing through the resistor 2 with a reference voltage 5 of, for example, 10Ω.
If the resistance value is larger than 10Ω, the data is open, and if it is smaller, the data is stored in the memory 7 by the judgment circuit 6. Then, in subsequent actual tests, the open or short results obtained in the same manner for the resistances of other printed circuit boards to be measured are obtained for the reference printed circuit board to be measured 1 and stored in the memory 7. It is compared with the short data by the determination circuit 6, and if they match, it is determined to be "acceptable", and if they do not match, it is determined to be "impossible".

しかしながら、この従来のインサーキツトテス
タでは、閾値レベルを設定する基準電圧5は最初
のデータ吸い上げ時と以後の実テスト時とで同じ
である。抵抗2の抵抗値が10Ωで±10%のばらつ
きを有する場合、このばらつきのためにオープ
ン/シヨートについて誤判定を生じていた。
However, in this conventional in-circuit tester, the reference voltage 5 for setting the threshold level is the same at the time of initial data acquisition and at the time of subsequent actual testing. When the resistance value of the resistor 2 is 10Ω and has a variation of ±10%, this variation causes an erroneous determination as to open/short.

考案の開示 したがつて、本考案の目的は、部品の抵抗値の
バラツキによる誤判定を無くしたオープン/シヨ
ートインサーキツトテスタを提供することにあ
る。
DISCLOSURE OF THE INVENTION Accordingly, an object of the present invention is to provide an open/short insert circuit tester that eliminates false judgments due to variations in resistance values of components.

このために、本考案は、部品のデータに応じた
閾値レベルを自動的に設定できるようにしたもの
である。
To this end, the present invention is capable of automatically setting a threshold level according to component data.

これにより、部品のバラツキによる誤判定を無
くすことができる。
This makes it possible to eliminate erroneous determinations due to component variations.

考案を実施するための最良の形態 以下、本考案の一実施例を図面を参照しながら
説明する。第2図は本考案の1実施例に係るオー
プン/シヨートインサーキツトテスタの回路図で
ある。
BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, one embodiment of the present invention will be described with reference to the drawings. FIG. 2 is a circuit diagram of an open/short in-circuit tester according to an embodiment of the present invention.

本実施例は10Ωをオープン、シヨートの判定基
準とするもので、第1図の従来回路に、10Ω以下
の被測定部品に対しては5Ω、10Ω以上の被測定
部品に対しては20Ωの閾値を記憶したメモリ7、
被測定部品の抵抗値に応じた閾値をメモリ7から
読出す閾値選択回路8、メモリ7から読出された
閾値をデジタル/アナログ変換して、比較器4の
基準電圧として設定するD/A変換器9を設けた
ものである。したがつて、被測定部品の抵抗値
(基準値10Ω)が上方にばらついて11Ωの場合に
は5Ωの閾値がD/A変換器9に設定されてシヨ
ートと判定され、下方にばらついて9Ωの場合に
は20Ωの閾値がD/A変換器9に設定されてオー
プンと判定される。すなわち、抵抗値のばらつき
によるオープン/シヨートの誤判定が無くなる。
なお、閾値の選択はメモリ7に記憶された最初の
吸い上げデータによる。
In this example, 10Ω is used as the open/short judgment criterion, and the conventional circuit shown in Fig. 1 has a threshold of 5Ω for a component under test of 10Ω or less, and a threshold of 20Ω for a component under test of 10Ω or more. memory 7 that stores
a threshold selection circuit 8 that reads out a threshold value corresponding to the resistance value of the component to be measured from the memory 7; a D/A converter that converts the threshold value read out from the memory 7 into digital/analog and sets it as a reference voltage for the comparator 4; 9. Therefore, if the resistance value of the part to be measured (standard value 10Ω) varies upward and is 11Ω, a threshold of 5Ω is set in the D/A converter 9 and it is judged as short; In this case, a threshold value of 20Ω is set in the D/A converter 9 and it is determined that it is open. That is, erroneous open/short determinations due to variations in resistance values are eliminated.
Note that the selection of the threshold value is based on the first downloaded data stored in the memory 7.

なお、メモリ7およびD/A変換器9の代り
に、比較器4に基準電圧をスイツチを介して複数
並列に接続し、閾値選択回路8の出力によりスイ
ツチを切換えて所定の基準電圧を選択するように
してもよい。
Note that instead of the memory 7 and the D/A converter 9, a plurality of reference voltages are connected in parallel to the comparator 4 via a switch, and a predetermined reference voltage is selected by switching the switch based on the output of the threshold selection circuit 8. You can do it like this.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のオープン/シヨートインサーキ
ツトテスタの概略回路図、第2図は本考案の1実
施例に係るオープン/シヨートインサーキツトテ
スタの概略回路図である。 3……演算増幅器、4……比較器、6……判定
回路、7……メモリ、8……閾値選択回路、9…
…D/A変換器。
FIG. 1 is a schematic circuit diagram of a conventional open/short in-circuit tester, and FIG. 2 is a schematic circuit diagram of an open/short in-circuit tester according to an embodiment of the present invention. 3... Operational amplifier, 4... Comparator, 6... Judgment circuit, 7... Memory, 8... Threshold selection circuit, 9...
...D/A converter.

Claims (1)

【実用新案登録請求の範囲】 オープン/シヨートインサーキツトテスタにお
いて、 被測定部品の抵抗値それぞれに応じて所定の閾
値を複数有する閾値メモリ回路と、 被測定部品の抵抗値に応じた閾値を前記閾値メ
モリ回路から選択し、オープン/シヨート判定の
比較器の基準電圧としてセツトする閾値選択回路
とを有することを特徴とするオープン/シヨート
インサーキツトテスタ。
[Claims for Utility Model Registration] An open/short in-circuit tester comprising: a threshold memory circuit having a plurality of predetermined threshold values according to the resistance values of the parts to be measured; An open/short in-circuit tester comprising a threshold selection circuit that selects a threshold value from a threshold memory circuit and sets it as a reference voltage of a comparator for open/short determination.
JP20070683U 1983-12-29 1983-12-29 Open/short insert kit tester Granted JPS60111278U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20070683U JPS60111278U (en) 1983-12-29 1983-12-29 Open/short insert kit tester

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20070683U JPS60111278U (en) 1983-12-29 1983-12-29 Open/short insert kit tester

Publications (2)

Publication Number Publication Date
JPS60111278U JPS60111278U (en) 1985-07-27
JPH0411179Y2 true JPH0411179Y2 (en) 1992-03-19

Family

ID=30761806

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20070683U Granted JPS60111278U (en) 1983-12-29 1983-12-29 Open/short insert kit tester

Country Status (1)

Country Link
JP (1) JPS60111278U (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013242251A (en) * 2012-05-22 2013-12-05 Hioki Ee Corp Continuity testing apparatus and continuity testing method
US9423444B2 (en) * 2013-07-29 2016-08-23 Biosense Webster (Israel), Ltd. Identifying defective electrical cables

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6319811Y2 (en) * 1980-10-20 1988-06-02

Also Published As

Publication number Publication date
JPS60111278U (en) 1985-07-27

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