JPH04111651A - Phase locked loop circuit - Google Patents

Abstract

PURPOSE:To reduce the synchronization lock time by providing a phase comparison characteristic to a phase history discrimination circuit in which its output phase control voltage is a prescribed positive or negative voltage with respect to a synchronization stabilizing point. CONSTITUTION:A phase history discrimination circuit 6 receiving outputs of comparators 3,4 is provided on the circuit. An output of the circuit 6 is given to amplifiers 8, 9, which output a prescribed voltage of +A or -A based on a phase difference phi between an input signal and a recovery signal and its phase history. That is, when the phase difference phi is (4n+1)m/2-(4n+3)pi/2, a prescribed voltage of +A or -A opposite to each other is outputted in response to the history of the phase difference phi. Then the prescribed voltage and a phase control voltage outputted from an amplifier 7 are synthesized in a synthesis circuit 10 and given to an amplitude control circuit 11, from which a phase control voltage Vd applied to a phase synchronization circuit is outputted. Thus, stable and rapid locking to a synchronization stable point is attained and the synchronization lock time is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a phase synchronized circuit, and more particularly to a phase synchronized circuit used in a receiving side demodulation device of a multilevel digital wireless communication device.

[Conventional technology]

An example of a conventional phase locked circuit of this type is shown in FIG. As shown in the figure, the input signal is branched into two and input into phase detectors 1 and 2, respectively, where the π/2 phase shifter 5
voltage controlled oscillators (
The signal is detected by the reproduced signal from the VCO). The outputs of these phase detectors 1.2 are converted into digital signals by two comparators 3.4, and are converted into binary digital signals, D
, will be output. Further, the output of one phase detector 2 is amplified by an amplifier 7 and outputted as a phase control voltage (6) for controlling (2) CO.

According to this phase synchronization circuit, the input signal is subjected to quadrature detection by the two phase detectors 1.2, and signals of sin φ and cos φ are output for the phase difference φ between the input signal and the reproduced signal, respectively. These two signals are then sent to each comparator 3.
4, the binary digital signals DP, D
It can be output as Q.

On the other hand, the phase control voltage necessary to obtain the reproduced signal is
As shown in the phase comparison characteristic in the figure, it is expressed as sinφ, and s
It is obtained by amplifying the phase detection output of inφ with the amplifier 7.

[Problem to be solved by the invention]

In the conventional phase synchronization circuit described above, as shown in the phase comparison characteristics in FIG. 2nx 3rad E (n
: O, ±1. ±2. . As a result, when the phase difference φ is near this pseudo-synchronization stable point, it becomes easier to be pulled toward the pseudo-synchronization stable point, and it takes a significantly longer synchronization pull-in time to reach the original synchronization pull-in point. There was one problem.

SUMMARY OF THE INVENTION An object of the present invention is to provide a phase-locked circuit in which synchronization pull-in time is shortened.

[Means to solve the problem]

The phase-locked circuit of the present invention includes two phase detectors that detect an input signal from reproduced signal numbers having mutually different phases of π/2 output from a voltage controlled oscillator, and converts the outputs of these phase detectors into a binary signal. Two comparators that convert into digital signals, and phase control based on the phase difference between the input signal and the reproduced signal (based on the means for outputting the word and the history of the phase difference) using the output of the phase detector to control the polarity of each other. a phase history discriminator circuit that outputs constant voltages inverted from each other, a synthesis circuit that synthesizes the phase control signal and the signal from the phase history discrimination circuit, and a phase control circuit that limits the amplitude of the signal output from this synthesis circuit. and an amplitude limiting circuit that outputs a voltage.

In this case, the means for outputting the phase control signal has a phase difference φ of (4n-1)π/2 to (4n+1)π/2, (n:
O, ±1. ±2. ..., hereinafter the same), the phase difference φ
Phase system based on? The phase history discrimination circuit outputs the il voltage and determines whether the phase difference φ is between (4n+1)π/2 and (4n+3)π/
2, +A or -A depending on the history of the phase difference φ
[Operation] According to the present invention, the output phase control voltage has a phase comparison characteristic that goes from the synchronization stable point to a constant voltage in ten directions or one direction. A pseudo synchronous stable point does not occur, and the phase can be stably and quickly drawn toward the synchronous stable point.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of a phase locked circuit according to the present invention. Note that the same parts as in the conventional configuration shown in FIG. 3 are given the same reference numerals. That is, 1.2 is a phase detector, and π
By passing through the /2 phase shifter 5, the phases differ by π/2
The branched input signals are each detected using the reproduced signal from the CO. Further, 3.4 is a comparator that converts the output of the phase detector 1.2 into binary digital signals Dr and DQ.

Further, 7 is an amplifier that amplifies the output of the phase detector 2, and from this amplifier 7, the phase difference φ between the input signal and the reproduced signal is (4n1)π/2 to (4n1) so as to control CO.
+1) When π/2, a phase control voltage based on the phase difference φ is output.

Furthermore, here, a phase history discrimination circuit 6 is provided to which the output of the comparator 3.4 is input. This phase history discrimination circuit 6 has a flip-flop circuit composed of logic elements such as a NOR circuit and an AND circuit, and its two output terminals are connected to inverting and non-inverting amplifiers 8 and 9, respectively. . In this phase history discrimination circuit 6, the amplifiers 8 and 9 output a constant voltage of 7A or a constant voltage of -A depending on the phase difference φ between the input signal and the reproduced signal and the phase history thereof. That is, the phase difference φ is (4nA-,1)π/2~(4n+
3) When π/2, outputs a constant voltage of +A or -A with mutually inverted polarities depending on the history of the phase difference φ.

Then, these constant voltages and the conventional phase control voltage output from the amplifier 7 are combined in a combining circuit IO,
It passes through the amplitude control circuit 11 and is output as a phase control voltage (4) applied to the phase locked circuit of this example.

The conditions for this output are as follows.

Taking as an example the section where the phase difference φ is from 13/2π to +3/2π, (1) −π/2≦φ≦+π/2 Conventional phase control voltage (2) −3/2π≦φ≦−π /2 (3) π/2≦φ≦−3/2 πdoA ($6“
/2(7)(nNffff~1(-A (when there is a phase history of φ≧3/2π). In the section (1), the conventional phase side ?11 voltage is as shown in Fig. In a phase locked circuit, it represents a sine wave output of "A·sinφ".

As a result, the phase control voltage output from this phase-locked circuit has a phase difference φ, as shown in FIG.
The characteristic is that the voltage can be switched as a constant voltage in the child direction or in one direction.

Therefore, the phase control voltage does not become 0 at the pseudo-synchronized stable point, and even when the pseudo-synchronized stable point is eliminated and the phase difference φ is near the pseudo-synchronized stable point, the i-direction changes depending on the phase history. Or it can be stably and rapidly drawn to the original synchronous stable point of 2nπ [rad] in one direction,
It becomes possible to shorten the synchronization pull-in time.

(Effects of the Invention) As explained above, the present invention provides a phase history discrimination circuit and has a characteristic that the phase control voltage is constant in the ground direction or in one direction depending on the value of the phase difference and its history. Even when the synchronization stable point is eliminated and the phase difference is near this pseudo synchronization stable point, it is possible to stably and rapidly pull into the original synchronization stable point, thereby shortening the synchronization pull-in time.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an embodiment of the phase-locked circuit of the present invention, FIG. 2 is a phase comparison characteristic diagram of the present invention, FIG. 3 is a circuit diagram of a conventional phase-locked circuit, and FIG. FIG. 3 is a phase comparison characteristic diagram in a phase locked circuit of FIG. 1.2... Phase detector, 3, 4... Comparator, 5...
・π/2 phase shifter, 6... Phase shift history discrimination circuit, 7 to 9・
...Amplifier, 10...Synthesizing circuit, 11...Amplitude limiting circuit. Fig. 2 Fig. 4

Claims (1)

[Claims] 1. In a phase synchronized circuit used in a receiving side demodulator of a multi-level digital micro wireless communication device, an input signal is detected using reproduced signals output from a voltage controlled oscillator and having mutually different phases by π/2. two phase detectors, two comparators that convert the outputs of these phase detectors into binary digital signals, and a phase control signal based on the phase difference between the input signal and the reproduced signal using the output of the phase detector. a phase history discrimination circuit that outputs constant voltages whose polarities are reversed based on the phase difference history; a synthesis circuit that synthesizes the phase control signal and the signal from the phase history discrimination circuit; A phase synchronized circuit comprising: an amplitude limiting circuit that limits the amplitude of a signal output from the circuit and outputs a phase control voltage. 2. The means for outputting the phase control signal has a phase difference φ of (4n
-1) π/2 ~ (4n+1) π/2, [n: 0, ±1,
±2,..., the same applies hereinafter], the phase control voltage based on the phase difference φ is output, and the phase history discrimination circuit outputs the phase control voltage when the phase difference φ is (4n+1)π/2 to (4n+3)π/2. 2. The phase locked circuit according to claim 1, which outputs a constant voltage of +A or -A with opposite polarities depending on the history of the phase difference φ.