JPS6238665B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a delayed feedback synthesis type pulse width expansion device used, for example, when delaying a high frequency pulse signal or measuring the carrier frequency of a pulse modulated wave.

The basic configuration of a conventional delayed feedback synthesis loop is shown in FIG.

In the figure, 1 is a pulse width limiter, 2 is a delay line with delay time τ, 3 is a superimposition circuit, 4 is a compensation amplifier,
5 is a gate switch, and 6 is a variable phase shifter. In such a delayed feedback synthesis loop, the input signal 101
is input to the pulse width limiter 1. The pulse width limiter 1 has a function of limiting the input signal 101 to a length equal to the delay time τ of the delay feedback loop.
Compensation amplifier 4 sets the loop gain of the delayed feedback loop to 1.
It has the function to match.

The input signal 101 has the waveform shown in FIG.
The short pulse signal 102, which has a spectrum as shown in Figure a, and output from the pulse width limiter 1 has a waveform as shown in Figure 2b, and its frequency spectrum is as shown in Figure 3b. These waveforms and spectra are expressed by equations (1a) and (1b) _{f 1} (t) = Arect (t/τ) e ^j2 〓 ^f ₀ ^t ... (1a) f-f ₀ τ)/π(f-f ₀ )
τ...(1b) However, rect(t/τ) is a rectangular pulse with pulse width τ centered at t=0. The short pulse signal 102 is n
By passing through the feedback synthesis loop and turning off the gate switch 5, an expanded pulse output signal 103 as shown in FIG. 2c is obtained. The spectrum of the expanded pulse output signal 103 is as shown in FIG. 3c. Expressing these as formulas, they become formulas (2a) and (2b).

However, θ: Phase difference at pulse junction 2πf ₀ τ = 2nπ + △φ (n: integer) △f = △φ/2πτ f ₁ = f ₀ + △f Therefore, Fn(f) = Aτsinπ (f - f ₀ ) τ /π(f−f ₀ )τ×
sin2πn(f- _f1 )τ/sinπ(f- _f1 )τ
...(2b) That is, f ₀ ≠n/τ ∴△φ≠0 ...(3) In the case of (3), the phase of the junction of each short pulse in Fig. 2c becomes discontinuous, and the spectrum of the expanded pulse output signal 103 The input signal 101 becomes as shown in Fig. 3c.
The carrier wave frequency f ₀ of the output signal 103 and the carrier wave frequency f ₁ of the output signal 103 are not equal.

Note that Δφ is a quantity representing phase discontinuity.

In the case of f ₀ =n/τ ∴△φ=0...(4), the phase discontinuity at the short pulse junction of the output signal 103 disappears, and the spectrum becomes as shown in Fig. 3d.
As in, f ₀ = f ₁ and the sideband component becomes minimum.

Therefore, in order to extend the pulse width without changing the carrier frequency, it is necessary to make the phase shifter 6 variable and adjust it to a value that satisfies equation (4). Conventionally, there was no suitable means to automatically match the phase shift amount of this delay loop, so it was used with the phase discontinuity remaining, or the elongated pulse output was observed with a spectrum analyzer to determine the spectrum. The variable phase shifter 6 was manually adjusted to minimize the phase discontinuity in the extended pulse as shown in Figure 3d. In addition, in order to automatically match the phase shift amount of this delay loop, a method as shown in Figure 4 has been considered in the past, but this method reduces the noise contained in the input signal and the noise generated in the delay feedback loop. It is very difficult to operate stably due to the influence.

The method shown in Fig. 4 is based on the input signal 1 shown in Fig. 5a.
01 and the signal 104 which has passed through the delay feedback circuit one or more times and is delayed.
The phase detector 7 detects the phase difference between the two and the phase shifter 6 is controlled so that this phase difference becomes zero. The system shown in FIG. 4 is a system in which an automatic phase matching circuit is added to the delayed feedback synthesis loop shown in FIG. delayed signal {5th
c} and the input signal {Fig. 5a} input to the pulse width limiting circuit 1 is detected, and a detection signal proportional to this phase difference is extracted with the waveform shown in Fig. 5d. The detection signal is then input to the sample and hold circuit 8 and sampled and held as shown in FIG. Output. This control signal is supplied to the variable phase shifter 6, and the variable phase shifter 6 is controlled so that the phase difference becomes zero. This method has the disadvantage that the pulse width of the input signal needs to be approximately twice the pulse width limit value τ.In addition, the time to detect the phase error is short at τ ₀ −τ, so the bandwidth of the detection system can be widened. It also has the disadvantage of being susceptible to noise.

This invention has a stable automatic phase control circuit (APC circuit) that automatically controls the amount of phase shift of a delayed feedback synthesis loop, and can generate pulse modulated waves using a delayed feedback loop that operates stably over a wide frequency range. The purpose of this invention is to provide a pulse width stretching device.

An embodiment of the present invention shown in FIG. 6 will be described below. In the embodiment shown in FIG. 6, first, a pulse width limiter 1 and a delay line are connected to an intermediate frequency circuit formed after a first frequency converter 22 which operates using the output of an electronically controlled oscillator (VCO) 20 as a local signal. 2. As in FIG. 1, there is a delayed feedback synthesis loop composed of a superimposing circuit 3, a compensation amplifier 4, a gate switch 5, and a variable shifter 6. In addition to the electronically controlled oscillator (hereinafter referred to as VCO) 20 and the first frequency converter 22, it is composed of a phase detector 7, a reference signal oscillator 23, and a phase-locked loop filter 21, and the delayed feedback synthesis loop is Output signal 1
03 carrier wave component and the output 1 of the reference signal oscillator 23
19 {FIG. 8c, FIG. 9b, and FIG. 10b} A phase synchronization circuit (hereinafter referred to as a PLL circuit) that automatically controls the VCO 20 so as to phase-synchronize the VCO 20 is added to the delay feedback loop. In addition, the residual phase error of the PLL circuit is extracted from the output 107 of the phase detector (Fig. 9 c, Fig. 10 c), and the phase ripple component of the delayed feedback synthesis output 103 is detected and the open loop transmission of the delayed feedback synthesis loop is performed. In order to automatically control the phase amount, a bandpass filter 11 and a synchronous demodulator 1 are used.
2. An automatic phase matching circuit (hereinafter referred to as APC circuit) consisting of an integral hold circuit 8, an APC loop filter 9, and a timing pulse generator 13 is also added. The operation of the delayed feedback synthesis loop is exactly the same as that explained earlier using Figures 1, 2, and 3, except that the signal is converted to an intermediate frequency signal and then passes through the loop, so it will be explained here. Now, I will omit the explanation and explain the PLL system and APC system.
The waveforms of each part in FIG. 6 are shown in FIG. 7, and the signal spectra are shown in FIGS. 8, 9, and 10, respectively.

Figure 8 shows the spectrum when neither the PLL circuit nor the APC circuit is locked on, and Figure 9 shows the spectrum when both the PLL circuit and APC circuit are not locked on.
The PLL circuit is locked on and the APC circuit is locked off. Figure 10 shows the spectrum of the PLL circuit.
The spectra are shown when both the circuit and the APC circuit are locked on.

FIG. 8 and the following explanation assume that the carrier frequency f ₀ of the input signal 101 and the intermediate frequency signal 102 of FIG.
The relationship between the carrier wave frequency f _IFO and the frequency f _VCO of the output 118 of the electronically controlled oscillator 20 will be explained as follows.

f _IFO = f ₀ - f _VCO (1) However, it is applicable not only to equation (1) but also to equation (2) below.

f _IFO = mf ₀ ±n f _VCO (m, n: arbitrary integers) ...(2) The phase detector 7 generates a delayed feedback composite output signal 103 having the spectrum shown in FIG. 8b and a delayed feedback composite output signal 103 having the spectrum shown in FIG. 8c. The phase difference between the frequency f _REF and the reference signal is detected to obtain the waveform shown in FIG. 7c.

The PLL circuit extracts only this low frequency and DC component of the phase detection circuit using a PLL loop filter.
By changing the oscillation frequency of the VCO 20 and thereby changing the frequency of the intermediate frequency signal, the phase of the carrier component f ₁ of the delayed feedback composite output shown in FIG. 8b is synchronized with the reference signal 119 {FIG. 8c}. let Therefore, when the PLL circuit is locked on, f ₁ = f _RE
F , resulting in the spectrum shown in FIG.

In the APC circuit, when the PLL circuit is locked on, the output signal of the phase detector 7 {shown in FIG. 7d} has a passing center frequency of 1/τ (Hz) {however, τ
= short pulse width (sec)}, extract the component of f≒1/τ {only the component generated by the first sideband component of the delayed feedback composite output 103 shown in FIG. 9a}. , a ripple (waveform) signal shown in FIG. 7e is obtained. This ripple signal is called a phase ripple signal 108, and its spectrum is as shown in FIG. 9d, and the amplitude is as shown in FIG. 9a.
It is proportional to the amplitude of the sideband component shown in , and is proportional to the sine value sin Δφ of the phase error Δφ of the output of the delayed feedback loop.

On the other hand, the timing pulse generator 13 is operated by the signal timing pulse signal 109 which detects the operation time of the pulse width limiter 1, and the seventh
Synchronous timing pulse signal 1 with period τ shown in Figure f
Generate 10.

Next, the synchronous demodulator 12 outputs the phase ripple signal 1.
08 is subjected to synchronous detection using the synchronous timing pulse signal 110 as a reference, and a pulse component 111 as shown in FIG. 7g, which is synchronized with the circulation cycle of the short pulse signal in the delayed feedback synthesis loop, is extracted. As it is, the waveform of the pulse component 111 is a full-wave rectified waveform with an intermittent width nτ as shown in FIG. It is converted into a DC voltage signal 112 as shown in FIG. 7h. This DC voltage signal 112 is proportional to the sine value sinΔφ of the loop phase error Δφ of the delayed feedback synthesis loop. Therefore, this value of Δφ is called a phase error voltage signal 112. This phase error voltage signal 112 is fed back to the variable transfer device 6 of the delayed feedback synthesis loop through the APC loop filter 9 to control the amount of phase shift of the delayed feedback synthesis loop so that the loop phase error △φ is always zero. do. Note that the synchronous demodulator 12 has a period τ
Since only the components that are synchronized with the reference timing pulse are extracted, the bandpass filter 11 inserted between the phase detector 7 and the synchronous demodulator 12 is not essential.

Therefore, both the PLL circuit and the APC circuit are locked.
When turned on becomes.

In this state, the signal spectrum of each part is 10th
As shown in the figure, the delayed feedback synthesis loop output 103 shown in FIG. 10a is the reference signal 1 in FIG.
Since the phase is synchronized with 19 and the sideband component is almost eliminated, the waveform becomes a continuous long pulse modulated wave with no phase fluctuation, and the carrier frequency f ₁ is f ₁ =f _IFO ·(=f _REF ). Therefore, this delayed feedback composite output 103
If the second frequency converter 24 converts the frequency again using the output 118 of the VCO 20, the output 12
When the carrier frequency is set to 0, a continuous long pulse modulated wave with no phase fluctuation with a carrier frequency of f _IFO + f _VCO = f ₀ is obtained. Depending on the application, this second frequency converter 2
4, the input carrier frequency f ₀ , the output carrier frequency f _IFO , and the local signal frequency f _VCO can be synchronized, and the relationship f _IFO = f ₀ − f _VCO = f _REF can be maintained. There may be cases where this is fine.

In this method, a PLL circuit is used to control the local signal so that the carrier component of the delayed feedback composite output 103 is synchronized with the reference signal, and then the delayed feedback composite output 10
Only the components synchronized with the delayed feedback synthesis cycle of phase fluctuations in step 3 are extracted by synchronous demodulation and used as the phase error detection voltage of the APC circuit, so phase changes caused by the delayed feedback cycle can be efficiently detected. As a result, the S/N ratio of the phase error detection system can be significantly improved, and control errors and fluctuations caused by noise generated inside the delayed feedback synthesis loop and thermal noise of the input RF signal are significantly reduced, resulting in stable Automatic phase control can be performed. Furthermore, in order to configure the delayed feedback synthesis loop in the intermediate frequency circuit and incorporate it into the PLL circuit that controls the phase synchronization of the local oscillator, the required bandwidth of the delayed feedback synthesis loop was significantly narrowed, and the PLL circuit was locked on. In this state, the frequency f _REF almost matches the reference signal, so that control errors due to the frequency-phase characteristics of the delayed feedback synthesis loop can be eliminated.

Next, FIG. 11 shows another embodiment of the present invention, and FIG. 12 is a signal waveform diagram of each part in FIG. 11. In this embodiment, a high frequency gate circuit 28 is provided at the output of the pulse width expansion device, and a delay pulse generator 29 is used to generate the signal at an arbitrary time delayed timing from the signal input timing 109 shown in FIG. 12d to the timing shown in FIG. 12e. By interrupting the signal for an arbitrary period of time, the pulse modulated wave shown in Fig. 10f, which has the same carrier frequency as the input short pulse modulated wave, is delayed by an arbitrary time, and has an arbitrary pulse width can be generated. It has the added function of converting to . Note that in this embodiment, the high frequency gate circuit 28 is connected to the second frequency converter 2.
It may be provided at either the front stage or the rear stage of 4.

As described above, the delayed feedback synthesis type pulse width stretching device according to the present invention has an automatic phase control circuit (APC).
A delayed feedback synthesis loop with a circuit) is configured in an intermediate frequency circuit, and a phase-locked control circuit (PLL circuit) is provided to control a local signal oscillator for frequency conversion.
The carrier wave component of the delayed feedback synthesis output is controlled to be phase-synchronized with the reference signal, and at the same time, the component synchronized with the delayed feedback cycle of the delayed feedback synthesis loop is extracted from the residual error of the phase control of this PLL circuit by the action of this APC circuit. is configured to detect phase discontinuity in the pulse junction portion of the delayed feedback synthesis output and to control a variable phase shifter provided in the delayed feedback synthesis loop so that this phase discontinuity becomes zero. There is. Therefore, automatic phase control of the delayed feedback synthesis loop can be performed stably against noise generated in the delayed feedback synthesis loop, thermal noise included in the input signal, and other external noise, and the phase is always continuous and the carrier frequency does not shift. A pulse width expanded output can be obtained. In addition, due to the function of the PLL circuit, the carrier frequency of the output signal of the delayed feedback synthesis loop is kept equal to the reference signal frequency regardless of the high frequency input frequency, so the required bandwidth of the delayed feedback synthesis loop is equal to the high frequency input frequency range. Regardless, it becomes very narrow and the influence of the open-loop frequency characteristic of the delayed feedback synthesis loop can be avoided.

[Brief explanation of the drawing]

Figure 1 is a block configuration diagram showing the basic configuration of a single-carrier delayed feedback synthesis loop, Figure 2 is a waveform diagram showing the waveforms of each part in Figure 1, and Figure 3 is the frequency of the waveform of each part in Figure 2. Spectrum diagram, Figure 4 is a block configuration diagram showing a conventional delayed feedback synthesis loop with an automatic phase matching function, Figure 5 is a waveform diagram showing waveforms of each part of the system in Figure 4, and Figure 6 is a diagram showing the waveform of the system of the present invention. A block configuration diagram showing one embodiment, Fig. 7 is a waveform diagram showing waveforms of each part of the system in Fig. 6, and Figs. 8, 9, and 10 show frequency spectra of waveforms in each part of the system shown in Fig. 7. 11 and 13 are block diagrams showing other embodiments of the present invention, and FIG. 12 is a signal waveform diagram at each part of the embodiment of FIG. 11. In the figure, 1 is a pulse width limiter, 2 is a delay line, 3 is a superimposition circuit, 5 is a gate switch, 6 is a phase shifter, and 7
is a phase detector, 8 is an integral hold circuit, 9 is a
APC loop filter, 12 is a synchronous demodulator, 13
20 is a timing pulse generator, 20 is an electronically controlled oscillator, 21 is a PLL loop filter, 22 is a first frequency converter, 23 is a reference signal oscillator, and 24 is a frequency converter. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] 1. In a pulse width stretching device that stretches the pulse width of a pulse modulated wave using a delayed feedback synthesis loop having a phase shifter, an electronically controlled oscillator and an output of the electronically controlled oscillator are used as local signals for the delayed feedback synthesis loop. a frequency converter for converting an input signal into an intermediate frequency signal; a reference signal oscillator; and a phase detector for detecting a phase difference between a reference output of the reference signal oscillator and an output of the delayed feedback synthesis loop; a phase synchronization circuit that varies the output of the electronically controlled oscillator so that the phase of the carrier component of the output of the delayed feedback synthesis loop is synchronized with the phase of the reference output by the output of the phase detector; and circulation of the delayed feedback synthesis loop. A reference timing pulse generator generates a synchronized timing signal synchronized with the cycle, and a component synchronized with the circulation cycle of the delayed feedback synthesis loop is detected from the output of the phase detector using this synchronized timing signal. a synchronous demodulator that varies the amount of phase shift of the phase shifter; and an automatic phase matching circuit that varies the amount of phase shift of the phase shifter so that the output of the synchronous demodulator becomes zero. Equipped with a pulse width stretching device.