JPH04111028A - Programmable storage device - Google Patents

Abstract

PURPOSE:To shorten the time when all signals are stabilized in a memory and the system access time to a storage device by generating address data and writing the address data in a program memory means. CONSTITUTION:The device is provided with a program memory 6 for storing an address generation program instead of inputting an address signal from the outside, a circuit 4 for writing program data in the program memory 6, and a sequence control circuit 3 of the program memory. In such a state, the program writing circuit 4 writes address data in the program memory 6. Subsequently, the control circuit 3 sets a data memory 1 to a read-out mode or a write mode. Also, when a clock signal is supplied to the program memory 6, an address signal is generated, and read-out or write of data is executed with respect to an address designated by the address signal. In such a way, the time when the address signal is propagated through an external circuit and a delay time of an address input circuit become unnecessary, and an access time in a read-out operation of the data memory is shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a programmable storage device, and particularly to a storage device for automatic access by a program.

[Prior Art] As shown in FIG. 2, a conventional storage device includes an address input circuit 8 supplied with a multi-bit address signal 801 supplied from the outside, and an address signal outputted from the address input circuit 8. a data memory 1 that inputs a signal to read or write data; a data input/output circuit 2 that inputs and outputs a data signal 201 between the data memory 102 and the outside; and a data input/output circuit 2 that inputs a control signal 301 from the outside. A control circuit 3 for controlling read or write operations of the data memory 1 is provided.

FIG. 3 shows an application example of a conventional storage device, which is a storage device that actually exists for purposes such as cache memory. Third
The conventional example shown in the figure includes an address input circuit 8 which manually inputs a multi-bit address signal 801 supplied from the outside, and a data memory l which inputs a lower address signal 803 of the address input circuit 8 to read or write data. , data memory 1 by inputting an external control signal 301.
A lower address signal 803 is inputted from the control circuit 3 that controls the read or write operation of the address input circuit 8, and an address signal 801 from the outside that was previously stored is input.
Read the upper address of or address input circuit 8
a tag memory 9 into which the upper address signal 804 of the tag memory 9 is written;
an address comparison circuit 10 that inputs the read data signal 901 from the tag memory 9 and the upper address signal 804 of the address input circuit 8 and checks whether they match;
a tag memory control circuit 11 that inputs the match signal 1001 from the address comparison circuit 10 and controls writing of the upper address signal 804 to the tag memory 9 as data;
The data input/output circuit 2 inputs and outputs the data signal 201 between the data memory 1 and the outside, and controls the output of the data signal 102 from the data memory 1 to the outside based on the match signal 1001 from the address comparison circuit 10.

[Problems to be Solved by the Invention] This conventional storage device has the following problems because it inputs a multi-bit address signal from the outside.

First, a multi-bit address signal is propagated from the external circuit to the address input circuit 8, and then it takes time for all the signals in the memory 1 to become stable, resulting in a problem that the system access time to the storage device is long. Furthermore, as the number of words increases due to the increase in memory capacity, the number of address signal pits and, by extension, the number of external terminals also increase.As a result, the number of man-hours required for mounting the memory device increases, and the mounting area also increases. There was also the problem of reduced reliability.

[Means for Solving the Problems] The gist of the present invention is to have a data memory that has a plurality of addresses and stores data at each address, and a data memory that stores data at an address specified by an address signal. A programmable storage device comprising a data input/output circuit that reads or writes data to the outside, and a control circuit that controls reading or writing of the data, which stores address data representing the address and is supplied from the outside. The present invention is characterized by the provision of block memory means for generating the address signal in response to a clock signal, and program writing means for generating the address data and writing the address data into the program memory means.

[Operation of the Invention] First, the program writing means writes address data into the program memory means. A control circuit then sets the data memory to read or write mode. When the clock signal is supplied to the program memory means, an address signal is generated, and data is read from or written to the address specified by the address signal.

[Example] Next, examples of the present invention will be described.

FIG. 1 is a block diagram showing a storage device according to a first embodiment of the present invention. This figure shows only circuit blocks related to the present invention. The program data write circuit 4 inputs a 1-bit write data signal 401 and a 1-bit write clock signal 402 from the outside, and writes a multi-bit data signal 403 and a write pulse signal 4 to the program memory 6.
Outputs 04. As shown in FIG. 5, the program address counter 5 is reset to "'0" by an external counter reset signal 503 (time t
501), when the counter activation signal 501 stands by at a high level, the counter increases by +1 in accordance with the rising timing of the counter clock signal 502, and the counter value is outputted to the program memory 6 as the sequence signal 504 of the program memory (at time t 502.
t503°t504). The program memory 6 executes writing using the write data signal 403 as input data, the write pulse signal 404 as the write timing, and the sequence signal 504 from the program address counter 5 as an address. When writing of the program data to the block memory 6 is completed, the write clock signal 402 and the U counter clock signal 502 are stopped externally.

The program memory 6 enters the read state when the write clock signal 402 stops. As shown in FIG. 6, the read data signal 601 from the program memory 6 is the program data at the address indicated by the sequence signal 504. The data memory address generation calculation circuit 7 inputs the read data signal 601 to the data memory 1
This is an arithmetic circuit for generating an address that points to . The program memory 6 is programmed by the program address counter 5 at times t601 and t61 according to the counter clock signal 502.
1. t621. Using the sequence signal 504 incremented by +1 at t631 as an address, block data is read out and sequentially output to the arithmetic circuit 7 as a data signal 601 (times t602.t612, t622.t632). Data memory 1 is stored at time t603 according to the program data.
．． t613, t623. It operates using the data memory address signal 101 generated by the arithmetic circuit 7 at t633 as an address. The control circuit 3 inputs a control signal 301 and controls read and write operations of the data memory 1 using a control signal 302.
controlled by. The data output circuit 2 outputs the input/output data signal 201 from the data memory 1 to the outside at time t604.
t614. Output at t624 and t634.

Next, a program memory write operation will be explained using a specific example. A (1111), B (0101), and C (0
010), D (1101), first, write the write data signal 401 at the rising edge of the write clock signal 402 in the same month (1, 1, 1,
1,0,1,0,1゜0, 0. 1. 0. 1.
1. 0. Set 1).

The above data inputted to the program data writing circuit 4 generates a 4-bit width write data signal 403 by A(1111) every 4 clocks of the write clock signal 402.
L B (0101), C (001o), D (110
It should be output in the order of 1) at time t501, t502. t50
3. t504) A write pulse signal 404 is also output in synchronization with the data switching of the write data signal 403.

On the other hand, the program address counter 5 is reset by the pulse of the counter reset signal 503, and the counter clock signal 50 is reset while the counter start signal 501 is at a high level.
It is counted up according to the rise of 2. By raising the counter clock signal 502 in response to the switching of the write data signal 403, the sequence signal 504 counts up by +1 from 0 to 3, and sequentially writes the write data signal 403 from address 0 to address 3 of the program memory 6. Write.

The read operation of the data memory 1 by the program memory 6 will be explained using a specific example. Write clock signal 4
If a pulse is not output at 02, write pulse signal 40
4 also remains at a low level and no pulse is generated. In this state, the block memory 6 performs a read operation. The read address of the program memory 6 is generated by sequentially incrementing the sequence signal 504 by 1 starting from address 0 in the same procedure as the write operation (time t601.t611.t621°t6
31). The read data signal 601 from the program memory 6 is A (1111
), B (0101), C (0010), D
(1101) (time t, 602°t612
．． t622. t+632) and the data memory address signal 101 by the arithmetic circuit 7, respectively (5) and (
7), (0), (1) (time t6
03. t613. t623. t633). This conversion depends on the conversion rules between the program and the arithmetic circuit 7. Data memory 1 has addresses (5), (7), (0)
, (1), when the control signal 301 is at a low level, a read operation is performed, and when it is at a high level, a write operation is performed. In the example of FIG. 6, the write operation is at address (7), and the read operation is at addresses (5), (0), and (1). At that time, the input/output data signal 201 corresponds to the respective read data D5 from the data memory 1 at addresses (5), (0), and (1). D.O.

becomes Dl (time t604.t614.t624°t6
34). When the address is 7, it is a write operation, so the data is external data X7. In the first embodiment, a program address counter 5, a program 6, and a data memory address generation calculation circuit 7 constitute a program memory means.

FIG. 4 shows a second embodiment of the invention. The difference from the first embodiment is that the address calculation circuit 7 is not provided. Therefore, the data 602 in the program memory 6 itself becomes the address in the data memory 1. Although the data width of the program memory 6 tends to become wider, the data program written to the program memory 6 is simpler and easier to create, and since the arithmetic circuit 7 is also eliminated, the complicated logic circuit is reduced and the circuit becomes simpler.

In the second embodiment, the program address counter 5 and blockram memory 6 constitute blockram memory means.

[Effects of the Invention] As explained above, the present invention eliminates the address input circuit included in the conventional memory device, eliminates the address input circuit from the outside, and uses an address generation program instead of manually inputting the address signal from the outside. By providing a program memory for storing program data, a circuit for writing program data into the program memory, and a sequence control circuit for the program memory, the following effects can be achieved.

First, the time for the address signal to propagate through the external circuit and the delay time of the address input circuit are no longer necessary, and as shown in FIG. 7, the access time in the data memory read operation can be shortened.

Next, even if the number of words increases due to an increase in storage capacity, address signals and program memory control signals will hardly increase as shown in Table 1. It is possible to prevent an increase in area and a decrease in reliability.

Table 1

[Brief explanation of drawings]

Fig. 1 is a block diagram showing a first embodiment of the present invention, Fig. 2 is a block diagram of a conventional example, Fig. 3 is a block diagram showing application of the conventional example, and Fig. 4 is a block diagram of a second embodiment. , FIG. 5 is a timing chart showing the program memory write operation of the first embodiment, FIG. 6 is a timing chart showing the data memory read operation of the first embodiment, and FIG. 7 is a timing chart showing the time saving effect in the read operation of the present invention. This is a graph showing. 1...Data memory, 2...Data input/output circuit, 3...Control circuit, 4...Program data writing circuit, 5...
...Program address counter, 6...Program memory, 7...Data memory address generation calculation circuit, 8.
... Address input circuit, 9 ... Tag memory, 10 ... Address comparison circuit, 11 ... Tag memory control circuit, 101 ... Data memory address signal, 201 ...
Input/output data signal, 301 ・ ・ 401 ・ ・ 402 ・ ・ 403 ・ ・ 404 ・ ψ 501 ・ ・ 502 φ ・ 503 ・ ・ 504 ・ ・ 803 ・ ・ 804 ・ ・ 1001 φ ・Control signal, ・Write data signal, ・Write clock signal, ・Write data signal, ・Write pulse signal, ・Counter start signal, ・Counter clock signal, ・Counter reset signal, ・Sequence signal, ・Successive data signal, ・Lower address signal, ・Upper address signal, ・Read Data signal, - Match signal.

Claims (1)

[Claims] A data memory that has a plurality of addresses and stores data in each address, and reads or writes data stored in an address of the data memory specified by an address signal to the outside. A programmable storage device comprising a data input/output circuit and a control circuit that controls reading or writing of the data, which stores address data representing the address and outputs the address signal in response to a clock signal supplied from the outside. A programmable storage device comprising: program memory means for generating the address data; and program writing means for generating the address data and writing the address data into the program memory means.