JPH04108219A - Logic circuit - Google Patents

Abstract

PURPOSE:To obtain an SPL(Surer Push-pull Logic) circuit suitable for long distance signal transmission by providing a resistor means in parallel with a pull-down transistor(TR), forming selectively a relevant connection wire and activating the resistive means selectively. CONSTITUTION:An SPL circuit G1 includes a resistor R4 provided in parallel with a pull-down TR T4. The resistor R4 is designed to have a proper resistance causing sufficiently the impedance of the SPL circuit G1 at the transmission end low and not increasing its operating current aimlessly. Moreover, a connection wire provided between its end and the power supply voltage of the circuit, that is, a connection node n1 is formed selectively by changing a photo mask to form, e.g. a metallic wire layer partially thereby validating the resistor R4 selectively. Thus, the SPL circuit suitable for long distance signal transmission is realized.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to logic circuits, for example, SPs installed in high-speed logic integrated circuit devices constituting high-speed computers.
L (Super Pu5h-pull Log
ic) relates to a particularly effective technique for use in circuits.

[Conventional technology]

An NTL (Non Threshold Logic
c) There is a circuit. Also, the output emitter of the NTL circuit.

There is a so-called SPL circuit in which the pull-down circuit is replaced with an active pull-down circuit.

The SPL circuit, as illustrated in the SPL circuit Gl of FIG. 6, includes a pull-down transistor T4 provided between the emitter of the output transistor T3, that is, the output terminal of the circuit, and the power supply voltage of the circuit.

Further, a capacitor CI is provided between the non-inverting output node of the phase dividing circuit, that is, the emitter of the input transistor TI, and the base of the pull-down transistor T4, and a resistor is provided between the base of the pull-down transistor T4 and the power supply voltage of the circuit. It includes a differentiation circuit consisting of 3.

The input signal Sl is changed from low level to high level and S
When the output signal SO of the PL circuit is changed from the /'% high level to the low level, the differential signal of the non-inverted output signal of the phase division circuit, which is changed to the high level, is transmitted to the base of the pull-down transistor T4. Therefore, the pull-down transistor T4 is temporarily turned on, rapidly discharging the load capacitance coupled to the output terminal of the circuit. As a result, while reducing power consumption, S
The operation of the PL circuit is sped up.

Regarding SPL circuits, for example, Japanese Patent Application Laid-Open No. 1-26102
It is described in Publication No. 4, etc.

[Problem to be solved by the invention]

However, as the scale of high-speed logic integrated circuit devices, etc. becomes larger and the chip size thereof becomes larger, the following problems arise in the conventional SPL circuit as described above.
This was revealed by the inventors of the present application. In other words, as the chip size of high-speed, integrated circuit devices, etc. increases,
The signal line length to the subsequent SPL circuit becomes long, and as illustrated in FIG. 6, the wiring resistance Rs and wiring capacitance Cs, that is, the load capacitance, connected to the output terminal of the SPL circuit G1 on the transmitting side becomes large. Become. Therefore, it is necessary to sufficiently discharge these load capacitances while the pull-down transistor T4 of the SPL circuit Gl is temporarily turned on, and the receiving end of the signal line, for example, the SPL circuit G2
The waveform of the output signal SOr at the input terminal of is distorted as shown by the dotted line in FIG. As a result, the signal transmission delay time of high-speed logic integrated circuit devices and the like becomes correspondingly long, and the scale-up of the devices is restricted.

It is an object of this invention to provide an SPL circuit for long distance signal transmission.

Another object of the present invention is to reduce the signal transmission delay time of a high-speed logic integrated circuit device, etc. including an SPL circuit, and to promote the enlargement of the device.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the attached drawings.

[Means to solve the problem]

A brief overview of the most representative inventions disclosed in this application is as follows.

That is, the first resistor means is provided in parallel with the first pull-down transistor constituting the SPL circuit, and the corresponding connection wiring is selectively formed to selectively enable this, and the first resistor means is selectively enabled. Means of resistance or! A second resistor, a second pull-down transistor, or a second capacitor that is selectively enabled is provided in parallel with the first pull-down transistor or the first capacitor constituting the differential circuit.

[For production]

According to the above-described means, the output impedance of the SPL circuit on the transmitting side is reduced and the pull-down ability of the pull-down transistor is increased, or the pull-down transistor is turned on, depending on the signal line length to the next-stage SPL circuit. This allows you to increase the amount of time you spend. As a result, SP
By sufficiently discharging the load capacitor 1 coupled to the output terminal of the L circuit and suppressing the rounding of the signal waveform at the receiving end, the so-called long path! ! It is possible to realize an SPL circuit that passes M signal transmission. As a result, the signal transmission delay time of a high-speed logic integrated circuit device including an SPL circuit can be reduced and the scale of the device can be increased.

[Embodiment 1] FIG. 1 shows a circuit diagram of a first embodiment of an SPL circuit to which the present invention is applied. Further, FIG. 2 shows a signal waveform diagram of a practical example of the SPL circuit of FIG. 1. Based on these figures, an overview of the configuration and operation of the SPL circuit of this embodiment as well as its characteristics will be explained.

Note that the SPL circuit shown in the following embodiments is installed in a high-speed logic integrated circuit device constituting a high-speed computer together with many other SPL circuits, although this is not particularly limited. Although not particularly limited, each circuit element constituting the SPL circuit is formed on a single semiconductor substrate such as single-crystal silicon together with other circuit elements mounted on a high-speed logic integrated circuit device. In the following circuit diagrams, the illustrated transistors (in this specification, bipolar transistors are simply referred to as transistors) are all NPN transistors, although they are not particularly limited.

In FIG. 1, the SPL circuit Gl of this embodiment includes, although not particularly limited to, an input transistor TI that receives an input signal Sl. The collector of this input transistor Tl is connected to the circuit ground potential (first power supply voltage)
, and its emitter is coupled to the circuit power supply voltage (second power supply voltage) via a resistor R2. As a result, the input transistor T1 and the resistors R1 and R2
constitutes a phase division circuit of the SPL circuit. Here, the power supply voltage of the circuit is not particularly limited to wi, but for example, -2,
The input signal Sl is a negative rl voltage such as OV, and the input signal Sl is a digital signal with a relatively small amplitude, for example, 0.6V.

The SPL circuit G1 further includes an output transistor T3 provided between the ground potential of the circuit and the output terminal of the circuit, and a pull-down transistor T4 (first pull-down transistor T4 provided between the output terminal of the circuit and the power supply voltage of the circuit). The base of the output transistor T3 is coupled to the inverting output node of the phase division circuit, that is, the collector of the input transistor Tl, and the base of the pull-down transistor T4 is connected to the capacitor C1 (first capacitor). to the non-inverting output node of the phase divider circuit, ie the emitter of the input transistor TI.

A resistor R3, which together with the capacitor CI constitutes a differential circuit, is provided between the base of the output transistor T4 and the power supply voltage of the circuit. As a result, the output transistor T3 and the pull-down transistor T4 form a so-called push-pull output circuit, and the pull-down transistor T
4, a capacitor C1, and a resistor R3.
Acts as an active pull-down circuit for output transistor T3.

A bias transistor T2 is provided between the ground potential of the circuit and the base of the pull-down transistor T4. Although not particularly limited, the base of the transistor T2 is supplied with a predetermined bias voltage higher than the power supply voltage of the circuit by twice the base-emitter voltage of the NPN transistor, that is, 2V8E, from a voltage generation circuit (not shown) of the high-speed logic integrated circuit device. VB is supplied. Thereby, the transistor T2 forms a bias circuit for the pull-down transistor T4 together with the resistor R3 forming the differential circuit. At this time, a bias voltage higher than the circuit power supply voltage by its base-emitter voltage VIE is applied to the transistor T4. As a result, transistor T4 is biased to a state immediately before being turned on.

In this embodiment, the SPL circuit Gl includes a resistor R4 (
This resistor 4 has a sufficiently low impedance at the transmitting end of the SPL circuit;
Moreover, it is designed to have a predetermined resistance value that does not increase the operating current unnecessarily. Further, the connection wiring provided between one end thereof and the power supply voltage of the circuit, that is, the connection node n1, is selectively formed, for example, by partially changing a photomask for forming a metal wiring layer,
This selectively enables resistor R4. In FIG. 1, the receiving side SPL circuit G2 is connected to the transmitting side SPL circuit G2.
It is arranged with a relatively long cline distance from circuit G1, and the SPL
A relatively large wiring resistance Rs and wiring capacitance Cs parasitic to the signal line are coupled to the output terminal of the circuit G1 in a distributed manner. To deal with this, the SPL circuit G of this embodiment
1, the connection node n1 is formed and the resistor R4 is enabled.

When the input signal S1 is set to low level, the SPL circuit G
In the phase dividing circuit No. 1, its inverted output signal becomes a high level, and the non-inverted output signal becomes a low rail.The high level of the inverted output signal of the six phase dividing circuit is transmitted as it is to the output transistor T3. , a falling change in the non-inverted output signal is transmitted to the base of the pull-down transistor T4 via a differentiating circuit consisting of a capacitor CI and a resistor R3. Therefore, the pull-down transistor T
4 rapidly turns off, and the output transistor T3 turns on. Therefore, the output signal SO of the SPL circuit
As shown by the solid line in FIG.
Both are set to a predetermined high level.

On the other hand, when the input signal Sl is set to high level, the inverted output signal of the phase division circuit becomes a predetermined low level, and the non-inverted output signal becomes a predetermined high level.The low level of the inverted output signal of the 0 phase division circuit is , is similarly transmitted as is to the base of the output transistor T3, and a rising change in the non-inverted output signal is transmitted to the base of the pull-down transistor T4 via the differentiating circuit. For this reason,
The output transistor T3 is turned off, and the pull-down transistor T4 is temporarily turned on for a period corresponding to the driving ability of the differential circuit, that is, the capacitance of the capacitor CI. As a result, the accumulated charge in the wiring layer 1jcs coupled to the output terminal of the SPL circuit ci is discharged, and the output signal SO of the SPL circuit Ct is set to a low level close to the power supply voltage of the circuit.

By the way, in the SPL circuit G1 of this embodiment, as described above, the resistor R4 is provided between the output terminal of the circuit and the power supply voltage, and the output impedance of the SPL circuit G1 is reduced. This speeds up the operation of discharging the charges accumulated in the wiring capacitor Cs, and the charges accumulated in the interconnect capacitor Cs are sufficiently discharged even if the period during which the pull-down transistor T4 is in the on state is insufficient. Therefore, the rise of the output signal SOr at the receiving end is accelerated as shown by the solid line in FIG. 2, and the rounding of the waveform is suppressed. As a result, the signal transmission delay time of the high-speed logic integrated circuit device is reduced, and accordingly, the chip size, that is, the scale thereof, is promoted.

Note that when the connection node n1 is not formed and the resistor R4 is not enabled, the SPL circuit Gl of this embodiment functions in the same manner as the conventional SPL circuit.

[Embodiment 2] FIG. 3 shows a circuit diagram of a second embodiment of the SPL circuit to which the present invention is applied. Incidentally, since the SPL circuit of the following embodiment basically follows the embodiment of $1 above, explanation will be added only for the parts that are different from this.

In FIG. 3, the SPL circuit of this embodiment has a resistor R5 provided in parallel with a resistor R4, although it is not particularly limited.
(second resistance means). In this embodiment, the connection wiring provided between one end of the resistor R5 and the power supply voltage of the circuit, ie, the connection node F n 2, is a part of a photomask for forming a metal wiring layer, although it is not particularly limited. The resistor R5 is selectively formed by changing the resistor R5 to be selectively self-supporting.

Although not particularly limited, the resistor R5 is self-effective when the wiring length to the subsequent SPL circuit is longer. At this time, the resistor R5 acts together with the resistor R4 to further reduce the output impedance of the SPL circuit, thereby making the discharge operation of the wiring layer fC3 coupled to the output terminal of the SPL circuit more reliable. As a result, the signal transmission delay time of the high-speed logic integrated circuit device Wi* equipped with the SPL circuit is further reduced, and its scale is promoted.

[Embodiment 3] FIG. 4 shows a circuit diagram of a third embodiment of the SPL circuit to which the present invention is applied.

In FIG. 4, although the SPL circuit is not particularly limited,
It includes another pull-down transistor T5 (second pull-down transistor) provided in parallel with the pull-down transistor T4.

In this embodiment, the pull-down transistor T5
The connection wiring provided between the emitter and the power supply voltage of the circuit, that is, the connection node n3, is not particularly limited, but can be selectively formed by changing a part of the photomask for forming the metal wiring layer, This selectively enables pull-down transistor T5.

Although the pull-down transistor T5 is not particularly limited,
This is effective when the wiring length to the subsequent SPL circuit is longer. At this time, the pull-down transistor T5 is
It is selectively turned on under the same conditions as the pull-down transistor T4. As a result, the pull-down ability of the pull-down transistor as a whole is increased, and the discharge operation of the wiring capacitor C3 coupled to the output terminal is performed more reliably. As a result, the signal transmission delay time of high-speed logic integrated circuit devices and the like equipped with 5PLu circuits is further reduced, and their scale-up is promoted.

[Embodiment 4] FIG. 5 shows a circuit diagram of a fourth embodiment of an SPL circuit to which the present invention is applied.

In FIG. 5, the SPL circuit of this embodiment includes, although not particularly limited to, another capacitor C2 (second capacitor) provided in parallel with the capacitor C1 of the differential circuit. The connection wiring provided between one electrode of C2 and the emitter of the input transistor Tl, that is, the connection node n4, is selectively formed by partially changing the photomask for forming the metal wiring layer. capacitor C2 by
is selectively valid.

Although not particularly limited, the capacitor C2 can be
This method is effective when the wiring length to the circuit is longer. At this time, capacitor C2 is connected to capacitor C1 and resistor R.
3 and 0 constitute a differentiating circuit. As is well known, the driving ability of the differentiating circuit from the perspective of the pull-down transistor T4 is:
It increases in proportion to the capacitance value of the capacitor that constitutes the differential circuit. As described above, by providing the capacitors CI and C2 in parallel, the driving ability of the differentiating circuit is increased, and the period during which the pull-down transistor T4 is in the on state is lengthened. Therefore, the pull-down ability of the pull-down transistor T4 is correspondingly increased, and the discharge operation of the wiring capacitance Cs coupled to its output terminal is reliably performed. As a result, the signal transmission delay time of high-speed logic integrated circuit devices and the like equipped with SPL circuits is further reduced, and their scale is promoted.

As shown in the plurality of embodiments described above, the following effects can be obtained by applying the present invention to an SPL circuit installed in a high-speed logic integrated circuit device constituting a high-speed computer. That is, by providing the first resistor means in parallel with the first pull-down transistor constituting the 11S P L circuit, and selectively forming the corresponding connection wiring to selectively enable it, When the wiring length to the next stage SPL circuit is relatively long, the output impedance of the SPL circuit on the transmitting side can be selectively reduced, and the accumulated charge in the wiring capacitance coupled to the signal line can be sufficiently discharged. It will be done.

(2) In the above item i11, the output impedance of the SPL circuit is further reduced according to the wiring length by providing a second resistance means that is selectively effective in parallel with the first resistance means. This provides the effect that the wiring capacitance coupled to the output terminal can be more reliably discharged.

(3) In the above item (11), by providing a second pull-down transistor that is selectively enabled in parallel with the first pull-down transistor, the pull-down ability of the pull-down transistor as a whole can be adjusted according to the wiring length. This has the effect of selectively increasing the wiring capacitance coupled to the output terminal, thereby roughly and reliably discharging the wiring capacitance coupled to the output terminal.

(In item (1) above, by providing a second capacitor that is selectively effective in parallel with the first capacitor constituting the differentiating circuit, the drive usage of the differentiating circuit can be adjusted according to the wiring length.) By selectively increasing the pull-down transistor and lengthening the period during which the pull-down transistor is in the on state, an effect can be obtained in which the wiring capacitance coupled to the output terminal of the SPL circuit can be more reliably discharged.

(5) Items (1) to (4) above have the effect of suppressing the rounding of the signal waveform at the receiving end of the signal line and speeding up the falling change.

C (51 above) Items to (5) reduce the signal transmission delay time of high-speed logic integrated circuit devices etc. equipped with SPL circuits, and correspondingly increase the chip size, that is, SPI,
This has the effect of increasing the scale of the circuit.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. For example, in the embodiments shown in FIG. 1 and FIGS. 3 to 5, the 5PLIT path can be configured to have any number of inputs or logic functions by changing the number and connection form of the input transistors that make up the phase division circuit. can have. Further, the SPL circuit can include a bias circuit for applying bias pressure VB to the bias transistor T2, and furthermore, the SPL circuit can include a bias circuit for applying bias pressure VB to the bias transistor T2, and furthermore, the
A clamp circuit can also be provided to limit the level of. Resistors R1 and R2 forming the phase division circuit are:
The connection nodes 111-n4 may be placed in active pull-up or pull-down MO3FETs.
The invention shown in FIG. 1 and FIGS. 3 to 5 may be provided on the opposite side of each circuit element, or the wiring may be fixed by eliminating these connection nodes. It can be applied. Furthermore, SP
The specific circuit configuration of the L circuit, the combination of power supply voltages, the conductivity type of the transistors, etc. may be varied in various embodiments.
).

In the above explanation, we have mainly explained the case where the invention made by the present inventor is applied to an SPL circuit installed in a high-speed logic integrated circuit device, etc., which is the field of application that forms the background of the invention, but the present invention is not limited to this. Rather than, for example,
It can also be applied to similar SPL circuits installed in gate array integrated circuits and various dedicated logic integrated circuit devices. The present invention is widely applicable to logic circuits including at least a pull-down transistor and a differentiating circuit for temporarily turning on the pull-down transistors, or dinotal integrated circuit devices including such logic circuits.

〔Effect of the invention〕

A brief explanation of the effects obtained by representative inventions among the inventions disclosed herein is as follows. That is, the first resistor means is provided in parallel with the first pull-down transistor constituting the SPL circuit, and the corresponding connection wiring is selectively formed to make it selectively effective. A second resistor, a second pull-down transistor, or a second capacitor which is selectively made into a quadruple effect is placed in parallel with the resistor means, the first pull-down transistor, or the first capacitor constituting the differential circuit. By providing this, the output impedance of the SPL circuit is reduced depending on the length of the signal line up to the next stage logic circuit, and the pull-down ability of the pull-down transistor is increased, or the time during which the pull-down transistor is in the on state and in a stable state is increased. Be able to do that. This allows ~SPL
By sufficiently discharging the load capacitance coupled to the output terminal of the circuit and suppressing the distortion of the No. 4 waveform at the receiving end, it is possible to realize an SPL circuit that allows so-called long-distance signal transmission. As a result, signal transmission of high-speed logic integrated circuit devices including SPL circuits is possible! It is possible to reduce the delay time and promote the large-scale production of barrels.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a first embodiment of an SPL circuit to which the present invention is applied. J is a signal waveform diagram showing one embodiment of the SPLM circuit in Fig. 1, @3 is a circuit diagram showing a second embodiment of the SPL circuit to which this invention is applied, and Fig. 4 is a signal waveform diagram showing an embodiment of the SPLM circuit in Fig. 1. The third part of the SPL circuit where
FIG. 5 is a circuit diagram showing a fourth embodiment of the SPL circuit to which the present invention is applied. FIG. 186 is a circuit diagram showing an example of a conventional SPL circuit. G1-G2...SPL circuit, Tl-75...NPN
type bipolar transistor, Cl-C2...capacitor, R1-R5...resistance, nl-n4...connection node, Cs...wiring capacitance, Rs...wiring resistance.

Claims (1)

[Claims] 1. A phase division circuit that receives an input signal; an output transistor that is provided between a first power supply voltage and an output terminal of the circuit and receives an inverted output signal of the phase division circuit at its base; a first pull-down transistor provided between the output terminal of the circuit and a second power supply voltage; and a first capacitor provided between the non-inverting output node of the phase division circuit and the base of the first pull-down transistor. A logic circuit comprising: a differential circuit including a differential circuit; and a first resistor provided in parallel with the first pull-down transistor. 2. The first resistance means is selectively enabled by selectively forming a connection wiring between one end thereof and the output terminal of the circuit or the second power supply voltage. The logic circuit according to claim 1, characterized in that: 3. The logic circuit according to claim 2, wherein the logic circuit includes a second resistance means that is provided in parallel with the first resistance means and is selectively activated. . 4. Claim 1 or 2, wherein the logic circuit includes a second pull-down transistor that is provided in parallel with the first pull-down transistor and is selectively enabled. The logic circuit described. 5. The logic circuit according to claim 1 or 2, wherein the logic circuit includes a second capacitor that is provided in parallel with the first capacitor and is selectively enabled. logic circuit.