JP3243202B2 - Pulse transmission circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a pulse transmission circuit for transmitting a high-speed pulse signal with low jitter.

[0002]

2. Description of the Related Art In recent years, high-speed data processing of 100 MHz or more has been performed in the fields of electronic computers, data communication, and optical disks. As a conventional pulse transmission circuit, one disclosed in Japanese Patent Application Laid-Open No. 4-71016 is known. Hereinafter, the pulse transmission circuit disclosed in JP-A-4-71016 will be described with reference to FIG. FIG. 9 is a block diagram of a conventional pulse transmission circuit disclosed in the above publication, and the conventional pulse transmission circuit is configured as follows. P-MOS transistor 104
Indicates that an external input is input to the gate and the source is VD
D power supply. N-MOS transistor 10
Reference numeral 5 indicates that an external input is input to the gate, the drain is grounded, and the source is connected to the drain of the P-MOS transistor 104. P-MOS transistor 10
4 and the N-MOS transistor 105 constitute an invert buffer 101. The inverter 108 is a P-MO
It is connected to the drain of S transistor 104. N
The output of the inverter 108 and an external input are input to the OR gate 109. The output of the inverter 108 and an external input are input to the NAND gate 110. Inverter 111, the output of NOR gate 109 is input. Inverter 112, NAND gate 11
An output of 0 is input. P-MOS transistor 106
The output of the inverter 111 is input to a gate, a source connected to the VDD power supply. N-MOS transistor 107, the output of inverter 112 is input to the gate, the drain is grounded, and a source connected to the drain of the P-MOS transistor 106. Inverter 108, NOR gate 109, NAND gate 110
Is inverter 111, inverter 112, P-MOS
Transistor 106 and N-MOS transistor 10
7 configures the control unit 102. Load capacity 10
3 has one end connected to the drain of the P-MOS transistor 104 and the other end grounded.

The input to the invert buffer 101 (P-
When the input to the gates of the MOS transistor 104 and the N-MOS transistor 105 is at the GND level, the load capacitance 103 is charged to the VDD level. Load capacity 1
03 is charged to the VDD level and the input to the invert buffer 101 is set to the VDD level, then N-M
The OS transistor 105 is turned on. The charge charged in the load capacitor 103 is discharged via the N-MOS transistor 105. When the difference between the voltages input to the NOR gate 109 and the NAND gate 110 reaches the threshold voltages of the NOR gate 109 and the NAND gate 110, respectively, the N-MOS transistor 107 is turned on.
The charge charged in the load capacitance 103 is discharged via the N-MOS transistor 105 and the N-MOS transistor 107. As described above, the charges charged in the load capacitance 103 are dispersed and discharged. Therefore, with the circuit configuration shown in FIG. 9, overshoot can be suppressed.

[0004]

However, in the conventional pulse transmission circuit, the drive current of the transistor oscillates due to the parasitic capacitance of the transmission line. Therefore, the pulse edge of the output pulse signal fluctuates, causing a phase shift. SUMMARY OF THE INVENTION It is an object of the present invention to provide a pulse transmission circuit that has a parasitic capacitance in a transmission line and can suppress a phase shift between two pulse signals even when transmitting two high-speed pulse signals exceeding 100 MHz. I do.

[0005]

A pulse transmission circuit according to the present invention outputs a first digital signal from a first output and a second digital signal.
A digital data generation circuit that outputs a second digital signal synchronized with the first digital signal from the output of the first digital signal; a first emitter follower circuit that receives the first digital signal output by the digital data generation circuit; An emitter follower circuit pair having the second digital signal output from the digital data generation circuit and having a second emitter follower circuit having the same configuration as the first emitter follower circuit; an output of the first emitter follower circuit; A first transmission line, one end of which is connected to the first transmission line, a second transmission line, one end of which is connected to the output of the second emitter follower circuit, and a signal transmitted by the first transmission line and the second transmission line. And a phase comparator for comparing the phases of the digital signals.
As described above, if a pulse transmission circuit including an emitter follower circuit pair in which two emitter follower circuits are paired is configured, the first transmission path and the second transmission path have a parasitic capacitance, and a high-speed operation exceeding 100 MHz. Even when transmitting two pulse signals, the phase shift can be suppressed.

A pulse transmission circuit according to another aspect of the present invention outputs a first digital signal from a first output, and outputs a second digital signal from a first output.
Outputs a second digital signal synchronized with the first digital signal and having the same clock cycle with the opposite polarity and the third digital signal synchronized with the first digital signal from the third output. Then, the fourth output is synchronized with the third digital signal, the polarity is reversed, and the clock cycle is the same as the fourth digital signal.
Digital data generation circuit for outputting a digital signal of the following, a first emitter follower circuit to which the first digital signal output by the digital data generation circuit is input, and the second digital signal output by the digital data generation circuit And a second emitter follower circuit having a second emitter follower circuit having the same configuration as the first emitter follower circuit, a first transmission line having one end connected to an output of the first emitter follower circuit. A second transmission path having one end connected to the output of the second emitter follower circuit, one end connected to the other end of the first transmission path and the other end of the second transmission path, A first comparator for comparing the digital signal transmitted by the second transmission path with the digital signal transmitted by the second transmission path, and receiving the third digital signal output by the digital data generation circuit. A third emitter follower circuit having the same configuration as the first emitter follower circuit and the fourth digital signal output from the digital data generation circuit are input to the fourth emitter follower circuit having the same configuration as the first emitter follower circuit. A second emitter-follower circuit pair having an emitter-follower circuit, a third transmission line having one end connected to the output of the third emitter-follower circuit, and one end connected to the output of the fourth emitter-follower circuit. A fourth transmission line, a digital signal transmitted through the first transmission line and the second transmission line, one end of which is connected to the other end of the third transmission line and the other end of the fourth transmission line. second comparator for comparing, and comprises a phase comparator, for comparing the phase of the digital signal inputted from said second comparator and said first comparator. As described above, if a pulse transmission circuit having two emitter follower circuit pairs, in which two emitter follower circuits are paired, is configured, each transmission path has a parasitic capacitance, and
Even when transmitting two high-speed pulse signals exceeding 0 MHz, the phase shift can be effectively suppressed.

In the above-described pulse transmission circuit, the first
The fourth to fourth emitter follower circuits include a transistor to which a digital signal input to each of the first to fourth emitter follower circuits is input to a base, a resistor having one end connected to an emitter of the transistor, and And a current bias circuit that is connected to the other end of the device and flows a current through the resistor. By incorporating a resistor between the transistor and the current bias circuit, the phase margin of each of the first to fourth emitter follower circuits can be increased.

BEST MODE FOR CARRYING OUT THE INVENTION

An embodiment of the present invention will be described below with reference to FIGS. Embodiment 1 FIG. 1 is a block diagram of a pulse transmission circuit according to Embodiment 1 of the present invention. The digital data generation circuit 1 generates a first digital signal a and a second digital signal b, outputs a first digital signal a from a first output, and outputs a second digital signal b from a second output. Is output. The first digital signal a is a reference signal and is a clock signal with a time period. The second digital signal b is the first digital signal b.
Is a serial data signal which is synchronized with the digital signal and represents data by the length of time from edge to edge. The first transistor 11 has a collector connected to the VCC power supply and a base connected to a first output of the digital data generation circuit 1. The first transistor 11 is an npn transistor. One end of the first resistor 12 is connected to the emitter of the transistor 11. The first current bias circuit 13 is connected to the other end of the first resistor 12,
For example, it is composed of a current mirror circuit. The first transistor 11, the first resistor 12, and the first current bias circuit 13 constitute a first emitter follower circuit 2. The first resistor 12 has a function of increasing a phase margin in the open-loop characteristic of the first emitter follower circuit 2.
One end of the first transmission path 3 is connected to a connection point between the first resistor 12 and the first current bias circuit 13, and transmits a digital signal.

The collector of the second transistor 14 is V
The base is connected to the second output of the digital data generation circuit 1. The second transistor 15 is an npn transistor. One end of the second resistor 15 is connected to the emitter of the second transistor 14. The second current bias circuit 16 is connected to the other end of the second resistor 15, and is constituted by, for example, a current mirror circuit. The second transistor 14, the second resistor 15, and the second
Constitutes the second emitter follower circuit 4. The second resistor 15 has an effect of increasing the phase margin in the open-loop characteristic of the second emitter follower circuit 4. Note that the second emitter follower circuit 4
Has the same configuration as the first emitter follower circuit 2. One end of the second transmission path 5 is connected to a connection point between the second resistor 15 and the second current bias circuit 16, and transmits a digital signal. The phase comparator 6 is connected to the other end of the first transmission line 3 and the other end of the second transmission line 5. Phase comparator 6
Compares the phase of the third digital signal A transmitted from the first transmission path 3 with the phase of the fourth digital signal B transmitted from the second transmission path 4, and compares the phase of the fourth digital signal B Determine the sign.

Next, the operation of the pulse transmission circuit will be described with reference to FIG.
This will be described with reference to FIG. Since the configuration of the first emitter follower circuit 2 and the configuration of the second emitter follower circuit 4 are the same, only the first emitter follower circuit 2 will be described. FIG. 2 shows an equivalent circuit on the first emitter follower circuit 2 side of the pulse transmission circuit of FIG. The digital generation circuit 1 includes a voltage source 20 which represents a first output by an equivalent circuit.
And a resistor 21 representing the output resistance of the digital data generation circuit 1 having one end connected to the voltage source 20. The first transistor 11 includes a resistor 22 representing a base resistor, a resistor 23 having one end connected to the resistor 22 and representing an input resistance, a capacitor 24 connected in parallel with the resistor 23 and representing a base storage capacitance, and a resistor 23. A current source 25 representing an equivalent current source that is connected to one end and that conducts a current in conductance when a voltage is generated across the parallel circuit of the resistor 23 and the capacitor 24;
And one end is connected to the other end of the resistor 23 and is represented by a resistor 26 representing an emitter resistance. Here, the combined impedance of the parallel circuit of the resistor 23 and the capacitor 24 depends on the characteristics of the transistor and the magnitude of the current output from the current source 25. Note that the resistance value of the combined resistance of the resistor 21 and the resistor 22 is
Almost determined by the resistance value of the resistor 21, 50 Ω to 5 k
Ω.

The first resistor 12 is represented by a resistor 27.
The first current bias circuit 13 and the first transmission line 3 are provided with a resistor 2 representing an equivalent resistance of the first current bias circuit 13.
8 and the equivalent capacity of the first current bias circuit 13 and the first
2 representing the combined capacitance of the parasitic capacitances of the transmission path 3 of FIG.
9. Here, when the first current bias circuit 13 is configured by a current mirror circuit using a transistor, the resistance value of the resistor 28 depends on the Early voltage and the current value of the transistor on the output side of the current mirror circuit.
When the first transmission line 3 is composed of a package lead of an integrated circuit and a printed circuit board wiring, the capacitance value of the parasitic capacitance of the first transmission line 3 is usually 0 PF to 30 PF, and the capacitance of the capacitor 29 Value is almost 0PF to 30PF
It is.

The operation of the equivalent circuit when the output voltage of the voltage source 20 fluctuates will be qualitatively described. When the output voltage of the voltage source 20 fluctuates and increases, the resistance 23 and the capacitor 2
4 (hereinafter, referred to as a first voltage) increases. When the first voltage increases, the current output from the current source 25 increases. Resistance 26, resistance 27 and resistance 2
The current flowing in the series circuit composed of the parallel circuit of the resistor 8 and the capacitor 29 increases, and the connection point of the parallel circuit of the resistor 23 and the capacitor 24, the resistor 26, and the current source 25 (hereinafter referred to as the first
The potential at the connection point) increases. Here, the potential of the first connection point is a potential based on the potential of the ground point where the parallel circuit of the resistor 28 and the capacitor 29 is grounded. Hereinafter, the potential of the first connection point is a potential based on the potential of the ground point where the parallel circuit of the resistor 28 and the capacitor 29 is grounded. Since the potential at the first connection point increases, the first voltage decreases. Then, the current output from the current source 25 decreases.

As the output voltage of voltage source 20 fluctuates and decreases, the first voltage decreases. When the first voltage decreases, the current output from the current source 25 decreases. Resistance 26 and resistance 27
The current flowing in the series circuit including the parallel circuit of the resistor 28 and the capacitor 29 decreases, and the potential at the first connection point decreases. The first voltage increases because the potential at the first connection point decreases. Then, the current output from the current source 25 increases. As described above, the first emitter follower circuit 2 is a series-series type feedback system. Similarly, the second emitter follower circuit 4 is also a series-series type feedback system.

Next, using the equivalent circuit described with reference to FIG.
A series composed of the first emitter follower circuit 2
A loop transfer function of a series feedback system will be described. In the equivalent circuit of FIG. 2, the value of the output voltage of the voltage source 20 is defined as Vin. The resistance value of the resistor 21 is r1, the resistance value of the resistor 22 is r2, the resistance value of the resistor 23 is r3, the resistance 2
6, the resistance value of the resistor 27 is defined as r5, and the resistance value of the resistor 28 is defined as r6. The capacitance value of the capacitor 24 is defined as C1, and the capacitance value of the capacitor 29 is defined as C2. The conductance of the transistor is defined as gm.
When defined as described above, the voltages generated at both ends of the parallel circuit of the resistor 23 and the capacitor 24, the current output from the current source 25, and the current output from the current source 25 are used only for the resistors 26, 27, 28, and 29. The voltages generated at both ends of the series circuit composed of the parallel circuit of Equation (1), Equation (2), and Equation (3) have a relationship as shown in Equations (1), (2), and (3). V1 is the voltage generated across the parallel circuit of the resistor 23 and the capacitor 24, I is the current output from the current source 25, and V2 is the current output from the current source 25 only, and the resistors 26, 27 and 27 2 shows a voltage generated at both ends of a series circuit including a parallel circuit of a capacitor 28 and a capacitor 29. V1 = Z2 × (Vin−V2) / (Z1 + Z2 + Z3) (1) I = gm × V1 (2) V2 = Z3 × I (3) where Z1 = r1 + r2 Z2 = r3 / (r3 × C1 × s + 1) Z3 = r4 + r5 + r6 / (r6.times.C2.times.s + 1) where s is a complex variable of the Laplace transform and is represented as follows. s = j × ω j is an imaginary unit, and ω is an angular frequency.

The loop transfer function of the feedback system is represented by G
Assuming H, when the base current is sufficiently smaller than the collector current, GH is expressed as in equation (4). GH = V2 / Vin = gm × Z2 × Z3 / (Z1 + Z2 + Z3) (4)

In the classical control theory, in a feedback system, if the phase margin obtained from the loop transfer function is 30 ° or more, the feedback system is stable, and the phase margin is 120 °.
It is known that if it is less than or equal to °, the time required for settling is short. Then, by stabilizing the feedback system, it is possible to reduce the fluctuation of the group delay characteristic with respect to the frequency of the closed loop characteristic.

FIGS. 3 to 5 show the results of computer simulation of the phase margin of the feedback system. It should be noted that even in the band of 100 MHz or more, the first
Computer simulation is performed when the value of the current flowing through the first current bias circuit 13 is in the range of 1 mA to 10 mA so that the transistor 11 can operate. Note that J in the drawing represents the value of the current flowing through the first current bias circuit. FIG. 3A is a characteristic diagram showing a relationship between a resistance value of a combined resistance of the resistors 26 and 27 and a gain intersection frequency value. FIG. 3B is a characteristic diagram showing the relationship between the resistance value of the combined resistance of the resistors 26 and 27 and the phase margin.
FIG. 3 shows the case where the capacitance value of the capacitor 29 is set to 30 PF, assuming the sum of the maximum value of the parasitic value of the lead of the package of a typical integrated circuit and the printed circuit board. The combined resistance of the resistors 26 and 27 is substantially determined by the resistance of the resistor 26 (the first resistor 12 in FIG. 1), and the capacitance of the capacitor 29 is determined by the parasitic capacitance of the first transmission line 3. Is almost determined by The gain intersection frequency is a frequency at which the gain margin becomes 0 (dB). FIG. 3 (a)
As can be seen from the graph, when the current value increases, the value of the gain intersection frequency increases, and the amount of increase of the gain intersection frequency with respect to a change in the current value is large. Further, it can be seen that the gain intersection frequency increases with an increase in the resistance value of the resistor 26, but the increase is small. FIG. 3B shows that the first emitter follower circuit 2 that is stable and has a short settling time can be configured when the capacitance value of the capacitor 29 is 30 PF.

FIG. 4A is a characteristic diagram showing the relationship between the resistance value of the combined resistance of the resistors 26 and 27 and the gain intersection frequency value. FIG. 4B is a characteristic diagram showing the relationship between the resistance value of the combined resistance of the resistors 26 and 27 and the phase margin. FIG. 4 assumes the sum of the standard value of the parasitic value of the lead of the package of a typical integrated circuit and the printed circuit board,
This is a case where the capacitance value of the capacitor 29 is set to 10 PF. FIG. 4A shows that as the current value increases, the value of the gain intersection frequency increases, and the amount of increase in the gain intersection frequency with respect to the change in the current value is large. FIG. 4B shows that the first emitter follower circuit 2 that is stable and has a short settling time can be configured when the capacitance value of the capacitor 29 is 10 PF.

FIG. 5A is a characteristic diagram showing the relationship between the resistance value of the combined resistance of the resistors 26 and 27 and the gain intersection frequency value. FIG. 5B is a characteristic diagram showing the relationship between the resistance value of the combined resistance of the resistors 26 and 27 and the phase margin. FIG. 5 assumes the sum of the minimum value of the parasitic capacitance of a typical integrated circuit package lead and a printed circuit board.
This is a case where the capacitance value of the capacitor 29 is set to 0PF. FIG. 5A shows that as the current value increases, the value of the gain intersection frequency increases, and the amount of increase of the gain intersection frequency with respect to the change in the current value is large. FIG. 5B shows that the first emitter follower circuit 2 that is stable and has a short settling time can be configured when the capacitance value of the capacitor 29 is 0 PF.

3 to 5, the phase margin is 30 °.
If the first emitter follower circuit 2 is configured to be in the range of about 120 ° to 120 °, the first emitter follower circuit 2
Is a feedback system that is stable and has a short settling time within the range of the capacitance value of the parasitic capacitance of the package lead of the integrated circuit and the printed circuit board. Therefore, the third digital signal A having a small pulse variation can be input to the phase comparator 6.

If the second emitter follower circuit 4 is constructed in the same manner as the first emitter follower circuit 2, the second emitter follower circuit 4 will have the capacitance value of the parasitic capacitance of the lead of the package of the integrated circuit and the printed circuit board. Within this range, the feedback system is stable and has a short settling time. Therefore, the fourth digital signal B having a small pulse fluctuation can be input to the phase comparator 6.

FIG. 6 is a schematic diagram of each digital signal of the pulse transmission circuit of FIG. Note that the phase margin is 30 ° to 1 °.
This is a case where the first emitter follower circuit 2 and the second emitter follower circuit 4 are configured to have a range of 20 °. The digital data generating circuit 1 outputs a first digital signal a and a second digital signal b as shown in FIG. 6 to a first emitter follower circuit 2 and a second emitter follower circuit 4, respectively. The first emitter follower circuit 2 and the second emitter follower circuit 4 output a third digital signal A and a fourth digital signal B as shown in FIG. 6 to the phase comparator 6, respectively. The phase comparator 6 includes a third digital signal A and a fourth digital signal B
Are compared to determine the sign of the fourth digital signal.

The time interval Y (FIG. 6) between the edge of the third digital signal A and the edge of the fourth digital signal B input to the phase comparator 6 even in a band exceeding 100 MHz due to a parasitic capacitance in each transmission path. Is the time interval X between the edge of the first digital signal a and the edge of the second digital signal b (FIG. 6)
Matches. As described above, by configuring the pulse transmission circuit by pairing the first emitter follower circuit 2 and the second emitter follower circuit 4, the third digital signal A
And the phase shift of the fourth digital signal B is suppressed, and the phase comparator 6 can correctly determine the sign of the fourth digital signal B.

Although the first embodiment uses the npn transistor, the same effect can be obtained by using the pnp transistor and the field effect transistor. In the first embodiment, if the first transmission line and the second transmission line have the same shape, the same size, and the same material, the phase shift of the digital signal input to the phase comparator can be effectively suppressed. In addition, if the first transmission line and the second transmission line are arranged at adjacent positions, it is possible to effectively suppress the phase shift of the digital signal input to the phase comparator. In the first embodiment, an emitter-follower circuit pair having two emitter-follower circuits and a phase comparator are each integrated into an IC on a printed circuit board, and the first pair of the emitter-follower circuit pair and the phase comparator are connected to each other. And the second transmission path.

Embodiment 2 FIG. 7 is a block diagram of a pulse transmission circuit according to Embodiment 2 of the present invention. The digital data generation circuit 31 outputs the first digital signal c, the second digital signal c,
, A third digital signal e, and a fourth digital signal f. Digital data generation circuit 3
1 outputs a first digital signal c from a first output;
The second digital signal d is output from the second output, the third digital signal e is output from the third output, and the fourth digital signal f is output from the fourth output. The first digital signal c is a reference signal and is a clock signal with a time period. The second digital signal d is a clock signal synchronized with the first digital signal c, having the opposite polarity and the same clock cycle. The third digital signal e is a serial data signal that is synchronized with the first digital signal and represents data with the length of time from edge to edge. Fourth digital signal f
Is a signal synchronized with the third digital signal e, having the opposite polarity and the same clock cycle.

The first digital data c output from the digital data generating circuit 31 is input to the first emitter follower circuit 32. One end of the first transmission path 33 is connected to the output end of the first emitter follower circuit 32,
Transmit digital signals. The second digital data d output from the digital data generation circuit 31 is input to the second emitter follower circuit 34. The second transmission path 35 is
One end is connected to the output end of the second emitter follower circuit 34, and transmits a digital signal. First comparator 3
6 is the other end of the first transmission line 33 and the second transmission line 35
Is connected to the other end. The first comparator 36 includes a fifth digital signal C transmitted by the first transmission path 33 and a sixth digital signal D transmitted by the second transmission path 35.
And outputs digital data having an amplitude of 1 when the voltage value of the fifth digital signal C is large, and digital data having an amplitude of 0 when the voltage value of the sixth digital signal D is large.

The third emitter follower circuit 37 receives the third digital data e output from the digital data generation circuit 31. The third transmission path 38 has one end connected to the output end of the third emitter follower circuit 37,
Transmit digital signals. The fourth digital data f output from the digital data generation circuit 31 is input to the fourth emitter follower circuit 39. The fourth transmission line 40 is
One end is connected to the output end of the fourth emitter follower circuit 39, and transmits a digital signal. Second comparator 4
1 is the other end of the third transmission line 38 and the fourth transmission line 40
Is connected to the other end. The second comparator 41 includes a seventh digital signal E transmitted through the third transmission line 38 and an eighth digital signal F transmitted through the fourth transmission line 40.
And outputs digital data with an amplitude of 1 when the voltage value of the seventh digital signal E is large, and digital data with an amplitude of 0 when the voltage value of the eighth digital signal F is large.

The phase comparator 42 is a ninth digital signal G input from the first comparator 36 and the second comparator 41.
And the phase of the tenth digital signal H are compared to determine the sign of the tenth digital signal H. Note that the first emitter follower circuit 32, the second emitter follower circuit 34,
The configuration of the third emitter follower circuit 37 and the fourth emitter follower circuit 39 is, for example, the first emitter follower circuit 39 shown in the first embodiment.
Is the same as that of the emitter follower circuit 2.

FIG. 8 is a schematic diagram of each digital signal of the pulse transmission circuit of FIG. Digital data generation circuit 31
Converts the first digital signal c, the second digital signal d, the third digital signal e, and the fourth digital signal f as shown in FIG. 8 into a first emitter follower circuit 32, respectively.
The signals are output to the second emitter follower circuit 34, the third emitter follower circuit 37, and the fourth emitter follower circuit 39. The first emitter follower circuit 32 and the second emitter follower circuit 34 output a fifth digital signal C and a sixth digital signal D as shown in FIG. 8 to the first comparator 36, respectively. The third emitter follower circuit 37 and the fourth emitter follower circuit 39 output a seventh digital signal E and an eighth digital signal F as shown in FIG. 8 to the second comparator 41, respectively. In addition,
In the second embodiment, unlike the first embodiment, the first emitter follower circuit 32 and the second emitter follower circuit 3
4. The short time required for the rise and fall of the output signal output by the third emitter follower circuit 37 and the fourth emitter follower circuit 39 is also taken into account. The first comparator 36 and the second comparator 41 output a ninth digital signal G and a tenth digital signal H as shown in FIG. 8 to the phase comparator, respectively. The phase comparator 42 compares the phases of the ninth digital signal G and the tenth digital signal H, and determines the sign of the tenth digital signal H.

The ninth signal input to the phase comparator 6 even when the transmission path has a parasitic capacitance in a band exceeding 100 MHz and the rise time and the fall time are taken into account in the output of each emitter follower circuit. The time interval Y (FIG. 8) between the edge of the digital signal G and the edge of the tenth digital signal H is the time interval X (FIG. 8) between the edge of the first digital signal c and the edge of the third digital signal e. Matches. Thus, an emitter follower circuit pair including the first emitter follower circuit 32 and the second emitter follower circuit 34 for the reference signal is formed, and the third emitter follower circuit 37 and the fourth emitter follower circuit for the signal are formed. By configuring the emitter follower circuit pair having the 39, the phase shift between the ninth digital signal G and the tenth digital signal H is effectively suppressed, and the phase comparator 6
The sign of the tenth digital signal H can be correctly determined.

In the second embodiment, the first transmission path,
If the second transmission line, the third transmission line, and the fourth transmission line have the same shape, the same size, and the same material, the phase shift of the digital signal input to the phase comparator can be effectively suppressed. . Further, if the first transmission line, the second transmission line, the third transmission line, and the fourth transmission line are arranged at adjacent positions,
The phase shift of the digital signal input to the phase comparator can be effectively suppressed.

[0032]

According to the present invention, even if two high-speed pulse signals exceeding 100 MHz are transmitted due to a parasitic capacitance in the transmission line, the sign of the pulse signal input to the phase comparator is accurately determined. be able to.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a pulse transmission circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram illustrating an operation of the pulse transmission circuit of FIG.

FIG. 3A is a characteristic diagram illustrating a gain intersection frequency of a first emitter follower circuit, and FIG. 3B is a characteristic diagram illustrating a phase margin of the first emitter follower circuit.

FIG. 4A is a characteristic diagram illustrating a gain intersection frequency of a first emitter follower circuit, and FIG. 4B is a characteristic diagram illustrating a phase margin of the first emitter follower circuit.

FIG. 5A is a characteristic diagram illustrating a gain intersection frequency of a first emitter follower circuit, and FIG. 5B is a characteristic diagram illustrating a phase margin of the first emitter follower circuit.

FIG. 6 is a schematic diagram of a digital signal in the pulse transmission circuit of FIG. 1;

FIG. 7 is a block diagram illustrating an example of a pulse transmission circuit according to a second embodiment of the present invention.

8 is a schematic diagram of a digital signal in the pulse transmission circuit of FIG.

FIG. 9 is a block diagram showing a conventional pulse transmission circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Digital data generation circuit 2 1st emitter follower circuit 3 1st transmission line 4 2nd emitter follower circuit 5 2nd transmission line 6 Phase comparator 11 1st transistor 12 1st resistance 13 1st electric current Bias circuit 14 Second transistor 15 Second resistor 16 Second current bias circuit 31 Digital data generation circuit 32 First emitter follower circuit 33 First transmission path 34 Second emitter follower circuit 35 Second transmission path 36 first comparator 37 third emitter follower circuit 38 third transmission path 39 fourth emitter follower circuit 40 fourth transmission path 41 second comparator 42 phase comparator

Claims (6)

(57) [Claims] A digital data generation circuit for outputting a first digital signal from a first output and outputting a second digital signal synchronized with the first digital signal from a second output; A first emitter follower circuit to which the first digital signal output from the circuit is input and a second emitter having the same configuration as the first emitter follower circuit to which the second digital signal output from the digital data generation circuit is input An emitter-follower circuit pair comprising: a first transmission line having one end connected to the output of the first emitter-follower circuit; and a second transmission line having one end connected to the output of the second emitter-follower circuit. And a phase comparator for comparing the phases of digital signals transmitted by the first transmission line and the second transmission line. Transmission circuit. 2. A first digital signal is output from a first output, and a second digital signal is output from a second output in synchronization with the first digital signal, having the opposite polarity and the same clock cycle, A third digital signal synchronized with the first digital signal is output from a third output, and a fourth digital signal synchronized with the third digital signal from the fourth output and having the opposite polarity and the same clock cycle is output from the fourth output. A first emitter follower circuit to which the first digital signal output by the digital data generation circuit is input, and the second digital signal output by the digital data generation circuit to input A first emitter-follower circuit pair having a second emitter-follower circuit having the same configuration as the first emitter-follower circuit; an output of the first emitter-follower circuit; A first transmission line having one end connected thereto, a second transmission line having one end connected to the output of the second emitter follower circuit, and a digital signal transmitted through the first transmission line and the second transmission line. A first comparator for comparing signals, a third emitter follower circuit having the same configuration as the first emitter follower circuit to which the third digital signal output from the digital data generation circuit is input, and the digital data generation circuit And a second emitter follower circuit pair having the fourth digital signal output from the third emitter follower circuit and having a fourth emitter follower circuit having the same configuration as the first emitter follower circuit, and an output of the third emitter follower circuit. A third transmission line having one end connected thereto, a fourth transmission line having one end connected to the output of the fourth emitter follower circuit, the third transmission line and the fourth Second comparator for comparing the digital signals transmitted by the sending passage, and a pulse having a phase comparator, for comparing the phase of the digital signal inputted from said second comparator and said first comparator Transmission circuit. 3. The first to fourth emitter follower circuits include: a transistor to which a digital signal input to each of the first to fourth emitter follower circuits is input to a base; one end of an emitter of the transistor; Connected resistors,
3. The pulse transmission circuit according to claim 1, further comprising: a current bias circuit connected to the other end of the resistor and flowing a current through the resistor. 4. 4. The pulse transmission circuit according to claim 1, wherein the first to fourth transmission lines have the same shape, the same size, and the same material. 5. The pulse transmission circuit according to claim 1, wherein the first to fourth transmission paths are arranged at adjacent positions. 6. The pulse transmission circuit according to claim 1, wherein each of the first and second transmission paths is configured as a transmission circuit that connects the emitter follower circuit pair and the phase comparator that are integrated into an IC. .