JPH0410804A - Integrated circuit device - Google Patents

Abstract

PURPOSE:To obtain a high yield while keeping high performance and low noise characteristic by selecting the gate length of a FET used for a 1st stage of a low noise multi-stage amplifier for microwave shorter than the gate length of a FET used for a post-stage. CONSTITUTION:A FET 10 of a 1st stage consists of a source electrode 11, a gate electrode 12 and a drain electrode 13. Moreover, a FET 20 (30, 40) of a 2nd (and succeeding) stage consists of a source electrode 21(31, 41), a gate electrode 22(32, 42) and a drain electrode 23(33, 43) respectively. Then the length of the gate electrode 12 of the FET 10 of the 1st stage is selected shorter than the length of the gate electrodes 22, 32, 42 respectively. Thus, the yield is improved and low noise multi-stage amplifier is attained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microwave integrated circuit for low-noise amplification used in a receiving device such as a satellite communication system.

[Conventional technology]

Microwave low-noise amplifiers generally have a multi-stage configuration in order to obtain a desired gain.

In addition, in order to reduce noise, FETs (@
The gate length of the field effect transistor (field effect transistor) is kept as short as possible.

FIG. 5 shows the relationship between gate length and noise figure. The noise figure of FET is 0.0 when the gate length is 0. 3-0.5μm
It is known that above and below it is proportional to the gate length, and below that it is approximately proportional to the logarithm of the gate length. Therefore, the shorter the gate length, the lower the noise figure.

[Problem to be solved by the invention]

However, there is a problem that the shorter the gate length is, the greater the manufacturing variation becomes, and the yield deteriorates. A decrease in productivity in the manufacture of FETs must be avoided as much as possible because it leads to an increase in manufacturing costs. especially,
Processing short gates of 0.1 μm to 0.25 μm requires an electron beam exposure device, but the productivity of this electron beam exposure device is considerably lower than that of an optical exposure device. In multi-stage amplifiers, the product of the yields of each stage is often the yield of the amplifier as a whole, so the poor yield of FETs is compounded.

An object of the present invention is to solve these problems.

[Means to solve the problem]

In order to solve the above problems, the present invention has been made, and is an integrated circuit device having a low-noise multi-stage amplifier that can be expected to have a high manufacturing yield while maintaining high-performance low-noise characteristics. Specifically, the gate length of the FET used in the first stage of the low-noise multistage microwave amplifier is shorter than the gate length of the FET used in the latter stage.

[Effect]

In a low-noise multi-stage microwave amplifier, the noise figure of the first stage accounts for a large proportion of the total noise figure.

Therefore, the low-noise multi-stage amplifier for microwaves according to the present invention, in which the first stage FET has a short gate length and a small noise figure, has a small noise figure as a whole.

Moreover, since the gate length of the FET in the subsequent stage is relatively long, the yield is good, and the yield of the integrated circuit device as a whole is also high.

〔Example〕

Embodiments of the present invention will be described with reference to FIGS. 1 to 4 of the accompanying drawings.

FIG. 2 is a circuit diagram showing a low-noise multi-stage amplifier in this embodiment, and FIG. 1 is a modeled illustration of the layout of FETs in each stage. As shown in FIG. 4, the actual FET pattern has a structure in which the gate length is extremely short compared to the gate width. The FET in FIG. 4 is composed of a source electrode 71, a gate electrode 72, and a drain electrode 73.

As shown in FIG. 1, four FETs are arranged on a semiconductor substrate 1. The first stage FETl0 has a source electrode 11
, a gate electrode 12, and a drain electrode 13. The FETs 20, 30, and 40 from the second stage onwards are also respectively,
Source electrode 21.31.41, gate electrode 22.32.
42, and drain electrodes 23, 33, and 43.

The gate length of each FET is 0.2 μm for the gate electrode 12.
One gate electrode 22, 32, 42 is 0.5 μm.

The characteristic feature of this embodiment is that the first stage FET10
The gate electrode 12 of is the gate electrode 22 of the subsequent FET,
This means that the gate length is shorter than that of the gate electrode 32 and the gate electrode 42. This gate electrode 12 helps to reduce the noise of the low-noise multi-stage amplifier of this embodiment.

Next, describe the considerations made to develop the present invention.

First, let's consider reducing noise in multistage amplifiers.

Noise figure N F of a multistage amplifier that connects n stages of FETs
T is NF −NF + (NF2-1)/G, + (N
I F -1)/G1G2+...+(NF, -1
)/G1 G2...' n-1. The variables used in these formulas are as follows.

NF z Total noise figure NF : First stage noise figure NF : Second stage noise figure NF : Third stage noise figure NF : Nth stage noise figure G1 : First stage gain G2 : Second stage gain G3 : th Gain G of 3rd stage; Gain n-1 of n-1th stage By the way, gain G of each FET SG SG3,...G
each usually has a value of 10.0 or more.

Therefore, the values of the second and subsequent terms having these gains as denominators are much smaller than the first term, and the values of the second and subsequent terms are almost ignored. The total noise figure NFT is approximately determined by the value of the first term noise figure NF.

In other words, by simply shortening the gate length of the first stage FET, the total FET
The noise figure of ET can be kept sufficiently low.

Next, we will consider the yield of multistage amplifiers. As mentioned above, in order to reduce the noise of a multistage amplifier, the gate length of the first stage FET can be shortened. However, the gain in this case is
This is lower than when the gate lengths of all FETs in a multistage amplifier are shortened. The reason for this is that the gain of each FET decreases as the gate length increases. Therefore, if you try to obtain the same gain as a multistage amplifier where the gate lengths of all FETs are shortened, but with a multistage amplifier where only the gate length of the first stage FET is shortened, the FET
We need to increase the number of ET stages. Increasing the number of FETs reduces yield. Therefore, the relationship between increasing the number of FET stages to prevent the gain from decreasing and yield will be discussed using the following example.

FIG. 3(a) is an example of a conventionally used general low-noise multistage amplifier 5o. The low noise multistage amplifier 50 has three
The FET gate length of each FET in each amplifier is 0.2 μm. FIG. 3(b) shows an embodiment of the present invention, in which a low noise multistage amplifier 6o has the same gain as the low noise multistage amplifier 5o.
This is an example. In the low noise multistage amplifier 6o, the first stage amplifier 6
A FET with a gate length of 0.2 μm is used for the amplifier 62, 63, and 64 in the second and subsequent stages.
A 0.5 μm FET, which is longer than the ET, is used.

In these two examples, amplifier 51.52.53.61
al, the yield of the FET used in the amplifier 62.
If the yield of the FET used in 63.64 is a, then the yield of the low-noise multi-stage amplifier 50 is α13, and the yield of the low-noise multi-stage amplifier 6° is α α.

Therefore, in this embodiment, if the relationship αlα2>α13 2/3 pa・α2>αI holds true, the desired yield can be secured without reducing the gain.

Although it is difficult to say for sure how thick α2 is compared to α1 since it depends on the process and manufacturing equipment, it is thought that there is a difference of more than twice in terms of the difficulty of manufacturing (microfabrication). Therefore, the current manufacturing technology sufficiently satisfies the above equation.

Regarding the FET in the final stage of the low-noise multi-stage amplifier,
A longer gate length is preferable because the output impedance is more stable. In particular, if the final stage gate length is approximately 1 to 1.2 μm, the stability index K of the FET will be greater than 1, and the performance will be stable. On the other hand, in devices where the stability index K of the FET is smaller than 1, matching is particularly difficult, and the impedance characteristics change greatly in response to device variations, which is one of the factors that lowers the yield.

Therefore, if the low-noise multi-stage amplifier according to the present invention is designed so that the stability index K of the final stage FET is greater than 1, the output impedance will be stabilized.

〔Effect of the invention〕

The low-noise multistage amplifier for microwaves based on the present invention realizes a high-performance amplifier with a low noise figure. Furthermore, since the structure is easy to manufacture, the yield is high and it is economical.

[Brief explanation of the drawing]

FIG. 1 is a perspective view showing a low-noise multi-stage amplifier for microwaves according to an embodiment of the present invention, FIG. 2 is a circuit diagram of a low-noise multi-stage amplifier for microwaves according to an embodiment of the present invention, and FIG. 3 is a conventional example. FIG. 4 is a plan view showing an example of a FET pattern, and FIG. 5 is a diagram showing the relationship between gate length and noise figure. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 11... Source electrode of FETI, 12... Gate electrode of FETI, 13... FETI
drain electrode of 21...source electrode of FET2, 2
2... Gate electrode of FET2, 23... Drain electrode of FET2, 31... Source electrode of FET3, 32
...Gate electrode of FET3, 33...Drain electrode of FET3, 41...Source electrode of FET4, 42.
...Gate electrode of FET4, 43...Drain electrode of FET4. Representative Patent Attorney Yoshiki Hasejo
Salt 1) Comparison of Tatsuya's four-legged arrangement and the laughing example Figure 3 FET pattern

Claims (1)

[Claims] 1. In an integrated circuit device including a low-noise multi-stage microwave amplifier, the gate length of the FET used in the first stage of the low-noise multi-stage microwave amplifier is equal to the gate length of the FET used in the subsequent stage. An integrated circuit device characterized by being shorter than the gate length. 2. The integrated circuit device according to claim 1, wherein the FET used in the final stage of the low-noise multi-stage amplifier for microwaves has a gate length such that its stability index K is 1 or more.