JPH04107879A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH04107879A JPH04107879A JP2225799A JP22579990A JPH04107879A JP H04107879 A JPH04107879 A JP H04107879A JP 2225799 A JP2225799 A JP 2225799A JP 22579990 A JP22579990 A JP 22579990A JP H04107879 A JPH04107879 A JP H04107879A
- Authority
- JP
- Japan
- Prior art keywords
- region
- area
- extended drain
- crosswise
- silicon substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims 2
- 239000000758 substrate Substances 0.000 claims abstract description 22
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 17
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 17
- 239000010703 silicon Substances 0.000 claims abstract description 17
- 230000015556 catabolic process Effects 0.000 abstract description 7
- 230000006866 deterioration Effects 0.000 abstract 1
- 230000005669 field effect Effects 0.000 description 6
- 230000000694 effects Effects 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Composite Materials (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、高耐圧横型ＭＯ８電界効果トランジスタに関
するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a high voltage lateral MO8 field effect transistor.
従来の技術
すなわち従来の高耐圧横型ＭＯ８電界効果トランジスタ
は第３図、第４図に示すようになっていた。−導電型（
Ｐ型）のシリコン基板１に、前記シリコン基板１とは逆
導電型（Ｎ型）の楕円リング状延長ドレイン領域２が設
けられ、かつ、前記延長ドレイン領域２の内部に包含さ
れるようにシリコン基板１と同一導電型（Ｐ型）の領域
（以下、ＦＴ領領域称する）３が形成され、さらに延長
ドレイン領域２内にはＰＴ領域３と並置されるようにＮ
＋のコンタクト領域４が形成され、この領域４はドレイ
ン電極５に接続されている。さらにシリコン基板１には
楕円リング状ゲート６を間にして延長ドレイン領域２と
相対するようにＮ＋の楕円状ソース領域７が形成され、
この領域はソース電極８に接続されている。またゲート
６は電極９に接続されている。さらにこの従来の構造で
は、第３図に示すように、延長ドレイン領域２の長さＬ
ａとＰＴ領域３の横方向長さＬｂが、曲線で形成された
部分Ａと、直線で形成された部分Ｂにおいて、同じにな
っている。The conventional technology, that is, the conventional high voltage lateral MO8 field effect transistor is shown in FIGS. 3 and 4. −Conductivity type (
An elliptical ring-shaped extended drain region 2 of a conductivity type opposite to that of the silicon substrate 1 (N type) is provided on a silicon substrate 1 (P type), and a silicon A region (hereinafter referred to as FT region) 3 of the same conductivity type (P type) as the substrate 1 is formed, and an N region is formed in the extended drain region 2 so as to be juxtaposed with the PT region 3.
A + contact region 4 is formed, which region 4 is connected to the drain electrode 5 . Furthermore, an N+ elliptical source region 7 is formed on the silicon substrate 1 so as to face the extended drain region 2 with an elliptical ring-shaped gate 6 in between.
This region is connected to the source electrode 8. Further, the gate 6 is connected to an electrode 9. Furthermore, in this conventional structure, as shown in FIG.
a and the lateral length Lb of the PT region 3 are the same in the curved portion A and the straight portion B.
発明が解決しようとする課題
このような従来の構造では、ＭＯ８電界効果トランジス
タがオフしているとき、表面でのソース、ドレインの各
領域と基板との境界線が曲線で形成された部分Ａでソー
ス領域の外債にドレイン領域が存在する部分では、前記
境界が直線で形成された部分Ｂに比べて、延長ドレイン
領域の空乏層がよく広がり、低いドレイン・ソース間電
圧でもって延長ドレイン領域２内部が空乏化してしまう
ものであった。このため、前記ソース領域７の外側にド
レイン領域が存在する部分Ａでは耐圧が低くなるという
課題があった。Problems to be Solved by the Invention In such a conventional structure, when the MO8 field effect transistor is off, the boundary line between the source and drain regions and the substrate on the surface is a curved portion A. In the part where the drain region exists outside the source region, the depletion layer of the extended drain region spreads more widely than in the part B where the boundary is formed with a straight line. was depleted. Therefore, there is a problem that the breakdown voltage is low in the portion A where the drain region exists outside the source region 7.
課題を解決するための手段
そこで、本発明では、この課題、すなわち耐圧低下を防
ぐために、表面でのソース、ドレインの各領域と基板と
の境界が曲線で形成された部分でソース領域の外側にド
レイン領域が存在する部分において、ＰＴ領領域延長ド
レイン領域の長さを長くする。Means for Solving the Problems Therefore, in the present invention, in order to solve this problem, that is, to prevent a drop in breakdown voltage, the boundary between the source and drain regions and the substrate on the surface is curved, and the boundary between the source region and the substrate is formed outside the source region. In the portion where the drain region exists, the length of the PT region extension drain region is increased.
作 用
上記のような構造にすることにより、表面でのソース、
ドレインの各領域と基板との境界が ｊＩ線で形成され
た部分より、曲線で形成された部分において、延長ドレ
イン領域が低いドレイン・ソース間電圧で空乏化してし
まうことを防ぐことができる。その結果、耐圧低下を防
ぐことができる。Effect By creating the structure as described above, the source on the surface,
It is possible to prevent the extended drain region from being depleted due to a low drain-source voltage in the curved portion than in the portion where the boundary between each region of the drain and the substrate is formed by the jI line. As a result, a decrease in breakdown voltage can be prevented.
実施例
以下、本発明の一実施例におけるＮチャネル横型ＭＯＳ
電界効果トランジスタについて第１図。Example Below, an N-channel lateral MOS in an example of the present invention will be described.
Fig. 1 about a field effect transistor.
第２図とともに説明する。これら第１図、第２図におい
て、１１はＰ型のシリコン基板、１２は型の延長ドレイ
ン領域、１３はこのドレイン領域１２内に設けられたＰ
型のＰＴｌＩｆｆ域、１４は同コンタクト領域、１５は
ドレイン電極、１６はゲート、１７はソース領域、１８
はソース電極、１９はゲート電極である。なお、第１図
はシリコン酸化膜や、アルミ電極、パッシベーション膜
を除去したシリコン基板表面を示している。This will be explained with reference to FIG. 1 and 2, 11 is a P-type silicon substrate, 12 is an extended drain region of the mold, and 13 is a P-type silicon substrate provided within this drain region 12.
PTlIff region of the type, 14 is the same contact region, 15 is the drain electrode, 16 is the gate, 17 is the source region, 18
is a source electrode, and 19 is a gate electrode. Note that FIG. 1 shows the surface of a silicon substrate from which a silicon oxide film, an aluminum electrode, and a passivation film have been removed.
このような本実施例のトランジスタでは、表面でのソー
ス１７．ドレイン１２の各領域とシリコン基板１１との
境界が曲線で形成された部分Ｘでソース領域１７の外側
にドレイン領域１２が存在する部分における、ＰＴ領域
１３の横方向長さＬｌの最大値を４４μｍ、延長ドレイ
ン領域１２の横方向長さＬ２の最大値を６０μｍとする
。また、直線で形成された部分ＹにおけるＰＴ領域１３
の横方向長さＬ３を２４μｍ （＜ Ｌ １ ） 、延
長ドレイン領域の横方向長さＬ４を４０μｍ （＜ Ｌ
２ ）とする。その結果、すべての部分において、Ｐ
Ｔ領領域横方向長さＬｂを２４μｍ、延長ドレイン領域
の横方向長さＬａを４０μｍとした従来の構造に比べて
、耐圧を１０％向上させることができた。In the transistor of this embodiment, the source 17. The maximum value of the lateral length Ll of the PT region 13 in the portion X where the boundary between each region of the drain 12 and the silicon substrate 11 is formed by a curve and the drain region 12 exists outside the source region 17 is 44 μm. , the maximum value of the lateral length L2 of the extended drain region 12 is 60 μm. In addition, the PT region 13 in the portion Y formed by the straight line
The lateral length L3 of the extended drain region is 24 μm (< L 1 ), and the lateral length L4 of the extended drain region is 40 μm (< L 1 ).
2). As a result, in all parts, P
Compared to the conventional structure in which the lateral length Lb of the T region was 24 μm and the lateral length La of the extended drain region was 40 μm, the breakdown voltage could be improved by 10%.
発明の効果 以上のように、本発明では、表面でのソース。Effect of the invention As described above, in the present invention, the source on the surface.
ドレインの各領域と基板との境界が曲線で形成された部
分でソース領域の外側にドレイン領域が存在する部分に
おいて、ＰＴ領領域よび延長トレイン領域の横方向長さ
を、前記境界が直線で形成された部分におけるＰＴ領領
域よび延長ドレイン領域の横方向長さに比べ長くするこ
とにより、従来課題であった耐圧低下を防止することが
できる。In a portion where the boundary between each drain region and the substrate is a curved line and the drain region exists outside the source region, the lateral length of the PT region and the extended train region is determined by the boundary being a straight line. By making the PT region and the extended drain region longer in the lateral direction than the lateral length thereof, it is possible to prevent a decrease in breakdown voltage, which has been a problem in the past.
第１図は本発明の一実施例におけるＮチャネル横型ＭＯ
Ｓ電界効果トランジスタの平面図、第２図（ａ） 、
（ｂ）は第１図のＡ−Ａ ’線およびＢ−Ｂ ゛線断面
図、第３図は従来の横型Ｍｏ５ｔ界効果トランジスタの
平面図、第４文は同断面図である。
１１・・・・・・シリコン基板、Ｉ２・旧・・延長ドレ
イン領域、１３・・・・・・ＰＴ領領域Ｌｌ・・曲・Ｐ
Ｔ領領域横方向長さ、Ｌ２・・・・・・延長ドレイン領
域の横方向長さ、Ｌ３・・・・・・ＰＴ＠域の横方向長
さ、Ｌ４・・・・・・延長ドレイン領域の横方向長さ。
代理人の氏名 弁理士 小鍛治 明はが２名第
図
１２−−−ｄＡＫＬイシ鳥看ｒ４、
第
図
＋１−一一シリコソ、１ｇ
＋１−１長１３４ン凄肴ｒ鴫、
１丁−・′へス々貴■啄
ＩＩ−−−１ハス
５−ＭＬイン
寥−一−・ノースFIG. 1 shows an N-channel lateral MO in one embodiment of the present invention.
Plan view of S field effect transistor, Fig. 2(a),
(b) is a sectional view taken along lines AA' and B-B' in FIG. 1, FIG. 3 is a plan view of a conventional lateral Mo5t field effect transistor, and the fourth sentence is a sectional view of the same. 11...Silicon substrate, I2/Old...Extended drain region, 13...PT region Ll...Song/P
T area lateral length, L2...lateral length of extended drain area, L3...lateral length of PT@ area, L4...extended drain area lateral length. Name of agent: Patent attorney Kokaji Akihabara, 2 persons Fig. 12--dAKL Ishicho r4, Fig. +1-11 Shirikoso, 1g +1-1 length 134 inches, 1 cho-・' Hess Taka ■ Taku II ---1 Hass 5-ML In-1 North
Claims (1)
電型の延長ドレイン領域とソース領域を設け、前記延長
ドレイン領域内にシリコン基板と同一導電型領域を形成
し、シリコン基板表面でのドレイン、ソースの各領域と
シリコン基板との境界線の全部または一部が曲線によっ
て形成されるとともに、前記延長ドレイン領域と延長ド
レイン領域内に形成された領域の横方向の長さを、表面
でのドレイン、ソースの各領域とシリコン基板との境界
線が直線で形成された部分よりも、曲線で形成された部
分でドレイン領域の外側にソース領域が存在する部分に
おいて、長くした半導体装置。A silicon substrate of one conductivity type is provided with an extended drain region and a source region of a conductivity type opposite to that of the silicon substrate, a region of the same conductivity type as the silicon substrate is formed in the extended drain region, and a drain region on the surface of the silicon substrate is formed. All or part of the boundary line between each region of the source and the silicon substrate is formed by a curve, and the lateral length of the extended drain region and the region formed within the extended drain region is , a semiconductor device in which the boundary line between each region of the source and the silicon substrate is longer in the curved part where the source region is outside the drain region than in the straight part.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2225799A JP2599494B2 (en) | 1990-08-27 | 1990-08-27 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2225799A JP2599494B2 (en) | 1990-08-27 | 1990-08-27 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04107879A true JPH04107879A (en) | 1992-04-09 |
| JP2599494B2 JP2599494B2 (en) | 1997-04-09 |
Family
ID=16834967
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2225799A Expired - Fee Related JP2599494B2 (en) | 1990-08-27 | 1990-08-27 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2599494B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012212842A (en) * | 2011-03-23 | 2012-11-01 | Toshiba Corp | Semiconductor device |
| CN110299356A (en) * | 2019-07-26 | 2019-10-01 | 宁波芯浪电子科技有限公司 | A kind of electrostatic protection method for metal-oxide-semiconductor |
-
1990
- 1990-08-27 JP JP2225799A patent/JP2599494B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012212842A (en) * | 2011-03-23 | 2012-11-01 | Toshiba Corp | Semiconductor device |
| CN110299356A (en) * | 2019-07-26 | 2019-10-01 | 宁波芯浪电子科技有限公司 | A kind of electrostatic protection method for metal-oxide-semiconductor |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2599494B2 (en) | 1997-04-09 |
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