JPH04107756A - Eeprom protecting system - Google Patents
Eeprom protecting systemInfo
- Publication number
- JPH04107756A JPH04107756A JP2227135A JP22713590A JPH04107756A JP H04107756 A JPH04107756 A JP H04107756A JP 2227135 A JP2227135 A JP 2227135A JP 22713590 A JP22713590 A JP 22713590A JP H04107756 A JPH04107756 A JP H04107756A
- Authority
- JP
- Japan
- Prior art keywords
- eeprom
- cpu
- writing device
- rom
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 8
- 230000006378 damage Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 101100524639 Toxoplasma gondii ROM3 gene Proteins 0.000 description 1
- RRLHMJHRFMHVNM-BQVXCWBNSA-N [(2s,3r,6r)-6-[5-[5-hydroxy-3-(4-hydroxyphenyl)-4-oxochromen-7-yl]oxypentoxy]-2-methyl-3,6-dihydro-2h-pyran-3-yl] acetate Chemical compound C1=C[C@@H](OC(C)=O)[C@H](C)O[C@H]1OCCCCCOC1=CC(O)=C2C(=O)C(C=3C=CC(O)=CC=3)=COC2=C1 RRLHMJHRFMHVNM-BQVXCWBNSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013256 coordination polymer Substances 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
Landscapes
- Read Only Memory (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
Description
【発明の詳細な説明】
〔概 要〕
ＣＰＵ、ＲＯＭ、ＲＡＭ及びＥＥＰＲＯＭを搭載する装
置に関し、
該ＥＥＰＲＯＭの内部データを更新するＥＥＰＲＯＭ書
込み装置未接続中は、該ＥＥＰＲＯＭ内部データの書込
みを防止することを目的とし、該ＥＥＰＲＯＭを搭載す
る装置に、該ＥＥＰＲＯＭ書込み装置の接続の状態を判
定する接続判定回路を儲け、
該ＥＥＰＲＯＭ書込み装置に、該ＥＥＰＲＯＭ搭載装置
に接続時送出する信号送出回路を儲け、該ＥＥＰＲＯＭ
書込み装置接続中は該書込み装置に搭載されたＲＯＭの
内部データを該ＥＥＰＲＯＭに転送し、
該ＥＥＰＲＯＭ書込み装置未接続中は、該ＥＥＰＲＯＭ
搭載装置のＥＥＰＲＯＭに対するＣＰＵからの書込みを
禁止するように構成する。[Detailed Description of the Invention] [Summary] Regarding a device equipped with a CPU, ROM, RAM, and EEPROM, writing of the internal data of the EEPROM is prevented while an EEPROM writing device for updating the internal data of the EEPROM is not connected. For the purpose of this, a device equipped with the EEPROM is provided with a connection determination circuit for determining the connection state of the EEPROM writing device, and the EEPROM writing device is provided with a signal sending circuit that sends out a signal when connected to the EEPROM device, The EEPROM
When the writing device is connected, the internal data of the ROM installed in the writing device is transferred to the EEPROM, and when the EEPROM writing device is not connected, the internal data of the ROM installed in the writing device is transferred to the EEPROM.
The configuration is such that writing from the CPU to the EEPROM of the installed device is prohibited.
本発明は、ＣＰＵ、ＲＯＭ、ＲＡＭ及びＥＥＰＲＯＭを
搭載する装置におけるＥＥＰＲＯＭプロテクト方式に関
する。The present invention relates to an EEPROM protection method in a device equipped with a CPU, ROM, RAM, and EEPROM.
ＥＥＰＲＯＭはプログラム的に書込み可能なリードオン
リーメモリで、電源を除いても書込まれたメモリ内容は
消去されないので、最近は種々の装置に搭載されて使用
されている。EEPROM is a read-only memory that can be written programmatically, and the written memory contents are not erased even if the power is turned off, so it has recently been installed and used in various devices.
現在電子交換機を複数の交換台と接続する場合に、その
接続制御に交換台制御装置が使用されている。この交換
台制御装置は従来ＣＰＵ、ＲＯＭ。Currently, when an electronic exchange is connected to a plurality of switchboards, a switchboard control device is used to control the connections. This switchboard control device conventionally uses CPU and ROM.
ＲＡＭ等から構成されて、ＲＯＭに装置を動かすに必要
なプログラムを書込み、ＲＡＭには計算結果を一時記憶
して交換台に対する接続処理をＣＰＵで処理していた。It consisted of RAM, etc., and the programs necessary to operate the device were written in the ROM, calculation results were temporarily stored in the RAM, and the connection process to the switchboard was processed by the CPU.
しかし、ＲＯＭに書込むプログラムは必要に応じて更新
等のため、現地でＲＯＭのＩＣを交換する場合があり、
ＩＣパッケージの抜き差しによるトラブルが発生する問
題があった。そこで、プログラム的に書込み可能なリー
ドオンリーメモリＥＥＰＲＯＭを交換台制御装置に搭載
し、ＲＯＭのＩＣ交換トラブルを防止するようになった
。However, in order to update the program written to the ROM as necessary, the ROM IC may be replaced on-site.
There was a problem in which troubles occurred due to the insertion and removal of the IC package. Therefore, a read-only memory EEPROM that can be written programmatically has been installed in the switchboard control device to prevent the trouble of replacing the ROM IC.
従来のＥＥＰＲＯＭ搭載装置のブロック構成図を第３図
に示す。図において、２１はＥＥＰＲＯＭ搭載装置、２
２はＥＥＰＲＯＭ書込み装置、２３はＥＥＰＲＯＭ搭載
装置に搭載されるＥ Ｅ Ｐ ＲＯＭ、２４は同搭載装
置のＲＯＭ、２５は同搭載装置のＲＡＭ、２６は同搭載
装置のＣＰＵ、２７はＥＥＰＲＯＭ書込み装置のＲＯＭ
、２８は差込みプラグを示す。A block diagram of a conventional EEPROM-equipped device is shown in FIG. In the figure, 21 is an EEPROM mounted device, 2
2 is an EEPROM writing device, 23 is an EEPROM installed in the EEPROM loading device, 24 is a ROM of the loading device, 25 is a RAM of the loading device, 26 is a CPU of the loading device, 27 is an EEPROM writing device of the loading device. ROM
, 28 indicates a plug.
ＥＥＰＲＯＭ書込み装置２２はプログラム設定用のＲＯ
Ｍ２７を搭載し、差込みプラグ２８によりＥＥＰＲＯＭ
搭載装置２１に容易に接続可能で、プログラム設定用の
ＲＯＭ２７は種々用意してあり、必要なプログラムを搭
載したＥＥＰＲＯＭ書込み装置２２を、現地でＥＥＰＲ
ＯＭ搭載装置２１に差込みプラグ２８で、差込み、ＥＥ
ＰＲＯＭ搭載装置２１のＥＥＰＲＯＭ２３にＥＥＰＲＯ
Ｍ書込み装置２２のＲＯＭ２７のプログラム内容を転送
することができる。The EEPROM writing device 22 is an RO for program setting.
Equipped with M27, EEPROM with plug 28
A variety of ROMs 27 are available for program settings that can be easily connected to the on-board device 21, and the EEPROM writing device 22 loaded with the necessary programs can be easily connected to the on-board device 21.
Insert the plug 28 into the OM-equipped device 21, and connect the EE
EEPRO in EEPROM23 of PROM mounted device 21
The program contents of the ROM 27 of the M writing device 22 can be transferred.
ＥＥＰＲＯＭ書込み装置２２をＥＥＰＲＯＭ搭載装置２
１に接続すると、ＣＰＵ２６がＲＯＭ２７のデータを読
込み、ＣＰＵ２６は読込んだデータを書込み端子により
ＥＥＰＲＯＭ２３に書込む。したがってＥＥＰＲＯＭ２
３のプログラム内容が書換えられる。The EEPROM writing device 22 is connected to the EEPROM loading device 2.
1, the CPU 26 reads data from the ROM 27, and writes the read data to the EEPROM 23 through the write terminal. Therefore, EEPROM2
3 program contents are rewritten.
ＲＡＭ２５はワーク用として使用され計算結果を一時記
憶する。ＥＥＰＲＯＭ２３のプログラム内容はＥＥＰＲ
ＯＭ書込み装置２２を抜いても保持されているが、別の
プログラム内容のＥＥＰＲＯＭ書込み装置を差込めば、
Ｅ Ｅ Ｐ Ｒ０６Ｍ２３のプログラム内容も書換えら
れる。The RAM 25 is used for work and temporarily stores calculation results. The program contents of EEPROM23 are EEPR
It is retained even if the OM writing device 22 is removed, but if you insert an EEPROM writing device with different program contents,
The program contents of EEP R06M23 are also rewritten.
上記従来の方式では、ＥＥＰＲＯＭ書込み装置２２がＥ
ＥＰＲＯＭ搭載装置２Ｉに差込まれてない時、ＣＰＵ２
６からの書込みアクセスによりＥＥＰＲＯＭ２３に書込
みが可能なため、ＥＥＰＲＯＭ２３の内部データの書換
えか可能であった。このためＥＥＰＲＯＭ搭載装置のプ
ログラム暴走等によるＥＥＦＲＯＭ内部データの破壊と
いう問題かあった。In the conventional method described above, the EEPROM writing device 22
When the EPROM is not inserted into the device 2I, the CPU 2
Since it is possible to write to the EEPROM 23 through write access from 6, it is only possible to rewrite the internal data of the EEPROM 23. For this reason, there was a problem of destruction of internal data in the EEFROM due to program runaway in the EEPROM-equipped device.
本発明は、ＥＥＰＲＯＭ２３の書込み端子にＣＰＵ２６
からの書込み信号の他に、ＥＥＰＲＯＭ書込み装置２２
かＥＥＰＲＯＭ搭載装置２１に完全に差込まれている時
だけ有効になる「接続中Ｊ信号の条件を入れることによ
り、ＥＥＰＲＯＭ２３内部データの破壊を防止すること
を目的とする。In the present invention, the CPU 26 is connected to the write terminal of the EEPROM 23.
In addition to the write signal from the EEPROM writing device 22
The purpose of this is to prevent the internal data of the EEPROM 23 from being destroyed by setting the condition of the "connected J signal" which becomes valid only when the EEPROM is completely inserted into the EEPROM mounted device 21.
本発明の原理構成図を第１図に示す。図において、Ｉは
ＥＥＰＲＯＭ搭載装置、２はＥＥＦＲＯＭ書込み装置、
３は搭載装置のＥＥＦＲＯＭ、４は搭載装置のＲＯＭ、
５は搭載装置のＲＡＭ、６は搭載装置のＣＰＵ、７は書
込み装置のＲＯＭを示す。FIG. 1 shows the principle configuration diagram of the present invention. In the figure, I is an EEPROM loading device, 2 is an EEFROM writing device,
3 is the EEFROM of the installed device, 4 is the ROM of the installed device,
5 is the RAM of the mounted device, 6 is the CPU of the mounted device, and 7 is the ROM of the writing device.
該ＥＥＰＲＯＭ３を搭載する装置１に、該ＥＥＦＲＯＭ
書込み装置２との接続状態を判定する接続判定回路８を
儲け、
該ＥＥＰＲＯＭ書込み装置２に、該ＥＥＰＲＯＭ搭載装
置ｌとの接続時送出する信号送出回路９を儲け、
該ＥＥＰＲＯＭ書込み装置２を該ＥＥＰＲＯＭ搭載装置
１に接続中は該書込み装置２に搭載されたＲＯＭ７の内
部データをＥＥＰＲＯＭ３に転送し、
該ＥＥＰＲＯＭ書込み装置２を接続していない時は、該
ＥＥＰＲＯＭ搭載装置１のＥＥＰＲＯＭ３に対するＣＰ
Ｕ６からの書込みを禁止するように構成する。The EEFROM 3 is installed in the device 1 equipped with the EEPROM 3.
A connection determination circuit 8 for determining the connection state with the writing device 2 is provided, and a signal sending circuit 9 is provided for the EEPROM writing device 2 to send out a signal when connected to the EEPROM-equipped device l, and the EEPROM writing device 2 is connected to the EEPROM. While connected to the installed device 1, the internal data of the ROM 7 installed in the writing device 2 is transferred to the EEPROM 3, and when the EEPROM writing device 2 is not connected, the CP for the EEPROM 3 of the EEPROM installed device 1 is transferred.
It is configured to prohibit writing from U6.
（１） Ｅ Ｅ Ｐ ＲＯＭ書込み装置２を接続中の
場合、ＥＥＰＲＯＭ書込み装置２の信号送出回路９の地
気が差込みプラグを経由してＥＥＰＲＯＭ搭載装置１の
接続判定回路８に接続される。接続判定回路８はＥＥＰ
ＲＯＭ書込み装置２の信号送出回路９の地気を検出して
、ＣＰＵ６からＥＥＰＲＯＭ３への書込み線を接続し、
ＲＯＭ７からのデータがＣＰＵ６に接続されると、ＣＰ
Ｕ６からの書込み信号がＥＥＰＲＯＭ３に接続され、Ｒ
ＯＭ７のデータがＥＥＰＲＯＭ３に転送される。ＲＯＭ
４には転送用プログラムが格納され、ＲＡＭ５はワーク
として使用される。(1) When the EEPROM writing device 2 is being connected, the signal from the signal sending circuit 9 of the EEPROM writing device 2 is connected to the connection determination circuit 8 of the EEPROM loading device 1 via the plug. Connection determination circuit 8 is EEP
Detect the signal transmission circuit 9 of the ROM writing device 2, connect the write line from the CPU 6 to the EEPROM 3,
When data from ROM7 is connected to CPU6, CPU
The write signal from U6 is connected to EEPROM3 and R
Data in OM7 is transferred to EEPROM3. ROM
4 stores a transfer program, and RAM 5 is used as a work.
（２） Ｅ Ｅ Ｐ ＲＯＭ書込み装置２を未接続の
場合、ＥＥＰＲＯＭ書込み装置２の信号送出回路９の地
気が送出されないので、ＥＥＰＲＯＭ搭載装置Ｉ搭載装
置窓回路８に信号が送出されず、接続判定回路８はＥＥ
ＰＲＯＭ書込み装置２との接続が無いと判定し、ＣＰＵ
６とＥＥＰＲＯＭ３の書込み端子間の接続線を切り、Ｅ
ＥＰＲＯＭ３へはＣＰＵ６からの書込み信号が送出され
ない。したがって、ＥＥＰＲＯＭ書込み装置２が接続さ
れていない時は、ＥＥＰＲＯＭ３の内部データの書換え
は行われないで済む。(2) If the EEPROM writing device 2 is not connected, the signal sending circuit 9 of the EEPROM writing device 2 will not send out the air, so no signal will be sent to the EEPROM loading device I loading device window circuit 8, and the connection will be interrupted. Judgment circuit 8 is EE
It is determined that there is no connection with the PROM writing device 2, and the CPU
6 and the write terminal of EEPROM3, cut the connection wire between E
A write signal from the CPU 6 is not sent to the EPROM 3. Therefore, when the EEPROM writing device 2 is not connected, there is no need to rewrite the internal data of the EEPROM 3.
本発明の実施例のブロック構成図を第２図に示す。図に
おいて、ｌはＥＥＰＲＯＭ搭載装置、２はＥＥＰＲＯＭ
書込み装置、３は搭載装置のＥＥＰＲＯＭ、４は搭載装
置のＲＯＭ、５は搭載装置のＲＡＭ、６は搭載装置のＣ
ＰＵ、７は書込み装置のＲＯＭ、８は接続判定回路、９
は信号送出回路、１０は差込みプラグを示す。A block diagram of an embodiment of the present invention is shown in FIG. In the figure, l is an EEPROM equipped device, 2 is an EEPROM
Writing device, 3 is EEPROM of the installed device, 4 is ROM of the installed device, 5 is RAM of the installed device, 6 is C of the installed device
PU, 7 is the ROM of the writing device, 8 is a connection determination circuit, 9
1 indicates a signal sending circuit, and 10 indicates a plug.
ＥＥＰＲＯＭ搭載装置ｌ搭載装置窓回路８は抵抗ｌｌと
インバータ１２とアンド１３とからなり、ＥＥＰＲＯＭ
書込み装置２の信号送出回路９は地気１４からなる。差
込みプラグ１０を挿入中は地気１４の“０”がインバー
タＩ２の入力側に接続され、出力側には“ｌ”が送出さ
れ、ＣＰＵ６のＷＲＩＴＥ端子からの信号はアンド１３
の入力“ｌ”により制御されてそのまま出力され、ＥＥ
ＰＲＯＭ３のＷＲＩＴＥ端子に入力される。したがって
、ＥＥＰＲＯＭ書込み装置２のＲＯＭ７からの入力デー
タは保護され、ＣＰＵ３のＷＲＩＴＥ信号によりＥＥＰ
ＲＯＭ３に転送される。Device with EEPROM 1 Device with EEPROM The window circuit 8 consists of a resistor 1, an inverter 12, and an AND 13.
The signal sending circuit 9 of the writing device 2 consists of a ground air 14. While the plug 10 is inserted, "0" of the earth 14 is connected to the input side of the inverter I2, "l" is sent to the output side, and the signal from the WRITE terminal of the CPU 6 is AND13.
It is controlled by the input “l” of EE and is output as is.
It is input to the WRITE terminal of PROM3. Therefore, the input data from the ROM 7 of the EEPROM writing device 2 is protected, and the EEPROM write data is protected by the WRITE signal of the CPU 3.
Transferred to ROM3.
次に差込みプラグ１０が挿入されていない時は、地気１
４が接続されないので抵抗１１からの＋５ｖがインバー
タ１２の入力側に接続され、出力側には“０”が送出さ
れ、ＣＰＵ６のＷＲＩＴＥ端子からの信号はアンド１３
の入力“０”により制御されて、ＥＥＰＲＯＭ３のＷＲ
ＩＴＥ端子には“０”だけしか送出されない。したがっ
て、ＣＰＵ６からのＷＲＩＴＥ信号はＥＥＰＲＯＭ３の
ＷＲＩＴＥ端子には送出されず、ＥＥＰＲＯＭ書込み装
置が接続されてない時はＥＥＰＲＯＭ３の内部データは
書換えられることはない。Next, when the plug 10 is not inserted,
4 is not connected, +5V from the resistor 11 is connected to the input side of the inverter 12, "0" is sent to the output side, and the signal from the WRITE terminal of the CPU 6 is AND13.
is controlled by the input “0” of EEPROM3.
Only "0" is sent to the ITE terminal. Therefore, the WRITE signal from the CPU 6 is not sent to the WRITE terminal of the EEPROM 3, and the internal data of the EEPROM 3 is not rewritten when the EEPROM writing device is not connected.
本発明により、ＥＥＰＲＯＭの内部データ書換えはＥＥ
ＰＲＯＭ書込み装置か接続されている時だけ行われ、Ｅ
ＥＰＲＯＭ搭載装置のプログラム暴走等によるＥＥＰＲ
ＯＭ内部データの破壊を防止する事が出来る。According to the present invention, the internal data of EEPROM can be rewritten using EE.
This is done only when a PROM writing device is connected, and E
EEPR due to program runaway of EPROM equipped device, etc.
Destruction of OM internal data can be prevented.
第１図は本発明の原理構成図、第２図は実施例のブロッ
ク構成図、第３図は従来例のブロック構成図を示す。
図において、１．２１はＥＥＰＲＯＭ搭載装置、２．２
２はＥＥＰＲＯＭ書込み装置、３，２３はＥＥＰＲＯＭ
、４，７．２４．２７はＲＯＭ、５．２５はＲＡＭ、６
，２６はＣＰＵ、８は接続判定回路、９は信号送出回路
、１０．２８は差込みプラグ、１１は抵抗、１２はイン
バータ、１３はアンド、１４は地気を示す。
ＥＥＰＲＯＭ搭載装置
実施例のブロック構成図
第２図
従来例のブロック構成図
第３図FIG. 1 is a block diagram of the principle of the present invention, FIG. 2 is a block diagram of an embodiment, and FIG. 3 is a block diagram of a conventional example. In the figure, 1.21 is an EEPROM equipped device, 2.2
2 is EEPROM writing device, 3 and 23 are EEPROM
, 4, 7.24.27 is ROM, 5.25 is RAM, 6
, 26 is a CPU, 8 is a connection determination circuit, 9 is a signal sending circuit, 10.28 is a plug, 11 is a resistor, 12 is an inverter, 13 is an AND, and 14 is an earth. Figure 2: Block configuration diagram of an embodiment of an EEPROM equipped device Figure 3: Block configuration diagram of a conventional example
Claims (1)
装置において、 該ＥＥＰＲＯＭ（３）を搭載する装置（１）に、該ＥＥ
ＰＲＯＭ書込み装置（２）の接続状態を判定する接続判
定回路（８）を儲け、 該ＥＥＰＲＯＭ書込み装置（２）に、該ＥＥＰＲＯＭ搭
載装置（１）に接続時送出する信号送出回路（９）を儲
け、 該ＥＥＰＲＯＭ書込み装置（２）接続中は該書込み装置
（２）に搭載されたＲＯＭ（７）の内部データを該ＥＥ
ＰＲＯＭ（３）に転送し、 該ＥＥＰＲＯＭ書込み装置（２）未接続中は、該ＥＥＰ
ＲＯＭ搭載装置（１）のＥＥＰＲＯＭ（３）に対するＣ
ＰＵ（６）からの書込みを禁止することを特徴とするＥ
ＥＰＲＯＭプロテクト方式。[Claims] In a device equipped with a CPU, a ROM, a RAM, and an EEPROM, the device (1) equipped with the EEPROM (3) includes the EE
A connection determination circuit (8) is provided to determine the connection state of the PROM writing device (2), and a signal sending circuit (9) is provided to the EEPROM writing device (2) to send out a signal when connected to the EEPROM loading device (1). , While the EEPROM writing device (2) is connected, the internal data of the ROM (7) mounted on the writing device (2) is transferred to the EEPROM writing device (2).
When the EEPROM writing device (2) is not connected, the EEPROM is transferred to the EEPROM (3).
C for EEPROM (3) of ROM mounted device (1)
E characterized by prohibiting writing from PU (6)
EPROM protection method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2227135A JPH04107756A (en) | 1990-08-29 | 1990-08-29 | Eeprom protecting system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2227135A JPH04107756A (en) | 1990-08-29 | 1990-08-29 | Eeprom protecting system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04107756A true JPH04107756A (en) | 1992-04-09 |
Family
ID=16856032
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2227135A Pending JPH04107756A (en) | 1990-08-29 | 1990-08-29 | Eeprom protecting system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04107756A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001188686A (en) * | 1999-10-22 | 2001-07-10 | Sony Corp | Data rewriting device, control method, and recording medium |
-
1990
- 1990-08-29 JP JP2227135A patent/JPH04107756A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001188686A (en) * | 1999-10-22 | 2001-07-10 | Sony Corp | Data rewriting device, control method, and recording medium |
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