JPH04105336A - Connection structure of tab type semiconductor device and the like - Google Patents

Connection structure of tab type semiconductor device and the like

Info

Publication number
JPH04105336A
JPH04105336A JP22118990A JP22118990A JPH04105336A JP H04105336 A JPH04105336 A JP H04105336A JP 22118990 A JP22118990 A JP 22118990A JP 22118990 A JP22118990 A JP 22118990A JP H04105336 A JPH04105336 A JP H04105336A
Authority
JP
Japan
Prior art keywords
leads
pattern
semiconductor device
width
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22118990A
Other languages
Japanese (ja)
Inventor
Mitsutoshi Nakamura
中村 充逸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP22118990A priority Critical patent/JPH04105336A/en
Publication of JPH04105336A publication Critical patent/JPH04105336A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/321Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/36Assembling printed circuits with other printed circuits
    • H05K3/361Assembling flexible printed circuits with other printed circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007Surface contacts, e.g. bumps

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To obtain a connection structure of a pattern and a lead which is free from position deviation, by forming recessed parts which have the same pitch as the leads of a TAB system semiconductor device and the like and a width larger than the lead, at the position of a substrate where a pattern is formed, and forming the pattern in the bottom parts of the recessed parts. CONSTITUTION:In connection structure wherein leads 14 of the flexible tape or a TAB type semiconductor device 11 are connected with a pattern 2 formed on a substrate 1, recessed parts 3 which have the same pitch as the leads 14 and a width (b) larger than the width (c) of the lead 14 are formed at positions of the substrate 1 where a pattern 2 is formed, and said pattern 2 is formed in the bottom parts of the recessed parts 3. For example, at positions of a glass substrate 1 where an electrode pattern 2 is formed, the recessed parts 3 wherein the depth (a) is 5-35mum and the width (b) is a little larger than the width (c) of the lead 14 are formed at the same pitch as the leads 14, and the electrode pattern 2 is formed in the bottom parts. The electrode pattern 2 and the leads 14 are position-aligned, and an anisotropic bonding film 4 is interposed between them. The leads 14 are connected with the electrode pattern 12 by applying heat and pressure to the film 12.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は、ポリイミドフィルムの如き可撓性のフィルム
に、半導体素子を搭載してフィルムに設けたインナーリ
ードと接続してなるTAB式半導体装置、あるいは上記
のフィルムにリードを設けてなるフレキシブルテープを
、基板に設けたパターンに接続するTAB式半導体装置
等の接続構造に関するものである。
[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a TAB type semiconductor device in which a semiconductor element is mounted on a flexible film such as a polyimide film and connected to an inner lead provided on the film. Alternatively, the present invention relates to a connection structure for a TAB type semiconductor device, etc., in which a flexible tape formed by providing a lead on the above-mentioned film is connected to a pattern provided on a substrate.

[従来の技術] ポリイミドフィルムの如き可撓性のフィルムに、半導体
素子を搭載してフィルムに設けたリードと接続したいわ
ゆるTAB式半導体装置は広く実用に供されている。ま
た、上記のフィルムに多数のリードを設け、その可撓性
を利用して基板間等を接続するフレキシブルテープも実
用化されている。
[Prior Art] A so-called TAB type semiconductor device, in which a semiconductor element is mounted on a flexible film such as a polyimide film and connected to leads provided on the film, is widely used in practice. In addition, flexible tapes have also been put into practical use, in which a large number of leads are provided on the above-mentioned film, and the flexibility of the tapes is utilized to connect substrates.

第3図は従来のこの種接続構造の一例を示す模式図、第
4図はその要部の拡大図である。図において、(1)は
例えば液晶パネルを構成するガラス基板で、その外縁に
は多数の電極パターン(2)が設けられている。(11
)はTAB式半導体装置で、可撓性のフィルム(12)
の中央部には半導体素子(13)が搭載され、その電極
はフィルム(12)に形成したリード(14)にそれぞ
れ接続されている。
FIG. 3 is a schematic diagram showing an example of a conventional connection structure of this type, and FIG. 4 is an enlarged view of the main part thereof. In the figure, (1) is a glass substrate constituting, for example, a liquid crystal panel, and a large number of electrode patterns (2) are provided on its outer edge. (11
) is a TAB type semiconductor device with a flexible film (12)
A semiconductor element (13) is mounted in the center of the film, and its electrodes are respectively connected to leads (14) formed on the film (12).

なお、(5)は例えばプリント基板、(15)は多数の
リード(IB)が形成され、ガラス基板(1)に設けら
れた電極パターンとプリント基板(5)に設けられた電
極パターンとを電気的に接続するフレキシプルテープで
ある。
Note that (5) is, for example, a printed circuit board, (15) is formed with a large number of leads (IB), and electrically connects the electrode pattern provided on the glass substrate (1) and the electrode pattern provided on the printed circuit board (5). It is a flexible tape that connects the

上記のようなガラス基板(1)の電極パターン(2)に
半導体装置(11)のリード(14)を接続するには、
第5図に示すようにガラス基板(1)の電極パターン(
2)に半導体装置(11)のリード(I4)を整合(位
置合せ)させて両者の間に異方性接着フィルム(4)を
介装し、フィルム(12)を加熱かつ加圧して電極パタ
ーン(2)にリード(14)を接続する。
To connect the leads (14) of the semiconductor device (11) to the electrode pattern (2) of the glass substrate (1) as described above,
As shown in Figure 5, the electrode pattern (
2), the leads (I4) of the semiconductor device (11) are aligned (positioned), an anisotropic adhesive film (4) is interposed between the two, and the film (12) is heated and pressurized to form an electrode pattern. Connect the lead (14) to (2).

ガラス基板(1)とプリント基板(5)に対するフレキ
シブルテープ(15)の接続も上記と同様にして行なわ
れる。
The flexible tape (15) is connected to the glass substrate (1) and the printed circuit board (5) in the same manner as described above.

[発明が解決しようとする課題] 上記のようなガラス基板(1)やプリント基板(5)と
TAB式半導体装置(11)又はフレキシブルテープ(
15)との接続構造においては、異方性接着フィルム(
4)で両者を接続する際、熱と圧力とによってフィルム
(12)が伸びるため、電極パターン(2)とリード(
14)との位置が整合しなくなり、第5図、第6図に示
すように両者の間に位置ずれ(α)が生じて一部の電極
パターン(2)とリード(14)との間に充分な接続面
積か得られない場合か生し、ときとしてリード(14)
が電極パターンク2)がら外れてしまい接続できなくな
ることもある。
[Problem to be solved by the invention] Glass substrate (1) or printed circuit board (5) as described above and TAB type semiconductor device (11) or flexible tape (
15), anisotropic adhesive film (
When connecting the two in step 4), the film (12) stretches due to heat and pressure, so the electrode pattern (2) and lead (
14), and as shown in Figures 5 and 6, a positional deviation (α) occurs between the two, and some of the electrode patterns (2) and leads (14) If sufficient connection area is not available, the lead may sometimes fail (14)
may come off from the electrode pattern 2), making it impossible to connect.

また、接続後においても熱によって異方性接着フィルム
(4)がゆるみ、信頼性を損うことがあった。
Furthermore, even after connection, the anisotropic adhesive film (4) may loosen due to heat, impairing reliability.

このような位置ずれ傾向は、第7図に示すように接続ピ
ッチが小さくなるほど著しがった。
As shown in FIG. 7, this tendency for positional deviation became more pronounced as the connection pitch became smaller.

本発明は、上述の課題を解決すべくなされたもので、位
置ずれを生ずるおそれのないパターンとリードとの接続
構造を得ることを目的としたものである。
The present invention was made to solve the above-mentioned problems, and an object of the present invention is to obtain a connection structure between a pattern and a lead without the risk of positional deviation.

[課題を解決するための手段] 本発明に係るTAB式半導体装置の接続構造は、基板の
パターンを形成する位置に、TAB式半導体装置等のリ
ードと同じピッチでがっこのリードの幅より広い幅の凹
部を設け、この凹部の底部にパターンを形成したもので
ある。
[Means for Solving the Problems] The connection structure of a TAB type semiconductor device according to the present invention has a connection structure in which a pattern on a substrate is formed with the same pitch as the leads of a TAB type semiconductor device, etc., but wider than the width of the bracket leads. A concave portion with a certain width is provided, and a pattern is formed on the bottom of the concave portion.

[作 用コ 基板のパターンにTAB式半導体装置等のり一部を位置
合せしてリードを基板の凹部内にそれぞれ嵌入し、接合
材料によりパターンとリードを接続する。
[Operation] Align a portion of the adhesive such as a TAB type semiconductor device with the pattern of the substrate, fit the leads into the recesses of the substrate, and connect the pattern and the leads with a bonding material.

[実施例] 第1図は本発明実施例を模式的に示した断面図、第2図
はその一部拡大図である。なお、第5図で説明した従来
技術と同じ部分に同じ符号を付し、説明を省略する。(
3)はガラス基板(1)の電極パターン(2)を形成す
る位置に、リード(14)と同じピッチでエツチング等
により形成した凹部で、実施例ではその深さ(a)を5
〜35−1幅(b)をリード(14)の幅(e)の1.
2〜1.5倍にした。この凹部(3)の底部には蒸着、
スパッタ等により電極パターン(2)が形成されている
[Example] FIG. 1 is a sectional view schematically showing an example of the present invention, and FIG. 2 is a partially enlarged view thereof. Note that the same parts as in the prior art explained in FIG. 5 are given the same reference numerals, and the explanation will be omitted. (
3) is a recess formed by etching or the like at the same pitch as the leads (14) at the position where the electrode pattern (2) is to be formed on the glass substrate (1), and in the example, the depth (a) is 5.
~35-1 width (b) is 1.5-1 of the width (e) of the lead (14).
It was increased by 2 to 1.5 times. At the bottom of this recess (3), vapor deposition,
An electrode pattern (2) is formed by sputtering or the like.

上記のような凹部(3)内に電極パターン(2)を設け
たガラス基板(1)にTAB式半導体装置(II)を接
続するには、先ず、ガラス基板(1)の電極パターン(
2)とTAB式半導体装置(11)のリード(14)と
の位置合せを行なったのち、ガラス基板(1)の凹部(
3)内に例えば異方性接着フィルム(4)を挿入する。
In order to connect the TAB type semiconductor device (II) to the glass substrate (1) having the electrode pattern (2) provided in the recess (3) as described above, first, the electrode pattern (2) of the glass substrate (1) is connected.
2) and the leads (14) of the TAB type semiconductor device (11), then align the concave part (1) of the glass substrate (1).
3) For example, an anisotropic adhesive film (4) is inserted inside.

ついで、TAB式半導体装置(11)を下降させてその
リード(14)をそれぞれ四部(3)内に嵌入し、フィ
ルム(12)を加熱かつ加圧して電極パターン(2)に
リード(14)を接続する。
Next, the TAB semiconductor device (11) is lowered and its leads (14) are fitted into the four parts (3), and the film (12) is heated and pressurized to attach the leads (14) to the electrode pattern (2). Connecting.

この場合、四部(3〉の幅(b)はリード(14)の幅
(C)の1.2〜1.5倍程度に形成されているので、
電極パターン(2)とリード(14)との位置合せは多
少ラフであっても両者を確実に接続できるため、位置合
せがきわめて容易になる。また、接続の際、加熱、加圧
によりフィルム(12)が多少伸びても、上述のように
凹部(3) 、したがって電極パターン(2)の幅(b
)をリード(14)の幅(c)より大きく形成して裕度
をもたせであるため充分にカバーでき、接続不良を生じ
るようなことはない。
In this case, the width (b) of the fourth part (3) is approximately 1.2 to 1.5 times the width (C) of the lead (14), so
Even if the alignment between the electrode pattern (2) and the lead (14) is somewhat rough, the two can be reliably connected, making alignment extremely easy. Furthermore, even if the film (12) is slightly stretched due to heating and pressure during connection, the recess (3) and therefore the width (b) of the electrode pattern (2) will be
) is formed to be larger than the width (c) of the lead (14) to provide a margin, so that it can be sufficiently covered and no connection failure will occur.

さらに、リード(14)の厚さ方向の大部分が凹部(3
)内に収容されるため、ガラス基板(1)とフィルム(
12)との間に形成される空間が少なく、したがってこ
の空間に充填される異方性接着フィルム(4)の容積も
小さい。このため、若し熱によって異方性接着フィルム
(4)がゆるんでも信頼性を損うことはない。
Furthermore, most of the lead (14) in the thickness direction has a recess (3).
), the glass substrate (1) and the film (
12), and therefore the volume of the anisotropic adhesive film (4) filled in this space is also small. Therefore, even if the anisotropic adhesive film (4) loosens due to heat, reliability will not be impaired.

TAB式半導体装置(11)又はフレキシブルテープ(
15)に設けたリード(14)と、ガラス基板(1)に
設けた電極パターン(2)の、ピッチごとの幅と間隔(
ギャップ)との関係の一例を表1に示す。
TAB type semiconductor device (11) or flexible tape (
15) and the electrode pattern (2) provided on the glass substrate (1), the width and spacing (
Table 1 shows an example of the relationship with the gap).

表1 上記表1の各種のピッチごとに、従来技術と本発明とに
よってガラス基板(1)の電極パターン(2)にTAB
式半導体装置(11)のリード(■4)を異方性接続フ
ィルム(4)を使用して接続し、その位置ずれ(α)を
調査した結果を第7図に示す。図から明らかなように、
従来技術では接続ピッチが小さくなる(ファインパター
ン)はど位置ずれ(α)が大きくなり、接続ピッチ10
0Ia+の場合は351a1(電極パターン(2)の幅
50−の70%)に達することがあり、歩留りが低かっ
た。
Table 1 For each pitch shown in Table 1 above, TAB is applied to the electrode pattern (2) of the glass substrate (1) using the conventional technology and the present invention.
The leads (4) of the semiconductor device (11) were connected using the anisotropic connection film (4), and the results of investigating the positional deviation (α) are shown in FIG. As is clear from the figure,
In the conventional technology, as the connection pitch becomes smaller (fine pattern), the positional deviation (α) becomes larger, and the connection pitch becomes 10.
In the case of 0Ia+, the width could reach 351a1 (70% of the width 50- of the electrode pattern (2)), and the yield was low.

これに対して本発明においては接続ピッチの大小にかか
わらず位置ずれは零であり、歩留り及び信頼性の高い接
続構造が得られた。
In contrast, in the present invention, the positional deviation was zero regardless of the size of the connection pitch, and a connection structure with high yield and reliability was obtained.

上記の説明では、ガラス基板(1)に凹部(3)を形成
し、この凹部(3)内に設けた電極パターン(2)に、
TAB式半導体装置(11)又はフレキシブルテープ(
I5)に設けたリード(14)を接続する場合について
述べたが、ガラス基板以外の基板にも本発明を実施する
ことができる。
In the above explanation, a recess (3) is formed in the glass substrate (1), and the electrode pattern (2) provided in the recess (3) is
TAB type semiconductor device (11) or flexible tape (
Although the case has been described in which the leads (14) provided in I5) are connected, the present invention can also be implemented on substrates other than glass substrates.

また、上記の実施例では電極パターン(2)とリード(
14)とを異方性接着フィルム(4)で接続する場合に
ついて述べたが、本発明においては、はんだ、導電性接
着剤等、各種の接合材料を使用することができる。
Furthermore, in the above embodiment, the electrode pattern (2) and the lead (
14) using an anisotropic adhesive film (4), various bonding materials such as solder and conductive adhesive can be used in the present invention.

[発明の効果] 以上の説明から明らかなように、本発明は基板のパター
ンの位置にTAB式半導体装置等のリードの幅より広い
幅の四部を設け、各四部の底部にパターンを形成してT
AB式半導体装置等のリードを接続するようにしたので
、次のような効果を得ることができる。
[Effects of the Invention] As is clear from the above description, the present invention provides four parts having a width wider than the lead width of a TAB type semiconductor device, etc. at the position of the pattern on the substrate, and forms a pattern at the bottom of each of the four parts. T
Since the leads of the AB type semiconductor device and the like are connected, the following effects can be obtained.

(1)パターンとリードとの位置合せは多少ラフでも両
者を確実に接続することにかできる。
(1) Even if the alignment between the pattern and the lead is somewhat rough, it is possible to reliably connect the two.

(2)リードをリードの幅より広い基板の凹部に嵌入し
てパターンと接続するので、加熱、加圧等によりフィル
ムが若干伸びても両者を確実に接続することができる。
(2) Since the leads are connected to the pattern by fitting into the recesses of the substrate wider than the width of the leads, the two can be reliably connected even if the film is slightly stretched due to heating, pressure, etc.

(3)リードが基板の凹部内に収容されるので基板とフ
ィルムとの間に形成される空間が少なく、シたがってこ
の空間に充填される接合材料の容積もまた小さい。この
ため熱によって接合材料がゆるんでも信頼性を損うこと
はない。
(3) Since the leads are accommodated in the recesses of the substrate, the space formed between the substrate and the film is small, and therefore the volume of the bonding material filled in this space is also small. Therefore, even if the bonding material loosens due to heat, reliability will not be compromised.

(4)これらのことから、作業が容易でその上歩留り及
び信頼性が高く、ファインパターン化のできる接続構造
を得ることができる。
(4) For these reasons, it is possible to obtain a connection structure that is easy to work with, has high yield and reliability, and can be formed into fine patterns.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明実施例を模式的に示した断面図、第2図
はその一部拡大図、第3図はガラス基板等とTAB式半
導体装置等の接続例を示す模式図、第4図はその一部拡
大図、第5図は従来のガラス基板とTAB式半導体装置
との接続例を模式的に示した断面図、第6図は電極パタ
ーンとリードとの位置ずれ状態を示す説明図、第7図は
接続ピッチと位置ずれとの関係を示す線図である。 (1)ニガラス基板、(2):電極パターン、(3):
凹部、(5)ニブリント基板、(11):TAB式半導
体装置、(12) :フィルム、(14) :リード、
(15) :フレキシブルテープ。 なお、図中同一符号は同一、又は相当部分を示す。
FIG. 1 is a cross-sectional view schematically showing an embodiment of the present invention, FIG. 2 is a partially enlarged view thereof, FIG. 3 is a schematic diagram showing an example of connection between a glass substrate, etc. and a TAB type semiconductor device, etc., and FIG. The figure is a partially enlarged view, FIG. 5 is a sectional view schematically showing an example of connection between a conventional glass substrate and a TAB type semiconductor device, and FIG. 6 is an explanation showing a state of misalignment between an electrode pattern and a lead. 7 are diagrams showing the relationship between connection pitch and positional deviation. (1) Niglass substrate, (2): Electrode pattern, (3):
recess, (5) niblint substrate, (11): TAB type semiconductor device, (12): film, (14): lead,
(15): Flexible tape. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

【特許請求の範囲】  TAB式半導体装置、フレキシブルテープ等のリード
を基板に設けたパターンに接続する接続構造において、 前記基板のパターンを形成する位置に前記リードと同じ
ピッチでかつ該リードの幅より広い幅の凹部を設け、該
凹部の底部にパターンを形成したことを特徴とするTA
B式半導体装置等の接続構造。
[Claims] In a connection structure in which leads of a TAB type semiconductor device, flexible tape, etc. are connected to a pattern provided on a substrate, the pattern is formed on the substrate at the same pitch as the leads and wider than the width of the leads. A TA characterized in that a wide recess is provided and a pattern is formed on the bottom of the recess.
Connection structure for type B semiconductor devices, etc.
JP22118990A 1990-08-24 1990-08-24 Connection structure of tab type semiconductor device and the like Pending JPH04105336A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22118990A JPH04105336A (en) 1990-08-24 1990-08-24 Connection structure of tab type semiconductor device and the like

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22118990A JPH04105336A (en) 1990-08-24 1990-08-24 Connection structure of tab type semiconductor device and the like

Publications (1)

Publication Number Publication Date
JPH04105336A true JPH04105336A (en) 1992-04-07

Family

ID=16762873

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22118990A Pending JPH04105336A (en) 1990-08-24 1990-08-24 Connection structure of tab type semiconductor device and the like

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JP (1) JPH04105336A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100496999B1 (en) * 1997-08-18 2005-09-14 엘지전자 주식회사 Structure and manvfactare method of pad electrode for plasma display panel

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100496999B1 (en) * 1997-08-18 2005-09-14 엘지전자 주식회사 Structure and manvfactare method of pad electrode for plasma display panel

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