JPH04102956A - Interruption control system - Google Patents

Abstract

PURPOSE:To prevent the generation of a time-out error by connecting plural priority order control circuits, and when interruption instructions (IRIs) having the same level are competed in plural buses, processing an IRI first received from the bus with the highest priority. CONSTITUTION:This interruption (IR) control system is provided with plural level-sorted IR signal holding/outputting circuits 2j,i (i = 0 to x) for holding and outputting IR signals correspondingly to IRIs received from respective buses 1j in respective levels. When IRIs having the same level are competed in plural buses, the level-sorted IR signal holding/outputting circuit 2p,k holding an IR signal corresponding to the IRI first received from the bus 1p is permitted to output the IR signal to an information processor 4. The system is also provided with plural level-sorted priority order control circuits 3i each of which inhibits the output of the IR signal with the same level to the circuits 2l,i (j not equal to p) connected to a bus 1j (j not equal to p) other than the bus 1p. Since IR processing is executed in the sending order of IRIs, the generation of a time-out error can be prevented.

Description

[Detailed Description of the Invention] [Summary] When there are multiple buses and there is an interrupt instruction from each bus,
Regarding an interrupt control method having an information processing device that performs interrupt processing according to the priority indicated by the level of the relevant interrupt command, if there is a conflict between interrupt commands of the same level from multiple buses, the relevant interrupt command is not sent. The purpose is to provide a reliable interrupt control method that can prevent time error 1~ errors by sequentially processing interrupts in the order in which the interrupt signals are received from each bus. A level-by-level interrupt signal retention output circuit that retains and outputs each level, and when interrupt instructions from multiple buses conflict for the same level, retains the interrupt signal corresponding to the interrupt from the bus that is received first. Enables the level-by-level interrupt signal holding output circuit to output an interrupt signal to the information processing device, and prohibits the level-by-level interrupt signal holding and output circuit of buses other than the relevant bus from outputting interrupt signals of the same level. This configuration has a priority control circuit for each level.

[Industrial application field]

The present invention relates to an interrupt control method, and in particular, to a plurality of buses,
The present invention relates to an interrupt control method including an information processing device that performs interrupt processing in accordance with the priority indicated by the level of the interrupt instruction when there is an interrupt instruction from each bus.

[Conventional technology]

Conventionally, there has been an interrupt control method as shown in FIG.

This method shows the part that performs interrupt processing in the control section of a module (a certain replaceable functional unit), and includes a plurality of (two in this example) buses lo, 1. and, when an interrupt instruction is received from each bus, an information processing device (
MPU) 64, and a level-by-level interrupt signal holding/output circuit 62J, which holds and outputs interrupt signals corresponding to interrupt instructions received from each bus 1j for each bus and level.
i=0.1, 2, ~, x).

This example works as follows.

When an interrupt command of level i is received, an interrupt signal corresponding to the interrupt command goes up, is held in each level interrupt command holding output circuit 62j, and then is sent to the information processing device (M
PU) 64.

Then, the MPU 64 reads the contents of the interrupt command representing the received interrupt signal and executes the interrupt process. Thereafter, when the MPU 64 reads the contents of the instruction, the interrupt (level) signal is dropped.

Furthermore, the module control unit is connected to two buses 1o and 11, and each bus has the same interrupt level, and as shown in the figure, the same interrupt signal (OR (using elements) to input to each side input terminal of the MPU 64. Further, the interrupt signal holding output circuit 62j, □ for each level is provided with a command reception buffer and an interrupt register.

However, if an interrupt command is received while the MPU 64 is executing other processing and the corresponding interrupt signal is raised,
The MPU 64 starts interrupt processing for the received interrupt command after the currently executed processing is completed.
If interrupt signals of the same level are coming from both buses 1° and 1□ at the same time or at different times within a predetermined time while the PU 64 is executing another process, the MPU 64 determines which process to execute first. Therefore, the interrupt process is executed in response to an interrupt instruction from the bus side that happens to be selected at that time, or from the bus side with a predetermined higher priority.

[Problem to be solved by the invention]

By the way, as explained above, in the conventional interrupt control method, when interrupt instructions of the same level happen to conflict, the transmission of an interrupt instruction on one bus is sent as an interrupt instruction on the other bus. Even though it was earlier than sending the interrupt instruction, it is postponed and errors such as timeout errors (when an operation is not performed within a predetermined time) occur in the module that sends the interrupt instruction. There was a problem in that there was a risk of

In view of this, the present invention provides reliability that can prevent timeout errors by sequentially processing interrupts in the order in which the interrupt instructions are sent, when interrupt instructions of the same level from multiple buses conflict. This was developed with the aim of providing a certain interrupt control method.

[Means to solve the problem]

In order to solve the above technical problems, the present invention provides a plurality of buses I with j=0.1. ~． n, and an information processing device 4 that performs interrupt processing according to the priority indicated by the level of the interrupt instruction when there is an interrupt instruction from each bus.
1. Interrupt signal holding output circuit 2, t, i; t=o, 1, 2, . ~． When interrupt commands from multiple buses compete for the same level as bus 1. The level interrupt signal holding/output circuits 2p and 2k holding the interrupt signal corresponding to the interrupt command from the bus 1p are permitted to output the interrupt signal to the information processing device 4, and the bus lj other than the bus 1p; j≠p
For each level interrupt signal holding output circuit 2j, □; j≠p, a level-by-level priority control circuit 3 for inhibiting the output of an interrupt signal of the same level is provided.

[Effect]

As shown in FIG. 1, when an interrupt command from bus 1 of the plurality of buses is received, an interrupt signal corresponding to the interrupt command is held in the level 1 interrupt command holding output circuit 2J9. , the interrupt signal will be sent to the information processing device 4.

The sent signal is input to the information processing device 4 as well as to the level-by-level priority control circuit 3□.

When an interrupt signal is input, the level-by-level priority control circuit 3i determines the level corresponding to the lotus 1p from which the interrupt command was sent, regarding the same level as the interrupt signal holding output circuit 2, 2, and 2. All interrupt signal holding output circuits for every bell other than 2j1. In this case, an instruction is given to prohibit the output of interrupt signals.

When this instruction is given, the interrupt signal holding output circuit 2J1. Even if the interrupt signal is held, it will not be output, and the earliest interrupt signal will be reliably sent to the information processing device 4, and the interrupt processing corresponding to the interrupt signal will be performed.

(Example) An interrupt control method according to an example of the present invention will be described.

In this system, as shown in FIG. 2, for convenience of explanation, a module control section sold in connection with two fixed buses 1° and 1□ will be described.

When there is an interrupt instruction from each bus, the MPU 14 as the information processing device 4 performs interrupt processing according to the priority indicated by the level of the interrupt instruction, and the interrupt obtained in response to the interrupt instruction received from each bus 1j. Level interrupt signal holding output circuit 1 that holds and outputs signals for each level
pJ, , ;1=OJ.

2, ~. When interrupt commands from multiple buses conflict with X and the same level k, the bus 1 that received it first
MP
The output of an interrupt signal to U14 is enabled, and for the same level k, buses 1. , ;j≠p, what level is the interrupt signal holding output circuit 1p. ,,□;j≠p
The output of interrupt signals is prohibited for Has1, which is received first.
Priority Control Logic
) 13 H.

Note that 1p00.1p0□ is a decoder, which decodes the received interrupt command and outputs an interrupt signal to the signal line corresponding to the corresponding level, and 15o,
. . , 15X represent OR elements for combining and inputting interrupt signals to each side input terminal of the MPU 14.

In addition, the level interrupt instruction holding output circuit 1po, o
, 1po, □, ~, 1po, X, 1p. ．． . .

1p1.1. ~, 1p1. , are command reception buffers 1p1o, respectively, as shown in the figure. , 1p1o, 1. .

~, 1p1o, X, 1p11. o, 1p11.1, ~
1p1,,X, AND element 1p2o, O+ 1p2
o, 1°~, 1p2o, X, 1p21. o, 1p2
1.1,~1p21,X and interrupt register 1p3o,
o.

1p30.1. ~． 1p3o, X, 1p3i
．． o.

It has 1p3□, □, ~, 1p3□, and X.

Further, each level priority control circuit 13o, . . .
13X, as shown in FIG. 3, negative logic elements 13io,
~, 13L, 132o, ~1328, respectively.

Furthermore, the decoders 1p0o, 1p0. , level What interrupt signal holding output circuit 1pJ, z;l=0.1゜2,
~． Each X is B I L (Bus Interfac
e Logic) 1po, 1p□. Next, the operation of the interrupt control method according to this embodiment will be explained.

As shown in FIG. 4(a), an interrupt command (command) of interrupt level X from bus 1° is sent to the decoder 1p0.
Command reception signal 11111 of the level corresponding to o
command reception buffer 1 of the corresponding level.
It is held at p1o,k.

At that time, the priority control circuit 13k outputs 11111.
The command reception signal "1°" is input to the AND element 1p2o, k, and the command reception signal "1°" is output to the interrupt register 1p3ok via the AND element 1p2o, k.

The interrupt signal "1"' is transmitted to the priority control circuit 13k.
and the OR element 15k.

At this time, as shown in FIG. 4(C), BIL1p□ excluding BIL1po corresponding to the bus 1° is transmitted through the negation element 13ik of the priority control circuit 13k.
An interrupt disabling signal ``0'' is output to the AND element 1p2t of the level interrupt signal holding output circuit 1p2x and corresponding to the same level k provided in the same level k. Therefore,
The command reception signal "1"" corresponding to the interrupt command generated from the bus 1□ corresponding to FIG. 4(d) is blocked by the interrupt prohibition signal, and the interrupt register 1p3□,
It will not be held at k. Therefore, when interrupt instructions conflict, only the earliest interrupt signal is sent to the MP
It will be sent to U14.

Thereafter, an interrupt signal is input to the MPU 14, the command is processed, and when the interrupt signal falls in FIG. 4(b), the interrupt prohibition signal shown in FIG. 4(C) falls.

Then, the command reception signal that was in the command reception buffer 1pLk of the level interrupt signal holding output circuit 1p□ corresponding to the bus 1□ is transferred to the AND element 1p21. The interrupt signal is held in the interrupt registers 1p3□ and k through b and is output as shown in the same figure (e), and at the same time, the interrupt disable signal is output to the interrupt signal holding output circuit at the level corresponding to bus 1°. The interrupt signal of the corresponding level of the bus 1° will not be output.

〔Effect of the invention〕

As explained above, by providing a priority control circuit, when interrupt instructions of the same level compete from multiple buses, the present invention prioritizes and processes only the interrupt instruction received from the bus first. I try to do something.

Therefore, it is possible to prevent the occurrence of timeout errors and provide a reliable interrupt control method.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the principle of the invention, FIG. 2 is a block diagram of an embodiment, FIG. 3 is a diagram showing a priority control circuit of the embodiment, and FIG. 4 is a timing chart of the embodiment. FIG. 5 is a block diagram according to a conventional example. 1 j; j=o, 1, 2. ~n...Bus 2□, 1
p1; i=0.1, 2. ~． X...BIL2j1
0, 1pj, ... Level interrupt signal holding output circuit 3, ... Priority control circuit for each level

Claims (1)

[Claims] When there is a plurality of buses (1_j; j=0, 1, ~, n) and an interrupt instruction from each bus, interrupt processing is performed according to the priority indicated by the level of the interrupt instruction. In an interrupt control system having an information processing device (4), a level-by-level interrupt signal holding/output circuit (2_j_,_i ;i=0,1,2,~
, x), and when interrupt instructions from multiple buses compete for the same level,
The level-by-level interrupt signal holding output circuit (2_p_,_k) holding the interrupt signal corresponding to the interrupt command from p) is permitted to output the interrupt signal to the information processing device (4), and the corresponding bus (1_p) Interrupt signal holding output circuit (2_j_,_i;j
≠p), a level-by-level priority control circuit (3_i) that prohibits the output of an interrupt signal of the same level.