JPH04101577A - Clock signal regenerating circuit - Google Patents

Abstract

PURPOSE:To stably regenerate a clock signal and a horizontal synchronizing signal from a video signal which contains noise by controlling the delay quantity of the variable delay line of a noise reduction circuit by means of a regenerative clock signal of a phase locked loop and reducing the noise with the help of the noise reduction circuit before the video signal is input to the phase locked loop. CONSTITUTION:A synchronizing signal is separated from an input video signal by a synchronizing separator circuit 1. Next, with the help of a noise reduction circuit 2, the noise in the horizontal synchronizing signal is suppressed. Here, the delay time of a variable delay line 7 is controlled so that two signals, which are obtained by frequency-dividing the output regenerative clock signal from a voltage controlled oscillator 10 in a phase lock loop 3 by means of a frequency divider 12 and are added by being input to an adder 5, will have time difference of one scanning line. Further, the delay quantity of the variable delay line 7 is also controlled in units of clock time by the regenerative clock signal. Then, a phase comparator 8, loop filter 9, the voltage controlled oscillator 10 and a frequency divider 11 compose the phase lock loop 3, and the clock signal I and the horizontal synchronizing signal, which are phase locked with a horizontal synchronizing signal are taken out.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a technology for reproducing tarock signals and horizontal synchronization signals necessary for digital signal processing of video signals.

(Summary of the Invention) The present invention relates to a clock signal reproducing circuit that reproduces from an input video signal a clock signal and a horizontal synchronizing signal that are phase-synchronized with the horizontal synchronizing frequency of the input video signal. The noise reduction circuit includes a noise reduction circuit including a delay line, and a phase lock loop circuit including a phase comparator, a loop filter, a voltage controlled oscillator, and a frequency divider, and furthermore, the delay amount of the variable delay line of the noise reduction circuit is phase locked. It is controlled by the loop circuit's regenerated clock signal.

By adopting such a configuration, even when the signal-to-noise ratio is low, the clock signal and horizontal synchronization signal can be regenerated stably.

(Prior art) Conventional technology for reproducing a clock signal and a horizontal synchronization signal from an input video signal includes a phase shifter as described in "Easy Digital Video Technology" by Japan Broadcasting Publishing Association, written by Kazumasa Enami, page 75. There is a method using a lock loop circuit. However, this circuit had the drawback of being susceptible to noise. Also,
As a synchronization signal regeneration technology, the Japan Broadcasting Publishing Association “NH
Various synchronization signal reproduction techniques are listed in "K Color TV Textbook," p. 149. However, in all of them, the clock signal and horizontal synchronization signal that are phase-synchronized with the video signal are reproduced starting from the signal with the lowest S/N ratio. There were some difficulties.

On the other hand, as for noise reduction technology, see Japan Broadcasting Publishing Association, Broadcasting Technology Volume 8, “Digital Technology in Broadcasting”, 18.
There is a noise reduction circuit published on page 3.

(Problems to be Solved by the Invention) As mentioned in the section of the prior art, the conventional clock signal regeneration circuit stabilizes the horizontal synchronization signal and the clock signal whose phase is synchronized to the horizontal synchronization frequency of the video signal containing noise. There was a problem that it could not be played back.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and to provide a clock signal that is phase-locked to the horizontal synchronization frequency of a noisy video signal and horizontal synchronization by skillfully combining conventional phase-locked loop technology and noise reduction technology. It is an object of the present invention to provide a clock signal reproducing circuit that can stably reproduce signals.

(Means for Solving the Problem) In order to achieve this object, the clock signal reproducing circuit of the present invention is a circuit that reproduces from a video signal a clock signal whose phase is synchronized with the horizontal synchronization frequency of the video signal necessary for digital signal processing. , the reproducing circuit includes a synchronization separation circuit that separates a horizontal synchronization signal of the video signal, a noise reduction circuit composed of a coefficient unit, an adder, and a variable delay line, a phase comparator, a loop filter, and a voltage control. The noise reduction circuit comprises a phase-locked loop circuit composed of an oscillator and a frequency divider, and is characterized in that the amount of delay of the variable delay line of the noise reduction circuit is controlled by a regenerated clock signal of the phase-locked loop circuit. be.

(Function) According to the reproducing circuit of the present invention, the phase-locked loop circuit section that performs the role of phase synchronization and the noise reduction circuit section that performs the role of noise reduction are skillfully combined, so that the video signal is transmitted to the phase-locked loop section. The noise is reduced in the noise reduction section before being input, and the exact amount of delay is always established by controlling the delay amount of the delay line in the noise reduction section or the recovered clock signal, increasing the efficiency of the noise reduction circuit. Therefore, it is possible to stably reproduce a clock signal and a horizontal synchronization signal whose phase is synchronized to the horizontal synchronization frequency from a video signal containing noise.

(Examples) The present invention will be described in detail below by way of examples with reference to the accompanying drawings.

FIG. 1 shows a block diagram of a non-limiting embodiment of the clock signal regeneration circuit of the present invention. A synchronization separation circuit l separates a synchronization signal from an input video signal. Noise in the horizontal synchronizing signal is suppressed using an integrating circuit, that is, a noise reducing circuit, which is composed of a thread count unit 4, an adder 5, a coefficient unit 6, and a variable delay line 7. 5. The delay time of the variable delay line 7 is calculated by dividing the output regenerated clock signal of the voltage controlled oscillator 10 of the phase-locked loop circuit 3 by the frequency divider 12 and adding the two signals at the input of the adder 5. Control is performed so that there is a one-scanning line time difference. Furthermore, at this time, the delay amount of the variable delay line 7 is also controlled in units of clock time by the reproduced clock signal to ensure its accuracy. This sets the SN of the noise reduction circuit.
The ratio improvement rate is lDAog [(1+k) / (1-k)
] CdB', where O<k<1.

Phase comparator 8, loop filter 9, voltage controlled oscillator 10
, constitute a phase-locked loop circuit using the frequency divider 11,
A clock signal and a horizontal synchronization signal that are phase-synchronized with the noise-suppressed horizontal synchronization signal are extracted.

Here, a lag filter, lag lead filter, etc. is used for this loop filter.

By the way, the coefficient k of the noise reduction circuit can be infinitely l
Is it possible to improve the S/N ratio by bringing it closer to ?It takes time from when a signal enters the input until the output signal is established. Therefore, in order to efficiently achieve the phase lock loop circuit or phase lock of the clock signal regeneration circuit of the present invention,
Is it necessary to set the lock-in time of the phase-locked loop circuit later than the time required for integration of the noise reduction circuit?

FIG. 2 shows a configuration diagram of an embodiment of the present invention when an NTSC signal is input. However, the synchronous separation circuit is omitted, and the same reference numerals are given to the same components as those shown in the first diagram. In this configuration example, the horizontal synchronization signal (f H#15.734 KH
z). The horizontal synchronizing signal passes through register Z-'21 which is delayed by one clock, and is attenuated by multiplying the signal by a coefficient (1-k) using multiplier 25. After passing through register Z-'22, the horizontal synchronizing signal is It is input to one input of the adder 5. The output of adder 5 passes through register Z-'23 and variable delay line 29087, is attenuated twice by multiplier 26, and then is input to the other input of adder 5 via register Z-'24. The output of the register Z-' 23 is a noise-suppressed horizontal synchronizing signal, which is input to one input of the phase comparator 8. In the voltage controlled oscillator 10 of the phase-locked loop circuit 3, the clock signal f is four times as large as the color subcarrier of the NTC signal. # 14.31818MH
Generate z. Frequency divider 1 divides the frequency to 1/910, inputs it to the other input of phase comparator 8, and registers Z-
A phase error is detected by comparing the phase with the output of '23. The detected phase error is used to control the output frequency of the voltage controlled oscillator 10 after passing through the loop filter 9.

On the other hand, the reproduced clock signal is further divided into L/908 by frequency divider j2.
It becomes a delay amount control signal for the variable delay line 7 and controls its delay amount. Here, for the variable delay line 7, a FIFO memory or something that can vary the amount of delay depending on the pulse period is used. A recovered clock signal output from the voltage controlled oscillator 10 is fed back and used as a clock signal for the registers Z-'21 to 24, the variable delay line 7, the frequency divider 11, and I2.

Although the embodiments of the present invention have been described above, the present invention is not limited thereto, and it is obvious that various modifications and changes can be made within the scope of the claims.

(Effects of the Invention) As described in detail above, according to the clock signal reproducing circuit of the present invention, even from a video signal containing noise, a clock signal and a horizontal synchronization signal that are phase-synchronized with the horizontal synchronization frequency of the video signal can be stably reproduced. I can do something.

[Brief explanation of drawings]

FIG. 1 shows a block diagram of an embodiment configuration according to the present invention, and FIG. 2 shows a block diagram of an embodiment configuration in the case of an input video signal or an NTSC signal. 1...Synchronization separation circuit ゛2...Noise reduction circuit 3...Phase lock loop circuit

Claims (1)

[Claims] 1. In a circuit that reproduces from a video signal a clock signal that is phase-synchronized with a horizontal synchronization frequency of the video signal necessary for digital signal processing, the regeneration circuit separates a horizontal synchronization signal of the video signal; The noise reduction circuit includes a noise reduction circuit configured with a coefficient unit, an adder, and a variable delay line, and a phase locked loop circuit configured with a phase comparator, a loop filter, a voltage controlled oscillator, and a frequency divider. A clock signal regeneration circuit characterized in that a delay amount of a variable delay line of the circuit is controlled by a regeneration clock signal of the phase-locked loop circuit.