JPH04101428A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To allow a semiconductor element to be less affected by contamination by heavy metal, etc., for increasing an yield by forming a phosphorus diffusion layer in such high density as exceeds the solid solubility limit inside a semiconductor at the specified diffusion temperature. CONSTITUTION:On an n-type silicon substrate 11, a p-type well 12, field oxide film 13, silicon oxide film 14 and n<+> type polysilicon film 15 are formed. Using the gate electrode 15 and field oxide film 13 as a mask, ions are injected to the substrate self-alignedly to form a p<+> type layer 16, an n<+> type layer 17 and source and drain regions for pM0S and nM0S. Then, a CVD oxide film 18 is formed on the whole surface. After an opening is made on the specified part of the oxide film 18, a second polysilicon film 19 is deposited on the whole surface of the device. Then, the whole body of the device is covered with an insulating film 20. After that, phosphorus is diffused from the rear surface of the substrate, for example, at 1000 deg.C for 60 minutes, to form a gettering site (a phosphorus diffusion layer) 21. In order to trap heavy metal, the device is subjected to a low-temperature treatment, for example, at 800 deg.C for 20 minutes or longer.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention provides a gettering system for removing contaminants such as heavy metals in a semiconductor device, and a method for protecting a semiconductor substrate from contamination by heavy metals. The present invention relates to a gettering barrier and a method for manufacturing the same.

(Prior art) Heavy metal contamination introduced during the manufacturing process of semiconductor devices forms centers of generation and annihilation of minority carriers, increases the leakage current of the p-n junction, and shortens the lifetime of excess carriers. This deteriorates the electrical characteristics of the semiconductor device. For example, in an MO8 type memory element, generated excess electrons or excess holes diffuse within the silicon substrate and reduce the charge accumulated in the charge storage well, and when the accumulated charge becomes less than the critical charge, the memory cell The state of is reversed from 1 to O, and the stored information is lost. In a CCD, excess carriers generated from the production/annihilation center are detected as signal charges in the same way as excess carriers caused by incident light. In this case, an abnormally strong signal (white spot) is generated and the image is disturbed. In a bipolar device, the production and annihilation center is pn
Increases junction leakage current. Furthermore, excess carriers generated in the base region are transmitted to the outside as an abnormal signal. This results in, for example, an increase in low frequency noise.

As described above, it is well known that heavy metal contamination deteriorates the electrical characteristics of devices and lowers the production yield of LSIs.

Two methods have been used to address this problem.

The first is to eliminate sources of heavy metal pollution as much as possible.

Sources of contamination include chemicals such as hydrofluoric acid, nitric acid, hydrochloric acid, hydrogen peroxide, ammonium fluoride, ammonia, and sulfuric acid, ultrapure water, dust in clean rooms, workers, resists, and fine particles generated in various microfabrication equipment. I don't have time to list them all. Technologies to improve these purity and reduce particulate contamination removal are being developed as ultra-clean technologies. However, VLSI memory cells are becoming smaller and smaller due to miniaturization. Although contamination is controlled in all steps of the VLSI manufacturing process, it is inevitable that contamination will occur in some steps. No matter how strict the process control is, there is a high chance of contamination. The second method is called gettering, which removes contaminating heavy metals from the active region of the device. For example, a ring getter method that diffuses phosphorus from the backside of the wafer at the final stage of the process is commonly used. The higher the concentration of phosphorus to diffuse, the more efficient the ring gettering is, and in order to getter heavy metals, the ring gettering is performed at 900 to 1000° C. in an oxidizing atmosphere using POCQ,3 as a source. Backsite damage, which involves intentionally adding mechanical strain to the backside of a wafer, is also commonly performed. Backsite damage adds backside distortion during wafer manufacturing. Usually, this is done by spraying 5 in 2 of fine powder onto the back surface of the wafer. This mechanical processing strain is the core of oxidation-induced stacking faults (O8F) that form the core of ultra-LSI
It occurs during the process, especially the first oxidation step, where heavy metals are gettered.

This ◯SF grows fastest in an oxidation process at about 1100°C, so backside damage is considered to be effective damage in high-temperature processes. Intrinsic gettering, in which oxygen present in the substrate is precipitated and heavy metals are incorporated therein, is also quite common. In-1 - Phosphate gettering utilizes the phenomenon that oxygen precipitation nuclei are formed by low-temperature heat treatment at 650-750°C, and oxygen is precipitated during high-temperature heat treatment at 1000-1100°C. In order to prevent the formation of precipitates in the active region of the device near the surface, high-temperature heat treatment at about 1200° C. is often performed before low-temperature heat treatment. Intrinsic gettering involves performing low-temperature heat treatment as a wafer manufacturing process.
The 100° C. high temperature process is performed as a semiconductor device manufacturing process.

In particular, even though the development of ultra-clean technologies such as cleaning the manufacturing environment of VLSI, cleaning the materials used, and reducing contamination from manufacturing equipment has progressed, there are still hundreds of steps required to complete the VLSI manufacturing process with the necessary cleanliness. It can be said that it is difficult to process it. Contamination has continued to occur with a statistically certain probability. This is because while advances in ultra-clean technology have improved the control limits of cleanliness, miniaturization of devices means that even a small amount of contamination can have a negative effect on the above-mentioned device characteristics. For this reason, some kind of gettering method has become an essential process in VLSI manufacturing. There are several problems in the gettering process of VLSI. One of them is that wafer costs increase when backside damage and intrinsic gettering are treated in the wafer manufacturing process. Further, in the case of a ring getter, a getter step is added. Both are LSI
Although this will involve an increase in costs, this is unavoidable. The next issue is gettering temperature. Backside damage requires a temperature at which O8F grows, that is, a temperature of approximately 1000° C. or higher. In intrinsic gettering, the temperature at which oxygen precipitates, that is, 90
A temperature of 0'C or higher is required. It is known that in the case of a phosphorus getter, it is difficult to sufficiently diffuse phosphorus at low temperatures due to the temperature dependence of the phosphorus diffusion coefficient. However, as the miniaturization of VLSIs progresses, the distance between each element becomes shorter, and the depth of pn junctions such as sources and drains becomes shallower. Accordingly, it is necessary to suppress the temperature as much as possible during the high-temperature treatment process of local doping regions such as junction formation of phosphorus, arsenic, boron, etc. and threshold voltage vth control, and the process temperature is 900°C or less, 800°C or less. ~8
It will be carried out at 50°C. In this case, the process cannot be performed at the optimum temperature for gettering. Another problem is the three-dimensional design of the device structure. 4
．． The memory cell structure of MDRAM and some IMDRAMs has become three-dimensional.

Furthermore, as we progress from 16 MDRAM to 256 MDRAM, increasingly complex three-dimensional structures are required. In such a structure, it is easy to see that it is extremely difficult to suck out (that is, getter) the contaminant heavy metals that have gathered in areas with large local strains to the back surface. That is, as the miniaturization of VLSIs progresses, it becomes difficult to incorporate effective gettering into the process due to lower process temperatures and three-dimensional (ie, more complex) device structures.

(Problems to be Solved by the Invention) As described above, as semiconductor devices, especially VLSIs, become smaller, effective gettering can be achieved through lower process temperatures and three-dimensional device structures. It is becoming difficult to incorporate. The present invention has been made in consideration of the above-mentioned circumstances, and is intended to remove contaminants such as heavy metals from gettering sites that exhibit an effective gettering effect and device regions in a semiconductor substrate during the element formation process. It is an object of the present invention to provide a semiconductor device with a novel configuration including a gettering barrier that protects the device from the irradiation, and a method for manufacturing the same.

[Structure of the invention]

(Means for Solving the Problems) The present invention removes contaminants containing heavy metals from an element formation region in a semiconductor substrate, and includes a diffusion layer in the semiconductor substrate that prevents the contaminants from passing through. 1. The invention is a semiconductor device characterized in that the diffusion layer is a high concentration phosphorus diffusion layer that exceeds the solid solubility limit in the semiconductor at a predetermined diffusion temperature, and the second invention provides a method for manufacturing the semiconductor device. The method is characterized by comprising a step of forming a phosphorus diffusion layer on a semiconductor substrate and a step of subjecting the phosphorus diffusion layer to a low temperature heat treatment. Further, the third invention is characterized in that the time for the low-temperature heat treatment is a time for heavy metals to diffuse within the semiconductor substrate and be sufficiently captured by the getter links 1- at the temperature of the low-temperature heat treatment.

(Function) According to the present invention, gettering sites are formed on the back surface of the semiconductor substrate at the beginning and during the element formation process,
This gettering site can absorb heavy metal contamination in the device formation region, and after its formation, the gettering site becomes a gettering barrier against external contamination during the subsequent device formation process, improving device manufacturing yield. It becomes possible to measure.

Next, the basic principle of the present invention will be explained.

First, a silicon substrate was forcibly contaminated with a metal solution to form a phosphorus diffusion layer as a gettering site, and the gettering ability of the phosphorus diffusion layer was evaluated from the recombination lifetime of minority carriers in the substrate. Forced pollution is 0.01-1.00
A silicon substrate was immersed in ppm of 0.1N HNO3 acidic Fe solution, and after spin drying, it was heated at 1000°C for 60 minutes.
I did N2 annealing. After this, 800-1000℃
Phosphorus diffusion or N2 annealing was performed in the range of
Using the (SP■) method, the diffusion length of minority carriers in the silicon substrate was measured and compared before and after gettering. Further, the amount of phosphorus diffusion was determined from the depth profile obtained by SIMS. FIG. 1 shows the Fe concentration dependence of the recombination lifetime calculated from the measurement results of minority carrier diffusion length using the SPV method, and the recombination lifetime after each subsequent treatment. F
In the sample after e-contamination, the Fe concentration is 3 x 1012-
In the range of 2×101014ato/Cm3, the recombination lifetime (τ) and the Fe concentration (N) satisfy the relationship τα], /N.

When this sample was subjected to ring gettering, it was found that the lower the gettering temperature, the longer the recombination life of the substrate. Furthermore, as a result of N2 annealing of a sample in which Fe was diffused at 1000° C. at the same temperature and time as phosphorus diffusion, the recombination lifetime in the high concentration region was longer than immediately after Fe contamination, and a tendency to saturation was observed. This saturating concentration, 6
X 10"2.2 X 10'34 X ]014at
oms/cm3 is 800.900.1000 respectively
It can be seen that this corresponds to the solid solubility limit of Fe in Si at °C. From this, it is concluded that gettering of Fe due to phosphorus diffusion occurs through two mechanisms: a decrease in Fe concentration in the substrate up to the solid solubility limit at each processing temperature, and a sucking effect by phosphorus from each level. be done.

On the other hand, the result that the amount of Fe remaining in the substrate is smaller in low-temperature phosphorus diffusion than in high-temperature phosphorus diffusion is explained by the equilibrium reaction of Fe in the getter link site consisting of the PSG layer and phosphorus diffusion layer and the silicon substrate. can. In Figure 2, 9
The ratio of the initial contaminant Fe amount ([Fe]■) to the phosphorus amount (Qp) in the substrate during 00°C phosphorus diffusion and the residual amount ([Fe]B) in the substrate after getter linking is shown. here,
Fe contamination is carried out within a range that does not exceed the solid solubility limit at 900''C.This shows that the amount of Fe in the substrate after gettering is uniquely determined by the amount of phosphorus diffused. This relationship is expressed by the following formula % Formula % The reason why the deviation occurs in the region where the amount of phosphorus diffusion is small is that the short diffusion time of Fe is not rate-limiting for the equilibrium reaction.
The figure shows the dependence of the distribution coefficient K(T) on the phosphorus diffusion temperature in the above equation. The heat treatment temperature is T ('K). When the same amount of phosphorus diffusion layer is formed, the amount of residual Fe is smaller at lower temperatures, and the gettering effect is higher at lower temperatures.

Next, after phosphorus diffusion at 1000℃, 1000 and 8
Fe of the samples heat-treated in nitrogen atmosphere at 00°C
The depth profile of is shown in Figure 4. As shown in the figure,
The Fe concentration near the substrate surface increases due to heat treatment,
It is clear that gettered Fe increased due to the low-temperature heat treatment after phosphorus diffusion formation. The depth of the substrate (horizontal axis) is based on the back surface.

]2 In this low-temperature heat treatment step, the heat treatment time must be longer than a certain time in order for the gettering effect to function effectively. At the very least, this heat treatment requires time for the heavy metal to run the shortest distance from one surface of the semiconductor substrate to the ground surface where the gettering site is located. This time depends on the heat treatment temperature; the higher the temperature, the faster the heavy metal runs through the plate. Time (1) and temperature (T)
The relationship is shown in Figure 9. The vertical axis is the low temperature heat treatment time (minutes) t
The horizontal axis represents the low temperature heat treatment temperature (° C.) T. The curve shown here shows the minimum heat treatment time corresponding to each heat treatment temperature, and shows the boundary between the optimal heat treatment time area (shaded area) and the inappropriate heat treatment time area. On this curve, Le 6006C, 70
The heat treatment times at 0°C, 800°C, 900°C, and 1000°C were approximately 104 minutes, 42 minutes, 21 minutes, 10 minutes, and 6 minutes, respectively.
It's a minute.

As mentioned above, it is necessary that the phosphorus concentration in the phosphorus diffusion layer exceeds the solid solubility limit in the semiconductor, but in the silicon semi-core, the concentration is at least about 101020ato/cm'. It is necessary that FIG. 10 shows a curve showing the solid solubility limit of phosphorus in silicon in the phosphorus diffusion layer corresponding to the low-temperature heat treatment temperature. As shown in the figure, the solid solubility limit of phosphorus increases as the heat treatment temperature increases. For example, the heat treatment temperature T is 600°C, 700°C.
The solid limits of phosphorus at C, 800°C and 900°C are approximately 9 x 1019, 0.5XIO” and 2.4, respectively.
X10", 3.4X10", 4.5X10"ato
ms/cm'', and the shaded area above this curve is the phosphorus concentration area necessary for the phosphorus diffusion layer.The temperature range in the low temperature heat treatment process is approximately 600 to 1000°C.

(Example) Example 1 FIG. 5 is a sectional view showing the manufacturing process of a C-MOS transistor according to an example of the present invention. First, as shown in Figure 5(a), it has a specific resistance of 10 Ωcm and a surface of (100
) boron ions are implanted into the n-channel MOS transistor forming portion of the n-type silicon substrate 11 at 1.5×10 13 cm −2 at an acceleration voltage of 160 KeV.

After that, heat treatment was performed at a temperature of 1190°C for 8 hours.
A p-well 12 is formed, and the substrate surface is formed with a 2MO8 region and an n
M. Separate into OS area. Next, in order to perform element isolation, as shown in FIG. 5(b), a thick field oxide film 13 of, for example, 7000 layers is selectively formed, and then a thin silicon oxide film 13 of 100 to 200 layers is formed to become a gate oxide film. ] 4 is formed. Subsequently, after forming an n+ polysilicon film 15 in which phosphorus is thermally diffused into an undoped polysilicon film that will become a gate electrode, patterning is performed using a normal photolithography method. After that, by performing ion implantation in a self-aligned manner using the gate electrode 15 and the field oxide film 13 as mask materials, a breakdown layer 16 and an n+ layer 17 are formed. As a result, pMO8 and nMOS source and drain regions are formed. Note that when ion-implanting p-type impurities into the nMOS region, the pMO3 region is
~Mask with resist. Conversely, n in the 2MO8 region
When ion-implanting type impurities, the n MOS region is masked with a photoresist. Further, arsenic is used as the n-type impurity, and boron or boron fluoride is used as the p-type impurity.

Next, as shown in FIG. 5(c), a CVD oxide film 18 is formed on the entire surface, and openings are opened in predetermined portions of this oxide film 18. Subsequently, a second polysilicon film 19 is deposited on the entire surface and patterned using ordinary photolithography.

Thereafter, the entire device is covered with an insulating film 20 of 4,000 layers. For the insulating film 20, a phosphorus glass film such as PSG or BPSG is usually used.

Thereafter, phosphorus is diffused from the substrate surface for 60 minutes at, for example, 1000° C. using POCP3 gas in an oxidizing atmosphere to form gettering silicon I to (phosphorus diffusion layer) 21. Subsequently, as a heavy metal capture step, for example, 800
℃, perform a low temperature process for 20 minutes or more.

Finally, as shown in FIG. 5(d), a contact hole is opened, a metallization process is performed, and the wiring pattern 22 is
After forming by micromachining, 450°
Heat treatment is performed at ℃ for 15 minutes. Thereafter, a passivation film 23 is deposited over the entire semiconductor in order to protect the entire semiconductor. With the above process, L consisting of CMOS+- transistors
SI is formed.

-15= The manufacturing process shown here is an example, and it goes without saying that the order of the steps, the number of steps, etc. may vary depending on the device to be manufactured.

FIG. 6 is a diagram showing the leakage current characteristics of the element fabricated according to this example and the conventional element, and the element according to the example in which low-temperature gettering was performed has a leakage current that is one order of magnitude lower than that of the conventional element. .

Embodiment 2 FIG. 7 is a cross-sectional view for explaining a second embodiment of the present invention, showing the manufacturing process of a dynamic RAM cell. First, as shown in Figure 7(a), the specific resistance is 10ΩC.
A field oxide film 3 is formed on a p-type silicon substrate 31 with a thickness of about m.
After selectively forming 0.8 C on the entire surface
A VD oxide film 33 is deposited, and using this as a mask, a phosphorus diffusion layer 21 is formed on the back surface of the substrate as a gettering site and a gettering barrier. Phosphorus diffusion is 1 for example 10
POCQ3 gas is used in an oxidizing atmosphere at 00°C for 60 minutes. Furthermore, as a subsequent low-temperature heat treatment, 80
A gettering heat treatment of 0°CCl2O or more may be applied, or a heat treatment in the subsequent cord forming step may be used.

Thereafter, the surface of the substrate is subjected to a conventional photolithography process to form a window in the capacitor formation region.

Next, as shown in FIG. 7(b), a CVD oxide film 33 is formed.
A groove 34 with a depth of approximately 3 μm and having vertical walls is formed in the region of the M○S capacitor of the dynamic RAM cell using as a mask.
form. This groove 34 is, for example, CF4. SF6.
Reactive ion etching (RIE) using a gas whose main component is CCL or the like, or a gas containing H.
Formed by law. Since the mask used in this RIE process may be etched and disappear in the case of a normal photoresist 1-, for example, SiO□/Si3N4/
It is desirable to use a SiO□ film or the like.

Next, as shown in FIG. 7(c), a CVD oxide film 33 is formed.
Remove by etching. Then, an n-type layer 35 is formed on the exposed surface of the silicon substrate 31, and thermal oxidation is performed again to form a thermal oxide film 36 that will become a capacitor insulating film. Subsequently, a first layer polycrystalline silicon film is deposited and patterned to form a capacitor electrode 37. Next, as shown in FIG. 7(d), a thermal oxide film 38 that will become a gate insulating film is formed at a position adjacent to the capacitor region, and a gate electrode 39 is formed by depositing and patterning a second layer polycrystalline silicon film. , for example by arsenic ion implantation,
An n-type layer 40, 41 serving as a train is formed. Here, it is also possible to form the capacitor electrode 37 and the gate electrode 39 from the same polycrystalline silicon.

Next, as shown in FIG. 7(e), a VD oxide film 42 of about 4,000 layers is deposited on the entire surface. The insulating film 42 has
Usually, a phosphorus glass film such as PSG or BPSG is used. After this, phosphorus is again diffused from the back surface of the substrate for 160 minutes using POCQ3 gas in an oxidizing atmosphere, for example, to form a gettering site (phosphorus diffusion layer) 21. Subsequently, a low-temperature heat treatment step at 800° C. for 20 minutes or more is performed as a heavy metal capturing step. In this two-step process, if the previously formed phosphorus diffusion layer as a gettering site remains sufficiently,
It doesn't matter if it's low temperature heat treatment.

At this point, the process at 600°C or higher is completed. After this, a metallization process is performed, a wiring pattern is formed by microfabrication, and a protective film is deposited on the entire surface.
Finish element formation.

Embodiment 3 FIG. 8 is a sectional view of a pixel portion of a CCD image sensor including a light weight conversion device which is a semiconductor device of the present invention. The semiconductor substrate consists of an n-type silicon substrate 51, in which p
- A well region 52 is formed. In this p-well region, an array of vertical CCD regions (n-layer) 53 and a photodiode are arranged.
- The array of diode regions (n layer) 61 is alternately formed. Vertical CCD area 53 and photodiode 61
and are separated by a vertical CCD channel stop (P layer) 60. Goo 1 is on top of the vertical CCD 53.
-Glue 1 to polysilicon electrodes 55 are formed with an oxide film (Sin2) 54 interposed therebetween. On top of that, an insulation film [58
A light shield layer 5 made of aluminum sandwiched between
7.59 is formed.

The high concentration phosphorus diffusion layer 21 is first formed at the initial stage of the element formation process.
After depositing a CVD silicon oxide film having a thickness of approximately 0.8 cm as a mask over the entire main surface, it is formed as a gettering site and a gettering barrier on the back surface of the substrate. Phosphorus diffusion is performed, for example, at 1000° C. for 60 minutes in an oxidizing atmosphere using POCP3 gas. Further, a subsequent low-temperature heat treatment is performed, for example, at 800° C. Cl2O or more. Then,
The process moves on to the subsequent steps of forming well regions, etc., as shown in Section 2. This diffusion layer can remove contaminants such as heavy metals from the element formation area and effectively prevent the intrusion of heavy metals, thereby eliminating the formation of minority carrier generation/annihilation centers due to heavy metals and eliminating the occurrence of white scratches. I can do it.

The width of the phosphorus diffusion layer formed on the back surface of the semiconductor substrate may be reduced by etching during the manufacturing process, but to prevent this, a protective film such as an oxide film or nitride film is applied. It is also possible to extend the life of the phosphorus diffusion layer by applying it.

Note that the manufacturing process shown here is just an example, and the order of the steps, number of steps, etc. may vary depending on the device to be manufactured.

〔Effect of the invention〕

As detailed above, according to the present invention, gettering sites and A gettering barrier can be formed, and it can contribute to improving the manufacturing yield of semiconductor devices with less contamination such as heavy metals.

[Brief Description of the Drawings] Figure 1 is an explanatory diagram showing the Fe concentration in the semiconductor substrate after Fe diffusion and the influence of diffusion or N2 annealing on the minority carrier recombination lifetime. Fe
An explanatory diagram showing the relationship between l:t and the amount of phosphorus Qp in the phosphorus diffusion layer, FIG. 3 is an explanatory diagram showing the dependence of the distribution coefficient K(T) on phosphorus diffusion temperature, and FIG. A diagram showing the depth profile of Fe in a semiconductor substrate according to the method, FIG. 5(a)
-(b) are cross-sectional views of the manufacturing process of the C-MOS transistor shown in Example 1 of the present invention, FIG. 6 is a leakage current-voltage characteristic diagram of the present invention and the conventional example, and FIGS. 7(a)-( e) is a cross-sectional view of the manufacturing process of the dynamic RAM shown in Example 2, FIG. 8 is a cross-sectional view of the pixel portion of the CCD image sensor shown in Example 3, and FIG. 9 is a cross-sectional view of the manufacturing process of the dynamic RAM shown in Example 3.
FIG. 10 is an explanatory diagram showing the dependence of the phosphorus amount QP of the phosphorus diffusion layer on the heat treatment temperature T. 11, 31.5 silicon semiconductor substrate, 1.2.52.
・P-well, 13, 32...Field oxide film, 1.4.38.54・Gate oxide film, 15, 39.55...Gate electrode, 16...P middle layer, 1
．． 7.40.4]・n middle layer, 18, 42.56...CVD oxide film, 19...polysilicon film, 20...insulating film, 21 phosphorous diffusion layer,
34 Groove, 35-n-layer, 36. Capacitor insulating film, 37. Capacitor electrode,
53. Vertical CCD area (n-layer), 57, 59... Light shield layer, 58... Insulating layer, 6
0. Channel stop (p+ layer), 61 photodiode region (n- layer).

Claims (3)

[Claims] (1) A semiconductor substrate includes a diffusion layer that removes contaminants containing heavy metals from an element formation region and prevents the contaminants from passing through the semiconductor substrate, and the diffusion layer A semiconductor device characterized by a high concentration phosphorus diffusion layer exceeding the solid solubility limit in the semiconductor device. (2) forming a phosphorus diffusion layer with a high concentration exceeding the solid solubility limit in the semiconductor at a predetermined diffusion temperature on the semiconductor substrate;
A method for manufacturing a semiconductor device, comprising the step of subjecting the phosphorus diffusion layer to low-temperature heat treatment. (3) The semiconductor device according to claim 2, wherein the time for the low-temperature heat treatment is a time for heavy metals to diffuse through the semiconductor substrate and be sufficiently captured at gettering sites at the temperature of the low-temperature heat treatment. manufacturing method.