JPH05136153A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To obtain a semiconductor device and its manufacturing method wherein gettering is enabled without deteriorating element characteristics. CONSTITUTION:A poly-silicon film 2a doped with phosphorus wherein phosphorus concentration is about 10<20>atoms/cm<3> or higher and the film thickness is about 400nm is deposited on the rear of silicon substrate 1b by a CVD method using SiH4 and PH3 gas, and sequentially low temperature heat treatment is performed, thereby segregating contaminants in an element region into the poly-silicon film 2a doped with phosphorus.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a step of removing contaminants such as heavy metals from element formation regions.

[0002]

2. Description of the Related Art Contaminants, such as heavy metals such as iron and copper, that enter during the manufacturing process of semiconductor devices are deposited as a solid solution or a compound at lattice positions or interstitial positions in Si.
As a result, the generation and extinction centers of minority carriers are formed, the leak current of the pn junction is increased, the excess carrier life is shortened, and the electrical characteristics of the semiconductor device are deteriorated.

For example, in a MOS type memory device,
Since the generated excess electrons or excess holes diffuse in the silicon substrate, the charge stored in the charge storage cell decreases,
As a result, when the accumulated charge falls below the critical charge, the state of the memory cell is inverted from 1 to 0, and the accumulated information is lost.

Further, in the CCD, excess carriers generated from the generation / disappearance center are detected as signal charges in the same manner as excess carriers due to incident light. As a result, the excessive carriers generated from the generation and extinction center become an abnormally strong signal (white defect), and the image quality deteriorates.

In addition, in the bipolar element, the generation and extinction center increases the leak current of the pn junction. In addition, the excess carriers generated in the base region are transmitted to the outside as an abnormal signal, which causes inconveniences such as an increase in low frequency noise. In this way, heavy metal contamination causes deterioration of the electrical characteristics of the device, and thus reduces the production yield of LSI. Conventionally, two measures have been taken against such pollutants.

One is to eliminate pollution sources as much as possible.
Examples of pollution sources include chemicals such as hydrofluoric acid, nitric acid, hydrochloric acid, hydrogen peroxide, ammonium fluoride, and sulfuric acid, ultrapure water, dust in clean rooms, workers, resists, and fine particles generated in various types of microfabrication equipment. I have no time to enumerate. A technique for improving these purities and reducing particulate contamination is being developed as an ultra-cleaning technique.

However, even if development of ultra-clean technology such as VLSI manufacturing environment, cleaning of used materials and reduction of contamination from manufacturing equipment is advanced, hundreds of VLSI manufacturing processes can be completed with required cleanliness. It is difficult to manage. Contamination has continued to occur with a certain probability statistically. As described above, although pollutants are controlled in all the steps of the VLSI manufacturing process, it is highly likely that the pollutants will be contaminated as the number of manufacturing steps increases, and it is inevitable that contamination will occur in some steps. That is not the case. The other is to remove contaminants such as heavy metals from the active region of the device, that is, gettering. The gettering includes ring gettering, wafer backside damage gettering, intrinsic gettering, and the like.

In the ring gettering, phosphorus is diffused from the back surface of the wafer at the final stage of the process, and the contaminated heavy metal is segregated in the phosphorus diffusion layer to remove the contaminated heavy metal from the active region of the device. To perform ring gettering, for example, P
Using OCl ₃ as the source gas for phosphorus, the wafer was
Exposing to an oxidizing atmosphere at a temperature of ℃ to 1000 ℃. As for the gettering, the higher the phosphorus concentration, the better the gettering efficiency.

In the wafer backside damage gettering, mechanical strain is intentionally formed on the backside of the wafer. As a result, using this mechanical strain as a nucleus, an oxidation-induced stacking fault occurs in the VLSI process, especially in the first oxidation process, and heavy metals segregate there. The mechanical strain can be formed, for example, by spraying SiO ₂ fine powder on the back surface of the wafer. Since the oxidation-induced stacking fault grows fastest in the oxidation step at about 1100 ° C.,
This gettering is said to be an effective method especially in a high temperature process.

In intrinsic gettering, 65
After forming oxygen precipitation nuclei by low temperature heat treatment at 0 ° C. to 750 ° C., oxygen is precipitated by high temperature heat treatment at 1000 ° C. to 1100 ° C., and heavy metals are incorporated into this oxygen. Further, in order to prevent the formation of precipitates in the active region of the element near the surface, high temperature heat treatment at about 1200 ° C. is often performed before low temperature heat treatment. Usually, the low temperature heat treatment is performed in the wafer manufacturing process, and the high temperature heat treatment is performed in the VLSI manufacturing process. However, the gettering has the following problems.

That is, there is a problem that the wafer cost is increased in the case of performing the wafer backside damaging gettering or intrinsic gettering in the wafer manufacturing process. In addition, since the gettering step is added to the ring gettering, the cost also increases in this case. Also,
There was also a problem with the heat treatment temperature.

That is, as miniaturization of VLSI progresses,
Since the distance between the respective elements becomes short, local doping for forming a pn junction of phosphorus, arsenic, boron or the like and for controlling V _TH is 900 ° C. or lower, for example, 800 to 85.
It is necessary to perform a low temperature heat treatment at about 0 ° C. However, as described above, in the wafer backside damaging gettering,
A high temperature heat treatment of about 1000 ° C. or higher is required for the growth of oxidation-induced stacking faults, and intrinsic gettering requires a high temperature heat treatment of about 900 ° C. or higher for the precipitation of oxygen. Even in the ring gettering, it was difficult to sufficiently diffuse phosphorus at low temperature because of the temperature dependence of the diffusion coefficient of phosphorus. Therefore, there is a problem that the gettering must be performed at a temperature lower than the optimum temperature and the contaminants cannot be sufficiently removed.

[0013]

As described above, even if the development of ultra-clean technology advances, element characteristics are deteriorated even with a smaller amount of contamination due to the miniaturization of the element. It is an essential process for manufacturing. However, the gettering in the conventional VLSI has problems in terms of cost and heat treatment temperature.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor device having a structure capable of sufficiently removing contaminants even by low temperature heat treatment, and a method for manufacturing the same. It is in.

[0015]

In order to achieve the above-mentioned object, a semiconductor device of the present invention comprises a semiconductor substrate having an element formed on the front surface thereof, and a heavy metal formed on the back surface of the substrate from the area where the element is formed. And a silicon film containing phosphorus that removes contaminants containing, and the phosphorus concentration of the silicon film exceeds the solid solubility limit of the silicon film at a predetermined temperature.

The semiconductor device manufacturing method of the present invention is
A method of removing contaminants containing heavy metals from an element formation region of a semiconductor substrate, the method comprising providing a silicon film containing phosphorus on the back surface of the substrate, and the phosphorus concentration of the silicon film exceeds a solid solubility limit of the silicon film. As described above, the heat treatment is performed at a predetermined constant temperature.

The silicon film may be plural in number. For example, the first silicon film containing phosphorus may be formed under the element, and then the second silicon film containing phosphorus may be formed via a non-doped silicon film or a silicon substrate. Further, it is desirable that the silicon film containing phosphorus, which is in contact with the outside, such as the second silicon film, be covered with a protective film such as an oxide film or a nitride film.

[0018]

[Function] Phosphorus has a higher ability to absorb contaminants such as heavy metals at lower temperatures. Further, by using the CVD method or the like, a high-concentration phosphorus-doped silicon film can be formed on the back surface of the substrate at a low temperature. That is, according to the present invention, since this silicon film is formed in a low temperature process, contaminants such as heavy metals are segregated in the silicon film in this process, and efficient gettering is performed. Further, even after the silicon film is formed,
Efficient gettering is performed during the low temperature heat treatment that accompanies the subsequent element formation.

Further, a silicon film containing the first and second phosphorus is formed on both surfaces of the non-doped silicon film or the silicon substrate, and another non-doped silicon substrate is bonded onto the first silicon film. In the case of forming a non-doped silicon film or the like, the second silicon film collects external contaminants, so that it is possible to prevent deterioration of the contaminant removing ability of the first silicon film.

Further, by covering the silicon film in contact with the outside with a protective film, it is possible to avoid thinning of the silicon film due to various treatments during the manufacturing process, and it is possible to prevent deterioration of the contaminant removal capability.

[0021]

Embodiments will be described below with reference to the drawings. 1A to 1D are sectional views of a semiconductor device in the manufacturing process according to the first embodiment of the present invention. This utilizes the bonded wafer method.

First, as shown in FIG. 1A, the specific resistance is 1
N-type silicon substrate 1 with 0 Ωcm and (100) surface
For example, a phosphorus concentration of 10 ²⁰ (atom / cm ²⁾ is obtained by a CVD method using SiH ₄ and PH ₃ gas. )that's all,
Phosphorus-doped polysilicon film 2 having a thickness of about 500 nm
a and 2b are formed. Here, the reaction temperature is 850 ° C., the reaction time is 150 minutes, the pressure is 0.6 Torr, the SiH ₄ flow rate is 800 sccm, the N ₂ flow rate is 850 sccm, and the PH is
₃ is diluted with He to 1% and diluted gas is 150s
It was flushed with ccm. Hereinafter, the phosphorus-doped polysilicon film 2a is referred to as a gettering site 2a, and the phosphorus-doped polysilicon film 2b is referred to as a gettering barrier 2b.

Next, as shown in FIG. 1B, the back surface of the silicon substrate 1b of the same standard as the silicon substrate 1a is attached to the front surface of the gettering site 2a. Then, a desired element is formed on the surface of the silicon substrate 1b.

According to this method, contaminants such as heavy metals mixed in the silicon substrate 1b during the element formation process are taken into the gettering site 2a, so that contamination of the element active region can be prevented. Further, the gettering barrier 2b is
The contaminants that enter from the back surface of the substrate 1a are prevented from diffusing into the element formation region. In this way, in this embodiment, the element formation region can be prevented from being contaminated, and the manufacturing yield can be improved.

As will be described later, the gettering site 2a and the gettering barrier 2b have a higher heavy metal removing ability (gettering ability) when the low temperature heat treatment is performed. There is no problem such as the change in size.

Further, since a new step for the low temperature heat treatment is not required, there is no problem that the number of steps is increased and the cost is increased. This is because the heat treatment for forming the element plays the role of the low temperature heat treatment.

Furthermore, conventional gettering, for example,
In the ring gettering, the contaminants were removed at the final stage of the process, but this embodiment has an advantage that the contaminants can be removed from the first step of forming the device. The silicon substrates 1a and 1b above and below the gettering site 2a may be changed depending on the element structure.

The inventors of the present invention used a metal solution on a silicon substrate to forcibly contaminate it to form a lind-polysilicon film functioning as a gettering site. It was evaluated from the recombination lifetime of minority carriers.

Specifically, the Fe concentration is 0.01 to 100.
The silicon substrate was immersed in 0.1 N HNO ₃ acidic Fe solution at ppm to perform forced contamination, and subsequently, spin drying was followed by N ₂ annealing at 1000 ° C. for 60 minutes, under the same conditions as in the above embodiment. A phosphorus-doped polysilicon film is formed on the back surface of the substrate to perform N ₂ annealing, or only N ₂ annealing is performed. After each of these treatments, the surface of the silicon substrate is treated with a fluorinated nitric acid solution to about 40 μm. Etched. And Surface Photovol
The diffusion length of the minority carriers in the silicon substrate was measured using the target (SPV) method, and the recombination lifetime of the minority carriers was obtained from the measurement result. The phosphorus concentration is SIMS
It was calculated from the depth profile obtained by the method.

FIG. 2 is a characteristic diagram showing the relationship between the Fe concentration and the recombination life obtained as described above. It can be seen that the recombination lifetime and the Fe concentration satisfy a linear relationship. When a Lind-polysilicon film is formed, N ₂
It can be seen that the lower the gettering temperature due to annealing, the longer the recombination life of the substrate. Further, instead of using the phosphorus-doped polysilicon film, when N ₂ annealing is performed at the same temperature and time as in this case, the recombination life becomes shorter than that of the phosphorus-doped polysilicon film, and the recombination life is saturated. The tendency to do was observed. Anneal temperature is 8
The saturation concentrations of Fe at 00 ° C., 900 ° C., and 1000 ° C. are 6 × 10 ¹² , 2 × 10 ¹³ , and 4 × 10 ¹⁴ ato, respectively.
ms / cm ³ Is. This is 800 ℃, 90
It was found that this corresponds to the solid solution limit of Fe in Si at 0 ° C and 1000 ° C.

From the above, the gettering of Fe by the phosphorus-doped polysilicon film reduces the Fe concentration in the silicon substrate up to the solid solution limit at each processing temperature and the absorption effect of phosphorus from each level. It is thought to be caused by two mechanisms.

On the other hand, the fact that the amount of Fe remaining in the silicon substrate is smaller when the gettering temperature is lower than the high temperature when the get-doped polysilicon film is used is low. This can be explained from the equilibrium reaction between gettering sites in the polysilicon film and Fe on the silicon substrate.

FIG. 3 shows 800 ° C., 900 ° C., 1000 ° C.
At the gettering temperature at the gettering temperature, the amount of phosphorus in the phosphorus-doped polysilicon film ([P]) and the amount of gettered Fe ([[Fe] _B ) in the silicon substrate after gettering ([Fe] _B ) It is a characteristic view showing a relation with the ratio of Fe] _G ) (gettering efficiency). Here, Fe contamination is performed within a range not exceeding the solid solubility limit of Fe at 800 ° C. Further, the phosphorus amount ([P]) is the number of atoms per unit area, and in order to obtain the number of atoms per unit volume, this is calculated as the film thickness of the phosphorus-doped polysilicon film (in this case, 5).
00 nm). From this figure, it is found that [Fe] _B is uniquely determined with respect to the amount of phosphorus, and this relationship can be expressed by the following equation. [Fe] _B / [Fe] _G = K (T) * [P] ^1/2 (1) where K (T) is a distribution coefficient.

FIG. 4 is a characteristic diagram showing the relationship between the distribution coefficient K (T) and the gettering temperature T. K (T) is 4.5 × 10 ⁻¹⁸ using the Boltzmann constant k exp (2.4
/ KT). It can be seen from this figure that when the P amount is the same, the residual Fe amount decreases as the temperature decreases. That is, the gettering effect is higher at lower temperatures.

In order to effectively perform gettering in a low temperature heat treatment, the heat treatment time must be a certain time or longer. That is, this time must be greater than or equal to the time required for the heavy metal to travel the shortest path from one surface of the substrate to the other surface with gettering sites.

The above heat treatment time depends on the heat treatment temperature, and the higher the temperature, the higher the speed at which the heavy metal runs in the substrate. FIG. 5 shows the relationship between the heat treatment time and the heat treatment temperature. In the figure, the vertical axis represents the square root of the heat treatment time t (minutes), and the horizontal axis represents the heat treatment temperature T (° C). The curve shown here indicates the minimum heat treatment time corresponding to each heat treatment temperature, and indicates the boundary between the region of optimum heat treatment time (hatched portion) and the region unsuitable for heat treatment time.
600 ℃, 700 ℃, 800 ℃, 9 on this curve
The heat treatment time at 00 ° C and 1000 ° C is about 104, respectively.
Minutes, 42 minutes, 21 minutes, 10 minutes, 6 minutes.

To obtain high gettering ability,
The phosphorus concentration of the phosphorus-doped polysilicon film needs to exceed the solid solubility limit, and is at least about 10 ²⁰ (atom / cm ^3). )
It is necessary to be above. FIG. 6 is a characteristic diagram showing the relationship between the heat treatment temperature and the solid solubility limit of phosphorus in silicon. As can be seen from this figure, the solid solubility limit of phosphorus increases as the heat treatment temperature increases. For example, when the heat treatment temperature T is 600 ° C., 700 ° C., 800 ° C., 900 ° C., the solid solubility limits of phosphorus are about 9 × 10 ¹⁹ and 2.4 × 1, respectively.
0 ²⁰ , 3.4 × 10 ²⁰ , 4.5 × 10 ²⁰ (atoms /
cm ³ ), And the shaded area above this curve is the Lind-
It is a concentration region above the solid solubility limit necessary for the polysilicon film. FIG. 7 is a sectional view of a manufacturing process of a CMOS transistor according to the second embodiment of the present invention.

First, as shown in FIG. 7A, the specific resistance is 1
N-type silicon substrate 11 with 0 Ωcm and (100) surface
About 1.5 × 10 ¹³ cm ⁻² of boron is ion-implanted at an acceleration voltage of 160 keV in the n-channel MOS transistor forming portion of the above. After that, heat treatment is performed at 1190 ° C. for 8 hours to form the p well 12, and the surface of the substrate 1 is separated into a pMOS region and an nMOS region.

Next, as shown in FIG. 7B, in order to perform element isolation, for example, after a thick field oxide film 13 having a thickness of about 700 nm is selectively formed, a thickness 10 to be a gate oxide film is formed. A thin oxide film 14 of about 20 nm is formed. Then, phosphorus was thermally diffused into the undoped polysilicon film to be the gate electrode, n ⁺ After the polysilicon film 15 is formed, it is patterned into a gate electrode shape by using ordinary photolithography.

Then, ions are implanted using the gate electrode 15 and the field oxide film 13 as a mask, and p ^{+ is} self-aligned.
Layer 16, n ⁺ Form layer 17. This allows the p-type MO
Sources of S-transistors and n-type MOS transistors,
A drain region is formed. When p-type impurities are ion-implanted into the n-type MOS transistor region, the p-type MOS transistor region is masked with photoresist. On the contrary, when ion-implanting the n-type impurity into the p-type MOS transistor region, the n-type MOS transistor region is masked with photoresist. Arsenic is used as the n-type impurity, and boron or boron fluoride is used as the p-type impurity.

Next, as shown in FIG. 7 (c), CVD is performed on the entire surface.
An oxide film 18 is deposited, an opening is formed in a predetermined portion of the oxide film 18, and then a polysilicon film 19 is deposited on the entire surface. Then, this polysilicon film 19 is patterned into an electrode shape by using photolithography, and then the entire surface is covered with an insulating film 20 having a thickness of about 400 nm, such as PSG or B.
Cover with a phosphorus glass film such as PSG.

Then, for example, by a CVD method using SiH ₄ and PH ₃ gas, the phosphorus concentration serving as a gettering site is 10 ²⁰ atoms / cm ^3. Above, the film thickness is 500
The phosphorus-doped polysilicon film 21 having a thickness of about nm is formed on the substrate 11
Formed on the back surface of. The film forming conditions are similar to those of the first embodiment. It should be noted that the step of removing contaminants such as heavy metals is sufficient in most cases within the formation time of the phosphorus-doped polysilicon film 21, but if it is insufficient for diffusion of contaminants, it is continued. A low temperature heat treatment step at 800 ° C. or lower is added.

Then, as shown in FIG. 7D, after removing the unnecessary polysilicon film on the surface of the substrate, a contact hole is formed on the insulating film 20, and subsequently a metallization process is carried out to form a wiring by fine processing. After forming the pattern 22, heat treatment is performed at 450 ° C. for 15 minutes in an N ₂ atmosphere. Finally, in order to protect the entire device, a passivation film 23 is deposited all over to complete the CMOS transistor.

FIG. 8 is a characteristic diagram showing the relation between the leak current and the voltage. In the figure, the curve a shows the relation between the leak current and the voltage of the device manufactured by the method of this embodiment. , Curve b
Is that of the conventional method. From this figure, the leakage current of the element of this example subjected to low temperature gettering is
It can be seen that the leakage current is smaller by one digit than that of the conventional device. Thus, according to this embodiment, by forming the gettering site 21 during the element forming process, a CMOS transistor with a small leak current can be obtained.

As in the first embodiment, the CMOS transistor may be formed after the silicon substrate on which the gettering site and the gettering barrier are formed and the silicon substrate 11 are bonded together. Further, a protective film made of an oxide film or a nitride film may be formed on the surface of the gettering barrier. 9 and 10 are sectional views showing the steps of manufacturing a DRAM cell according to the third embodiment of the present invention.

First, as shown in FIG. 9A, after a field oxide film 32 is selectively formed on a p-type silicon substrate 31 having a specific resistance of about 10 Ωcm, a thickness of about 0.8 μm is formed on the entire surface.
m CVD oxide film 33 is deposited. Then, for example, S
The substrate 31 is formed by the CVD method using iH ₄ and PH ₃ gas.
Concentration of phosphorus, which is a gettering site, is 10 ²⁰ a on the back surface of
toms / cm ³ As described above, the phosphorus-doped polysilicon film 21 having a film thickness of about 500 nm is formed. First film forming condition
The material is the same as that of the example. The pollutant removal step is performed by heat treatment in the subsequent element forming step. In addition,
In order to prevent thinning of the phosphorus-doped polysilicon film 21 that occurs during this heat treatment, the phosphorus-doped polysilicon film 2
It is desirable to form an insulating film such as a SiO ₂ film or a SiN film, which serves as a protective film, on the surface of 1. Next, a window is formed in the capacitor formation region on the surface of the substrate 31 by using photolithography.

Next, as shown in FIG. 9B, the substrate 31 is etched using the CVD oxide film 33 as a mask, and DRA is performed.
A groove 34 having a vertical wall and having a depth of about 3 μm is formed in a region to be the MOS capacitor of the M cell. Etching of the substrate 31, for example, performed by CF _4, SF _6, CC1 reactive ion etching (RIE) method using a gas or this H enters the gas mainly composed of such _4. In addition, RI
In the case of etching by the E method, if a normal photoresist is used as a mask, it may itself be etched and disappear. Therefore, for example, SiO ₂ / Si ₃ N _{4 is used.}
It is desirable to use a laminated insulating film such as a / SiO ₂ film.

Next, as shown in FIG. 9C, after the CVD oxide film 33 is removed by etching, the exposed silicon substrate 3 is removed.
N ^{− on} the surface of 1 A layer 35 is formed, and then thermal oxidation is performed to form a thermal oxide film 36 to be a capacitor insulating film. Then, a polycrystalline silicon film is deposited and patterned to form a capacitor electrode 37.

Next, as shown in FIG. 10A, a thermal oxide film 3 to be a gate insulating film is formed at a position adjacent to the capacitor region.
8. After sequentially forming a gate electrode 39 made of a polycrystalline silicon film, for example, arsenic is ion-implanted to form an n ⁺ source and drain. The layers 40 and 41 are formed. Here, the capacitor electrode 37 and the gate electrode 39 may be formed of the same polycrystalline silicon film.

Next, as shown in FIG. 10B, the insulating film 42 having a thickness of about 400 nm, for example, the entire surface is formed by the CVD method.
A phosphorus glass film such as PSG or BPSG is deposited. After this, again, for example, CVD using SiH ₄ and PH ₃ gas is performed.
By the method, the concentration of phosphorus, which is a gettering site, is 10
²⁰ atoms / cm ³ As described above, the phosphorus-doped polysilicon film having a thickness of about 400 nm is formed on the back surface of the substrate 31. Subsequently, as a heavy metal removing step, for example, 800 ° C.
Then, a low temperature heat treatment step for 20 minutes or more is performed. If the previously formed phosphorus-doped polysilicon film 21 as the gettering site remains sufficiently, it is not necessary to form the phosphorus-doped polysilicon film again, and only the low temperature heat treatment may be performed. Here, the process of 600 ° C. or higher is completed. Finally, a metallization process is performed to form a wiring pattern by fine processing, and then a protective film is deposited on the entire surface to complete the DRAM cell. Even with the method described above, it is possible to remove contaminants such as heavy metals from the element active region by low-temperature heat treatment, so that deterioration of element characteristics can be prevented.

As in the first embodiment, the DRAM substrate may be formed after the silicon substrate 31 having the gettering site and the gettering barrier formed thereon is bonded to the silicon substrate 31. FIG. 11 is a sectional view of a pixel portion of a CCD image sensor including a photoelectric conversion device according to a fourth embodiment of the present invention.

A p-well region 52 is formed in the n-type silicon substrate 51. In the p-well 52, a vertical CCD area 53 (n ⁻ Layer) and photodiode region 6
1 (n ^- Layers) are formed alternately. The vertical CCD area 53 and the photodiode area 61 are connected by a channel stop (P ⁺ Layers) 60. A gate electrode 5 made of polysilicon is formed on the vertical CCD region 53 via a gate oxide film 54 made of SiO _2.
5 is formed. On top of that, a CVD oxide film (SiO
₂ ) 56 and an optical shield layer 57 made of aluminum,
59 are sequentially formed, and an insulating film 58 made of BPSG or the like is further formed thereon. A high-concentration phosphorus-doped polysilicon film 21 is formed on the back surface of the substrate 51. The formation of this phosphorus-doped polysilicon film 21 is performed as follows.

That is, at the beginning of the element forming process, the thickness of about 0.8 μ serving as a mask is formed on the surface of the substrate 51 by using the CVD method.
m silicon oxide film is formed. Then SiH ₄ , P
By the CVD method using H ₃ gas, the phosphorus concentration which becomes a gettering site (gettering barrier) on the back surface of the substrate 51 is 10 ²⁰ atoms / cm ^3. Above, the thickness is about 500
A phosphorus-doped polysilicon film 21 having a thickness of nm is formed. The film forming conditions are similar to those of the first embodiment. Subsequently, for example, low temperature heat treatment is performed at 800 ° C. for 20 minutes or more. After that, the step moves to the step of forming the p well region 52 and the like described above.

Also in this embodiment, the phosphorus-doped polysilicon film 21 can prevent and remove contaminants such as heavy metals. As a result, the generation and extinction center of minority carriers due to heavy metals can be prevented from occurring, and the occurrence of white scratches can be eliminated.

As in the first embodiment, the CCD may be formed after the silicon substrate 51 on which the gettering site and the gettering barrier are formed and the silicon substrate 51 are bonded together. Furthermore, the surface of the gettering barrier may be covered with a protective film made of an oxide film or a nitride film.

The present invention is not limited to the above embodiment. In the above embodiment, the polysilicon film is 58
Although it is formed at 0 ° C., it is not limited to this and can be appropriately changed. Among them, 580 ° C to 620 ° C is preferable. When the temperature is lower than 580 ° C, the film forming rate decreases, and when the temperature is higher than 620 ° C, the uniformity of the film deteriorates. Further, although the gettering site and the gettering barrier using the polysilicon film have been described in the above embodiments, an epitaxial silicon film may be used. Further, the process of forming the gettering site and the gettering barrier is not limited to the process steps described in the above embodiments, but may be before or after the process steps. In addition, various modifications can be made without departing from the scope of the present invention.

[0057]

As described above in detail, according to the present invention, a silicon film containing phosphorus is deposited on the back surface of a substrate, and a low temperature heat treatment causes the polysilicon film to absorb contaminants, thereby reducing device characteristics. Contaminants in the element region can be removed without inviting it, and thus the manufacturing yield of semiconductor elements can be improved.

[Brief description of drawings]

FIG. 1 is a sectional view of a manufacturing process of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a characteristic diagram showing the relationship between Fe concentration and recombination lifetime.

FIG. 3 is a characteristic diagram showing a relationship between a phosphorus amount and gettering efficiency.

FIG. 4 is a characteristic diagram showing a relationship between a distribution coefficient K (T) and a gettering temperature.

FIG. 5 is a characteristic diagram showing the relationship between heat treatment time and heat treatment temperature.

FIG. 6 is a solid solubility limit curve of phosphorus for silicon.

FIG. 7 is a sectional view of a manufacturing process of the C-MOS transistor according to the second embodiment of the present invention.

FIG. 8 is a characteristic diagram showing a relationship between leak current and voltage.

FIG. 9 is a sectional view of a manufacturing process of a DRAM cell according to a third embodiment of the present invention.

FIG. 10 is a sectional view of a manufacturing process of a DRAM cell according to a third embodiment of the present invention.

FIG. 11 is a CCD image according to a fourth embodiment of the present invention.
Sectional drawing of the pixel part of a di-sensor.

[Explanation of symbols]

1a, 1b, 11, 31, 51 ... Silicon substrate, 2a,
2b, 21 ... Phosphorus-doped polysilicon film, 12, 52 ...
p-well, 13, 32 ... field oxide film, 14, 1
8, 36, 38, 54, 56 ... Oxide film, 15, 19 ... Polysilicon film, 16 ... P ⁺ layer, 17 ... N ⁺ layer, 20, 4
2 ... Insulating film, 22 ... Wiring pattern, 35 ... N ^- layer, 37
... Capacitor electrodes, 39, 55 ... Gate electrodes, 53 ... Vertical CCD area, 60 ... Channel stop, 61 ... Photodiode area.

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[Procedure amendment]

[Submission date] December 10, 1992

[Procedure Amendment 2]

[Document name to be corrected] Drawing

[Correction target item name] All drawings

[Correction method] Change

[Correction content]

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[Figure 5]

FIG. 11

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[Figure 10]

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Claims (2)

[Claims] 1. A silicon film, comprising: a semiconductor substrate having an element formed on a front surface thereof; and a silicon film formed on the back surface of the substrate and containing phosphorus for removing contaminants containing heavy metals from a formation region of the element. A semiconductor device having a phosphorus concentration exceeding the solid solubility limit of a silicon film at a predetermined temperature. 2. A method of removing a contaminant containing a heavy metal from an element formation region of a semiconductor substrate, comprising the step of providing a silicon film containing phosphorus on the back surface of the substrate, and the phosphorus concentration of the silicon film is equal to that of the silicon film. And a step of performing heat treatment at a predetermined constant temperature so as to exceed the solid solution limit.