JPH0410078B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a device for artificially adding reverberation to a musical tone signal or the like. More specifically, the present invention relates to a reverberation adding device mainly including a convolution operation circuit that generates a reverberation signal by convolution operation of a time function of a predetermined reverberation characteristic and an input signal.

FIG. 1 shows the basic configuration of a convolution calculation circuit as a reverberation adding device. The delay memory 1 stores the input signal X(t) while sequentially updating it for a predetermined period of time. As a result, the input signal X(t) is delayed by the delay memory 1. The signals X ₁ to Xm taken out from the delay memory 1 are signals obtained by delaying the input signal X(t) by times T1 to Tm, respectively. Each delayed signal _X1 to Xm is converted into a coefficient (gain data) _G1 to Gm by a coefficient multiplier ₂₁ to 2m, respectively.
are multiplied (weighted), and these respective outputs are added and combined in an adder 3. In other words, the adder 3 outputs the convolution result Y shown in the following equation.

Y= _n 〓 ⁱ⁼¹ Gi+Xi This output Y becomes the reverberation signal.

Here, the above delay time Ti and gain data Gi
(i=1 to m) corresponds to the reverberation characteristics due to the impulse response as shown in FIG. In other words, the time function of the desired reverberation characteristic is expressed by the parameters Ti and Gi, and the reverberation signal Y is generated by convolving this with the input signal X(t).

The problem with this type of convolutional reverberation adding device is that the number of convolution calculation points, that is, the m points in the example of FIG. 1, is severely restricted by hardware, and it is difficult to freely increase this number.

In the basic configuration shown in Figure 1, convolution operations are performed using individual coefficient multipliers 2 ₁ to 2 m, but it is easy to understand that if m is increased in this case, the hardware becomes enormous. It is possible.

Furthermore, in practice, the above convolution operation is not performed using individual coefficient multipliers, but is usually performed by serial sequential processing.

In this case, if m is increased, the number of arithmetic circuits that must be executed within a certain period of time increases, and as a matter of course, there is an upper limit to m in terms of arithmetic speed.

The fact that the number m of convolution calculation points cannot be increased means that reverberation with a very long delay time cannot be created. This is because the number of calculation points m is the number of parameters Ti and Gi used in calculation.
This is because reverberation characteristics extending to long delay times cannot be appropriately expressed with a small number of parameters.

This can be easily understood from FIG. If the delay time data Ti is taken very roughly on the time axis, reverberation characteristics over a long time period can be expressed with a small number of parameters. However, even if this method satisfies the length of the reverberation, it does not satisfy the quality of the reverberation (this method is called parameter thinning). Achieving the desired natural reverberation generally requires a large number of parameters that are spaced sufficiently closely together on the time axis.

For these reasons, in most conventional systems, reverberation of only the initial delay time period of a desired reverberation characteristic is created by convolution calculation. As long as there is only a limited initial delay time period, the reverberation characteristics can be expressed with high density even with m parameters. However, in this case, the latter part (later delay time range) of the originally desired reverberation characteristics over a large time range is omitted, and it is desirable to compensate for this in some way.

This invention was made against the above background, and its purpose is to create reverberation in the initial delay time zone of reverberation characteristics using a convolution calculation circuit,
To provide a reverberation adding device capable of obtaining a more natural reverberation effect by supplementing the reverberation in the subsequent late delay time period with another simple hardware.

In order to achieve the above object, the present invention includes a convolution calculation circuit that generates a reverberation signal in an initial delay time period, a plurality of cascade-connected delay circuits that delay the output of this convolution calculation circuit, and a convolution calculation circuit that delays the output of the convolution calculation circuit. an adder circuit that adds the outputs of the circuit and the delay circuits at each stage to obtain a composite output; and a filter inserted in a signal path from the output of the delay circuit at each stage to the final addition point by the adder circuit. It is characterized by having the following.

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 3 shows the configuration of a reverberation adding device according to the present invention. Convolution calculation circuit CU in the same figure
has the basic configuration shown in FIG. 1, and an input signal X(t) is applied to it. The reverberant signal output from the convolution arithmetic circuit CU is supplied to n-stage delay circuits DU1 to DUn connected in series and delayed. The output of the convolution arithmetic circuit CU and the output of the delay circuits DU1 to DUn of each stage are connected to n adders.
Addition and synthesis are performed by KU1 to KUn, and the output terminal
Derived to OUT. At this time, the delay circuit DU of each stage
The outputs of 1 to DUn pass through filters F1 to Gn before reaching the adder KU1 at the final addition point. In detail, the output of the first stage delay circuit DU1 is filter F.
1, the output of the second stage delay circuit DU2 passes through filters F2 and F1, and the output of the final stage delay circuit DUn passes through all filters Fn to F1, and is sent to the final stage addition point. is input.

Therefore, the configuration shown in FIG. 3 is equivalent to the configuration shown in FIG. 4, in which filters F1 to Fn are provided between stages of delay circuits DU1 to DUn, and one adder KU obtains a combined output. Here, the output of the convolution arithmetic circuit CU is Y, the output delayed by the delay circuit DU1 and passed through the filter F1 is Y1, and the output of the delay circuit DU1 is
The output delayed by DU2 and passed through filters F1 and F2 is expressed as Y2.

FIG. 5 shows the above-mentioned outputs Y, Y1, Y2 and their combined output in the form of an impulse response waveform. The convolution arithmetic circuit CU outputs a reverberation signal Y having a maximum delay time Tm with respect to the input impulse. This Tm is called the convolution time.
In the waveform example shown in Figure 5, the delay circuit DU1 and
The delay times DT1 and DT2 of DU2 are set equal to the convolution time Tm.

With this setting, the convolution calculation circuit CU
When the reverberation component of output Y1 disappears, a delayed reverberation component Y1 follows without any blank time, and when the reverberation component of output Y1 disappears, it continues with a delay without any blank time. Reverberation output Y2 is generated. As a result, as shown in FIG. 5, the composite output OUT becomes a signal with a continuous reverberation characteristic that includes the output Y of the convolution arithmetic circuit CU and the delayed outputs Y1 to Yn of each stage without any overlap or blank space.

Note that the present invention is not limited to making the convolution time Tm equal to the delay time of each stage. For example, the delay time DT1 may be made larger than the convolution time Tm to create a blank time between the reverberation components of the output Y and Y1, or conversely, the delay time DT1 may be made smaller than the convolution time Tm,
The reverberation components of the outputs Y and Y1 may be overlapped. In this way, it is preferable to appropriately set the delay time of each stage to prevent unnatural reverberation from occurring at the connection portion of the output of each stage.

Further, instead of setting the delay time of the delay circuit fixedly, the delay time may be changed over time. In this case, the way in which the reverberation components of the outputs of the front and rear stages grow is not constant, but changes randomly, so that the periodicity of the reverberation components of each stage is no longer noticeable, and a more natural reverberation effect can be obtained.

Next, the functions of the filters F1 to Fn will be explained. Filters F1 to Fn are generally high-cut filters. Then, the reverberation time becomes longer for lower frequency components of the input signal, and the reverberation time for wider frequency components becomes shorter. In other words, as mentioned above, the output terminal
This is because, when viewed from OUT, signal components with larger reverberation times (delay times) pass through filters F1 to Fn in multiple stages. The frequency characteristics of such reverberation are close to natural and are generally set in this way, but the present invention is not limited to this.
It is also possible to obtain special acoustic effects by selecting various characteristics of the filters F1 to Fn.

As described above, according to the present invention, even if reverberation is obtained only for a limited time Tm in the convolution arithmetic circuit CU, the reverberation that should follow is generated in the delay circuits DU1 to DU1.
DUn, filters F1 to Fn, and an adder create natural reverberation over a very long time in the form of repeating the reverberation characteristics in the convolution arithmetic circuit CU.

Next, a specific example of the configuration of the convolution arithmetic circuit CU will be explained in detail with reference to FIGS. 6, 7, and 8.

The convolution calculation circuit CU shown in FIG. 6 includes a data memory 23 that sequentially stores a predetermined number of samples of an input signal X(t) obtained by digitizing an analog musical tone signal, etc., and a reverberation corresponding to an impulse response of a virtual room. It is provided with a parameter memory 20 for storing characteristics, and convolution calculation means for performing a convolution calculation according to data in both of these memories 20 and 23 to obtain a reverberation signal OUT.

The data memory 23 enters the write mode every time the clock C2 with the period T output from the timing controller 32 is generated, and the output of the counter 24, which is incremented by the clock C1 with the same period T, is given as the write address ( Note that the output of the counter 24 is given via the subtracter 27, and the subtraction input at this time is O, as will be described later). In other words, the input signal X is stored in the data memory 23.
(t) are sequentially written at a constant sampling period T, and a predetermined number of latest sample data X ₁ to Xj (X ₁ , X _{2 .} . . in order of newest) are stored while being updated sequentially.

In the parameter memory 20, impulse response characteristics as shown in FIG. 2 are stored in the data format shown in FIG. One parameter consists of a pair of delay time data Di and gain data Gi (i = 1 to m), and the desired reverberation is achieved using delay time data Di at m points on the time axis and gain data Gi corresponding to each point. Characteristics are expressed. Parameter memory 2 is m+1
Data O is written to the first address O, and parameters are written to the subsequent addresses.
Di and Gi are stored in order (note that data O at address O is assumed to be D ₀ and G ₀ ).

The delay time data Di here is given as an integer value indicating how many times the sampling period T of the input signal is. That is, Di×T=Ti.

Writing of this parameter is performed by the controller 22 in advance. Note that the multiplexer 26 connected to the address input of the parameter memory 20 is selected by the controller 22 when the controller 22 writes data. In other normal operating conditions, the output of counter 25 is applied via multiplexer 26 to parameter memory 20 as a read address.

The counter 25 is cleared by the clock C4 that occurs immediately after the clock C1, and is incremented by the clock C5 with a period of 1/(m+1) of the sampling period T, and gives its coefficient output to the parameter memory 2 as a read address. . Therefore, data stored in the parameter memory 20 is sequentially read out every sampling period T. memory 20
The delay time data Di among the parameters read from the subtracter 27 becomes the subtraction input of the subtracter 27. Further, the gain data Gi is input to the multiplier 28 and multiplied by the data Xi read out from the data memory 23 as described later. The multiplication output is input to an accumulator 29 consisting of an adder 30, a register 35, and an AND circuit 31.

More specifically, as shown in FIG. 7, the counter 24 is incremented at the rising edge of the clock C1, and at the same time, the clock C4 goes low and the counter 25 is cleared. Therefore, the parameter memory 20 is designated with address O by the output of the counter 25, and the data stored at address 0 is stored in the parameter memory 20 as described above.
D ₀ =0, G ₀ =0 are read.

Then, when the next clock C5 rises, the clock C2 also rises, and the data memory 23 enters the write state. At this time, the output of the parameter memory 20 is 0.
Therefore, the output of the subtracter 27 is the output of the counter 24 itself. Therefore, the input signal X(t) at this time is written to the address indicated by the output Ak of the counter 24. This is the latest sample data
Similarly, a certain amount of latest past sample data X _{1 to} Xj is stored in the data memory 23.

When writing of one sample data to the data memory 23 is completed, the data memory 23 enters the read mode. Further, until the next rising edge of the clock C1, the counter 25 is incremented in synchronization with the clock pulse C5, and the counter 25 is incremented in synchronization with the clock pulse C5.
.about.n are sequentially specified, and parameters Di and G are sequentially read.

When the delay time data Di is output from the parameter memory 20, Di is changed from the output Ak of the counter 24.
The subtractor 27 outputs the value Ak−Di obtained by subtracting
This becomes the read address of the data memory 23, and the data corresponding to this is read from the memory 23.

The address Ak of the data memory 23 is the storage address of the latest sample data X1, whereas the address Ak-Di is the storage address of the past sample data Di times. This address Ak−
Let Xi be the sample data read from Di.
This data Xi converts input signal X(t) into time Ti=Di×
This is data delayed by T.

The delay data Xi read out from the data memory 23 is the gain data read out from the parameter memory 20 together with the delay time data Di.
Multiplyed (weighted) by Gi and multiplier 28. The output Gi×Xi of the multiplier 28 is input to the accumulator 29.

The accumulator 29 sequentially accumulates the output Gi×Xi of the multiplier 28 using an adder 30 and a register 35 in synchronization with the clock C5. Immediately after the next rise of the clock C1, the cumulative result for one cycle, Y= _n 〓 ⁱ⁼¹ Gi×Xi, is obtained, and this becomes the reverberant signal output OUT.

Thereafter, during the period in which the output of the counter 25 becomes 1, the clock C3 becomes L level, and as a result, the AND circuit 31 of the accumulator 29 is cut off. In other words, the contents of the accumulator 29 are once cleared at this point, and the accumulation for the next cycle is started again.

Next, one delay circuit in the configuration of FIG.
A specific circuit configuration including DUi and filter Fi will be explained with reference to FIG.

In FIG. 9, the input signal In is input to the delay memory 60, and the above-mentioned clock signal C having a period T is input to the delay memory 60.
It is written to the address specified by the output of counter 65, which is incremented by 1. When the output of the counter 65 is Ap, the delay memory 60 is controlled to read the data written to the address Ap immediately before writing the input to the address Ap. Therefore, the input signal from the delay memory 60
Signals obtained by delaying IN by the capacity of the memory 60 are sequentially output at a period T. This is the configuration of the delay circuit DUi.

Delayed data output from the delay memory 60 is supplied to a filter Fi consisting of multipliers 61 and 62, an adder 63, and a register 64. Register 64 receives clock C1 and latches old data for one cycle T. If the output of the delay memory 60 is Yp, the register 64 outputs the data from one cycle before.
Yp-1 is output. The signal Yp is multiplied by a coefficient A ₀ in a multiplier 61, the signal Yp-1 is multiplied by a coefficient A ₁ in a multiplier 62, and the results are sent to an adder 63.
are added together to form the output signal OUT. This is a well-known primary filter configuration.

FIG. 10 shows a modification of the delay circuit part in FIG. 9. Here, the delay time by the delay memory 60 is randomly changed over time by a random number generator 66 (the effect of this is described earlier). ing). When writing the input signal IN to the delay memory 60, the output of the counter 65 is sent to the delay memory 60 via the multiplexer 69.
This is the address input. However, the address when reading data immediately before writing is register 6.
A value obtained by adding the data stored in 7 and the output of the counter 65 by an adder 68 is given via a multiplexer 69. Random data generated from the random number generator 66 is stored in the register 67 as the clock C.
It is latched in synchronization with 9. The period of this clock C9 is equal to the aforementioned convolution time of the convolution arithmetic circuit CU. Further, the random number generator 66 operates at a cycle sufficiently faster than the convolution time Tm, and generates, for example, M-sequence random numbers. As a result, the delay memory 6
The delay time due to 0 changes randomly for each convolution time Tm.

As explained in detail above, according to the reverberation adding device according to the present invention, by adding relatively simple hardware to the convolution calculation circuit, it is possible to realize natural reverberation characteristics over a sufficiently long time period. I can do it.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the basic configuration of a convolution calculation circuit, FIG. 2 is an explanatory diagram of the time function of reverberation characteristics due to impulse response, and FIG. 3 is a block diagram showing the basic configuration of the reverberation adding device according to the present invention. , FIG. 4 is a block diagram showing another embodiment of the present invention equivalent to FIG. 3, FIG. 5 is an explanatory diagram of the operation of the device in FIG. 4, and FIG. 6 is a diagram showing the convolution in FIGS. 3 and 4. A block diagram showing a specific configuration example of the arithmetic circuit CU,
7 is a timing chart for explaining the operation of the device shown in FIG. 6, FIG. 8 is an explanatory diagram showing the contents of the parameter memory 20 in the device shown in FIG. 6, and FIG.
A block diagram showing a specific circuit configuration including a delay circuit and a filter in the device shown in the figure, and FIG. 10 is a block diagram showing a modification of FIG. 9. CU...Convolution operation circuit, DU1~DUn...Delay circuit, F1~Fn...Filter, KU1~KUn...Adder.

Claims (1)

[Claims] 1. A convolution calculation circuit that generates a reverberation signal by convolving an input signal with a time function of a predetermined reverberation characteristic; and a plurality of cascade-connected delay circuits that delay the output of the convolution calculation circuit. and; an adder circuit that adds the outputs of the convolution arithmetic circuit and the delay circuits of each stage to obtain a composite output; and a signal path from the output of the delay circuit of each stage to the final addition point by the adder circuit. A reverberation adding device comprising: an inserted filter;