JPH0262877B2 - - Google Patents

Description

[Detailed description of the invention]

[Industrial Application Field] This invention relates to a device that creates reverberant sound of an input signal by superimposing multiple delayed signals of an input signal (music signal, etc.) created using impulse responses as coefficient parameters. This method controls the frequency characteristics of the sound to limit the band, and at the same time increases the number of calculation points by lengthening the period for creating one sample of reverberant sound, creating a more ideal reverberant sound. . [Prior Art] When artificially adding reverberation to music signals, etc., the most direct electronic method is to extract various types of reverberation from the direct sound in response to the impulse response in an acoustic space such as a virtual hall. This is a method of expressing signals as a superposition of signals with time delays. That is,
As shown in Figure 2, the impulse response of the virtual acoustic space is expressed by the delay time τ _i and the level relative to the direct sound.
Assuming that it is a string of multiple reflected sounds consisting of g _i (i = 1 to n), the delay time τ _i and level g _i are used as coefficient parameters (reflected sound parameters) to reflect the reflected sound for each sample of the input signal. By creating each sound sequence and superimposing the reflected sounds of each sample at the same time (the operation of multiplying and adding the delayed signal by a gain is called convolution operation), reverberant sound is created. Ru. Conceptually, this convolution operation is performed using a multi-tap shift register 1, as shown in Figure 3.
Each sample value of the input signal is measured at the sampling period τ ₀
The delayed signals X ₁ to X _o of each sample are outputted from each tap corresponding to the delay time τ ₁ to τ _o within one sampling period τ ₀ , and these are sent to the multiplier 2- 1, 2-n are given coefficients (gains) g ₁ to g _o respectively, and the adder 3
One sample of the reverberant signal, Xout= _o 〓 ⁱ⁼¹ x _i・g _i , is obtained. Specifically, as shown in FIG. 4, each sample of the input signal is stored in the data memory 10, the delay time data τ ₁ to τ _o are sequentially read out from the parameter memory 12, and each delay time is set using these as addresses. The delayed signals X ₁ to X _o corresponding to τ ₁ to _{τ o} are sequentially read out _from the data memory 12, and the multiplier 14 assigns coefficients g ₁ to go to these delayed signals X ₁ to _{X o} , respectively.
Sequentially create individual reflected sound signals X ₁・g ₁ ~X _o・g _o ,
By sequentially accumulating these in an accumulator 16 comprising an adder 18 and a register 20, one sample of the reverberant signal is created. Then, by repeating this series of operations each time a new input signal sample is written to the data memory 10, a series of reverberation signals is created. The convolution operation using the above serial sequential processing is
The above series of operations must be performed during one sampling period τ ₀ of the input signal to create one sample of the reverberant signal, but due to constraints on calculation speed,
In the point accumulator 16 that can perform convolution operations during period τ ₀ , the number of times data coefficients are added and accumulated during period τ ₀ is limited. However, it is clear that a more natural reverberant signal can be reproduced if more convolutions are performed. Therefore, conventionally, there has been a method that selectively uses a region of the reflected sound parameter within the period τ ₀ to substantially increase the number of convolution points. FIG. 5 shows this situation, and shows the range of reflected sound parameters used at each time point a to k of the input signal. According to this, when the input signal continues (a to d), the second half of the reverberant sound (low level)
has the property of being masked by the input signal and becoming inaudible, so only the reflected sound parameters of the initial part are used (hereinafter referred to as fixed type operation), and when the input signal is interrupted (e~), the reflected sound parameters are used. The area of reflected sound parameters is sequentially shifted to lower levels to ensure natural and long reverberant sound (hereinafter referred to as adaptive operation). Incidentally, reverberation in the natural world changes over time, and has the property that higher frequency components attenuate faster. Therefore, even in the above-mentioned artificial reverberation addition, as shown in FIG. 6, for example, the reverberation addition circuit 2
A frequency characteristic control circuit 24 is provided on the output side of 2,
If the filter characteristic (low-pass filter) of the frequency characteristic control circuit 24 is sequentially switched from f ₁ to _fo (FIG. 8) as shown in FIG. 7 during the adaptive operation, this phenomenon can be avoided. can be simulated. [Problems to be Solved by the Invention] The present invention aims to obtain more natural reverberant sound in the reverberation adding device that involves frequency characteristic control. [Means for solving the problem] This invention increases the number of convolution points by lengthening the sampling period for creating a reverberation signal in the reverberation adding circuit in accordance with the band limitation by frequency characteristic control. be. [Operation] According to the solution of the present invention, the number of convolution points for creating one sample of the reverberant signal increases, so the amount of information constituting the reverberant signal increases, making it possible to obtain a more natural reverberant sound. can. [Principle of the Invention] According to the sampling theorem, the original waveform can be perfectly reproduced if sampling is performed at a sampling frequency that is twice or more the highest frequency of the signal. Therefore, when band limiting is performed by the frequency characteristic control circuit 24, even if the sampling frequency of the reverberation signal output from the reverberation addition circuit 22 is lowered as the band becomes narrower, the reverberation signal within the band becomes narrower. Can be reproduced. If the sampling period is lowered, one sampling period becomes longer and the number of points that can be convolved within this period increases, thereby increasing the information content of the reverberant sound and making it possible to obtain a reverberant sound that is more natural. That is, when the frequency band changes as shown in FIG. 8, by changing the sampling period as shown in FIG. 9 in accordance with the band change, the number of convolution points can be changed accordingly. That is, the number of convolution points≒sampling period/one operation (time required for adding coefficients and adding). FIG. 10 shows how the number of convolution points changes when the sampling period is changed according to the present invention. Furthermore, FIG. 11 shows how the area and number of reflected sound parameters used for convolution change as well as the filter characteristics change when the input is interrupted and the adaptive operation is started. As the reverberant signal attenuates, the band of the filter characteristic narrows (see Figures 7 and 8).
(Figure), the number of reflected sound parameters used gradually increases, and the number of convolution points increases. [Embodiment] An embodiment of the present invention is shown in FIG. This reverberation addition device includes a reverberation addition circuit 22 that creates a reverberation signal of an input signal, and a frequency characteristic control circuit 24 that gives filter characteristics to the created reverberation signal. The reverberation adding circuit 22 is configured to perform an adaptive operation of sequentially shifting the area of the reflected sound parameter to be used to a lower level when the input is interrupted. By the way, an adaptive reverberation adding device detects that the input signal has reached zero level, and changes from a fixed operation, that is, an operation that creates reverberant sound by fixing the parameter usage interval to an upper level, to an adaptive operation, that is, an operation that creates reverberation sound using parameters. However, in order to determine whether the detected zero level is simply due to a zero crossing of the signal waveform, or whether it is actually due to the input signal being interrupted, it is necessary to wait several tens of millimeters. It is necessary to detect the level of the input signal over a long period of time, on the order of seconds.
Furthermore, when it is determined that the input signal has been interrupted, the adaptive operation must be executed going back to the first input signal portion of the detection section. For this reason, in the conventional adaptive type, the input signal is always delayed by the detection time using a memory (pre-memory) to temporarily store the input signal, which has the disadvantage of causing a delay time between input and output. It was hot. Therefore, the reverberation addition circuit 22 of the embodiment shown in FIG. 1 improves this and performs a fixed convolution operation by applying the initial part of the reflected sound parameters to the data in the pre-memory 32, and converts the delayed data from the pre-memory into For the data memory 34 into which the reflected sound parameters are input, an adaptive convolution operation is performed by applying the remaining reflected sound parameters, and these outputs are finally added to eliminate the delay between input and output. . Note that in this example, a total of n parameters (τ ₁ , g ₁ ) to (τ _o , _go ) are used, among which the top h parameters (τ ₁ to g ₁ ) ~ (τ _h , g _h ) and the remaining parameters (τ _h+1 , g _h+1 ) in adaptive convolution
A case will be described in which an appropriate region of ~(τ _o , go ₎ is used. In FIG. 1, the input signal samples are temporarily stored in the pre-memory 32 for zero detection of the zero detection section 25, and are delayed for several tens of milliseconds before zero detection is performed.
It will be transferred to 4. The fixed convolution calculation unit 27 is connected to the pre-memory 3
A reverberation signal of the initial part is created from the data of 2.
That is, the impulse response delay memory 40 stores delay time parameters τ _i (i=1, 2...
n), parameters corresponding to the delay data held in the pre-memory 32 (that is, parameters up to several tens of milliseconds) τ ₁ to τ _h are stored. The impulse response level memory 42 also stores level parameters g ₁ to _gh corresponding to these. The counter 44 reads and scans all parameters (τ ₁ , g ₁ ) to (τ _h , g _h ) from the memories 40 and 42 every sampling period of the input signal, and
This is for providing a write address and a read address to the pre-memory 32. Since the read address is at a position delayed by τ ₁ to τ _h with respect to the write address, the adder 46 provides the write address in the form of adding the delay time parameters τ ₁ to τ _h . Each delay time τ ₁ read from the pre-memory 32
The input sample values X ₁ to X _h corresponding to ~τ _h are multiplied and accumulated by the corresponding level parameters g ₁ to g _h from the memory 42, respectively, in the convolution calculation circuit 48, and a convolution calculation is performed. It will be done. In this way, a series of convolution operations are performed every sampling period of the input signal, and the fixed convolution operation section 27 outputs an initial portion of the reverberation signal. In the adaptive convolution calculation unit 36, the data memory 34 writes the delayed data outputted from the pre-memory 32 in order from the address where the oldest sample is written, and updates the data memory 34 sequentially. The impulse response delay memory 50 is
Delay time parameters τ h+1 to τ o subsequent to delay time parameters τ ₁ to τ _h of the early reflected sound portion used in the fixed convolution calculation section 27 are stored, and the impulse response level memory 52 stores these delay time parameters τ _h+1 to τ _o . Corresponding gain parameters g _h+1 to g _o are stored. The contents of these parameters (τ _h+1 , g _h+1 ) to (τ _o , _go ) will be described later. The counter 48 reads out and scans parameters in a predetermined area among all the parameters (τ _h+1 , g _h+1 ) to (τ _o , g _h ) from the memories 50 and 52 every sampling period of the input signal 1. It is something. The permutation control 54 determines the predetermined area from which the counter 48 should read. In other words, when the input signal is continuous, a predetermined number of parameters (τ _h+1 , g _h+1 ), (τ _h+2 , g _h+2 ) from the beginning are
..., are read out sequentially according to the count of the counter 48, and when the zero detection unit 25 detects zero, the subsequent time t is measured, and this and the delay time t ₀ in the pre-memory 32 (τ _h ≦t ₀ ≦τ _{h+ 1} ) and use parameters having the relationship t+t ₀ ≦τ _i from the top. For example, since t = 0 at the beginning, (τ _h+1 , g _h+1 ), t
When +t ₀ > τ _h+1 , further t+t ₀ from (τ _h+2 , g _h+2 )
>τ _h+2 , a predetermined number of parameters are used from (τ _h+3 , g _h+3 ). In this case, the band control circuit 5
According to the command No. 5, the number of parameters used increases sequentially. The address controller 56 controls the data memory 3
This command specifies the write and read addresses of 4. As described above, as the write address, the address containing the oldest sample is sequentially designated and updated to a new sample. As the read address, a data address corresponding to the delay time parameter τ _i read from the impulse response delay memory 50 is designated based on the write address, and the delay time data X _i is read out. Note that specific details regarding reading data from the data memory 34 will be described later. Note that when zero detection is performed, writing to the data memory 34 is stopped, and when zero detection is canceled (when signal input is resumed), writing is restarted from the address where it stopped. There is. The convolution calculation circuit 38 is connected to the data memory 34
The delayed signal data X _i read from the impulse response level memory 52 is sequentially multiplied by the corresponding level parameter g _i from the impulse response level memory 52 and accumulated, and one reverberation signal sample is output. In this way, the predetermined period (when the input signal is sustained and the fixed type operation is performed, the sampling period of the input signal is sequentially longer than when the input signal is interrupted and the adaptive type operation is performed) Samples of the reverberant signal after the initial part are created for each period (with increasing frequency). The output of the adaptive convolution calculation unit 36 is input to the frequency characteristic control circuit 24 and is given a filter characteristic. This circuit 24 is composed of a digital filter, and sequentially delays the input signal in a memory provided in the filter calculation circuit 70, reads and scans the filter coefficients stored in the coefficient memory 66 with a dedicated counter 68, and The delayed data is multiplied and accumulated (that is, this filter operation is also a convolution operation) to give filter characteristics. Coefficients representing various filter characteristics are stored in the coefficient memory 66, and when a zero is detected by the zero detection section 25, low-pass filter characteristics whose cutoff frequency is successively lowered are selected. At this time,
Bandwidth control circuit 55 of adaptive convolution calculation unit 36
issues a command to the permutation controller 54, address controller 56, and counter 68 in order to sequentially lengthen the sampling period for creating a reverberation signal according to the selected filter characteristics. The initial part of the reverberation signal created by the fixed convolution calculation unit 27 and the adaptive convolution calculation unit 36
The sampling period created in is returned to the original value, and the reverberation signals after the initial stage, which are further given filter characteristics by the frequency characteristic control circuit 24, are added together by the adder 60 and output as a single unit. [Specific Example of Reverberation Addition Circuit 22] A specific example of the reverberation addition circuit 22 in the embodiment of FIG. 1 is shown in FIG. Before explaining a specific example, a brief description will be given of how the sampling period is varied, the contents of the convolution operation when the period is varied, and the storage of parameters therefor. In principle, as long as the sampling period change ratio matches the band limit content on the output side,
Any ratio is possible, but here:
To simplify the operation, the sampling period is increased by 2 times at a time (in other words, the band limit of the frequency characteristic control circuit is changed by 1/2 times at a time. Also, as the sampling period changes, the output The interval at which samples are obtained also changes.Recalling the principle of the convolution operation again, the data sequence used to obtain a certain output sample sequence is
They must be obtained at the same time. That is, when the sampling period doubles, the data interval used also doubles, that is, if the same data string is used, every other data must be used. If the sampling period quadruples, the data interval used must also quadruple, that is, every third data must be used. Furthermore, in the case of the above-mentioned adaptive calculation, it is necessary to accurately grasp the position of the leading data that is sequentially shifted. In order to achieve the above-mentioned contents, it is possible to control the data read address circuit to perform such an operation using hardware, but here, as a simpler and more effective method, we will use the convolution operation. The method of assigning the parameters used has been devised. The stored contents of the parameter memory of the specific example shown in FIG. 12 will be explained with reference to FIGS. 13a and 13b. Figure a schematically represents a general impulse response, with the horizontal axis representing real time. When storing this in memory as a coefficient parameter, it would be most direct if the memory address and time corresponded one to one, but in that case a huge amount of memory would be required. Therefore, in the past, there was a response and data only for the initial part was stored in memory in the form of delay time and gain, but here,
Considering that as time passes, the sampling period becomes longer and the applied data interval is also thinned out as described above, as shown in FIG. 13b, only necessary response parameters are stored. As a result, the parameters to be stored are generally thinned out in the latter part, depending on the convolution operation mode and sampling period at the relevant time, and the total number is considerably smaller than in the case without thinning. . By the way, in order to specifically determine the stored contents of the parameters, it is necessary to further determine the conditions for changing the band limit, etc. Here, the initial delay due to fixed type operation is t ₀ , and after shifting to adaptive type, the band limit value (corresponding to the cutoff frequency value of the filter) decreases by 1/2 at every t ₀ , 4t ₀ , and 16t ₀ . As something to go on,
Parameter selection is made from FIG. 13a to FIG. 13b. In other words, according to this, even with the same hardware, each time the bandwidth limit is reduced by 1/2,
The number of convolution points is doubled, and Fig. 13a
In terms of real time, which corresponds to the horizontal axis of , reverberation for four times as long can be obtained. In an actual circuit, the parameters of part a in Fig. 13b are the fixed operating parameters (τ ₁ , g ₁ ) ~
As (τ _h , g _h ), the parameters of part b are stored in the parameter memory 72 as adaptive operation parameters (τ _h+1 , g _h+1 ) to (τ _o , _go ).
As a result, skip reading of a predetermined number of data due to a change in the sampling period, which is required in adaptive operation with a variable sampling period, can be achieved extremely easily by simply changing the addresses of the parameter memory 72 in sequence. be able to. In FIG. 12, timing controller 1
From 24, control clocks C1, C1', C2', C3, C3', C4', C for operating each part are provided.
5 and C6 are output (see FIG. 14). Clock C1 is a signal synchronized with the sampling period τ ₀ of the input signal. Clock C1' synchronizes with the sampling period τ ₀ of the input signal when the input signal continues and is in fixed operation, and when the input signal is interrupted and shifts to adaptive operation, the period doubles, quadruples, and 8 times. It is a signal that gradually becomes longer. (Hereinafter, the period of this clock C1' will be referred to as the period of clock C1 τ ₀
The sampling period is called τ ₀ ′, including when it coincides with . ). Clock C2', C3', and C4' are signals with the same period τ ₀ ' as clock C1'.
The period is varied together with 1'. Clock C5 is a signal with a shorter period than clock C1 and has a fixed period, and clocks C3 and C6 are signals with the same period τ ₀ as clock C1. In addition, clocks C1', C2', C3', C4'
is variably controlled according to the filter characteristics of the frequency characteristic control circuit 24. The counter 80 provides a write address to the pre-memory 32, and is incremented by the clock C1 every cycle _τ0 . The counter 81 provides a read address for the fixed operating parameters in the parameter memory 72 and is reset at the beginning of the period τ ₀ .The subtracter 82 that counts the clock C5 thereafter uses the write address from the counter 80 and By subtracting the delay time parameters τ ₁ to τ _h from the parameter memory 72, the delay time τ ₁ to τ _h for the current write address is determined.
The address is determined and given to the pre-memory 32 as a read address. The prememory 32 is switched to the write mode once every period τ ₀ by the clock C6. At this time, since the address command of the counter 81 to the parameter memory 72 is 0, 0 is read out from the memory 72 as the delay time parameter, and the value of the counter 80 is output as is from the subtracter 82, and the value of the counter 80 is output as is. Pre-memory 3 indicated by the value
Samples of the input signal are input to and output from address 2. At timings other than clock C6, the prememory 32 is in the read mode, and the delay time parameter τ ₁ is sequentially output from the parameter memory 72 within the period τ ₀ according to the address command from the counter 81.
_{.about..tau.h} , input samples at a delay time of _.tau.1 to _.tau.h with respect to the write address are sequentially read out. The counter 74 provides a write address (or a reference address when writing is prohibited) to the data memory 34, and is configured to input a sampling period τ ₀ '/τ ₀ separately by the clock C1' _every period τ 0 '. The counter is incremented by a corresponding number (that is, when no adaptive operation is performed, the counter becomes a normal counter that counts by 1). The subtracter 76 uses the write address from the counter 74 and the delay time parameter τ _i (τ _i is a variable number selected from τ _h+1 to τ _o (parameters)) to obtain each address of delay time τ _i with respect to the current write address, and provide this to the data memory 34 as a read address. Data memory 34 is switched to write mode once every period τ ₀ ' by clock C2'. At this time, since 0 is read as the delay time parameter from the parameter memory 72, the value of the counter 74 is output as is from the subtracter 46, and the output of the prememory 32 is written to the address of the data memory 34 indicated by that value. . At this time, the pre-memory 32
Since the address to be written next (that is, the address containing the oldest data) is specified by the counter 80, the data written to the data memory 34 is data delayed by the capacity of the prememory 32. becomes. At timings other than clock C2', the data memory 34 is in the read mode, and the delay time parameter τ _i sequentially output from the parameter memory 72 within the period τ ₀ ' causes a delay time of τ _i with the write address as the reference. Certain data is read out sequentially. Data read out sequentially from pre-memory 32
X ₁ to X _h are level parameters g ₁ sequentially output from the parameter memory 72 in the multiplier 84
~g _h are multiplied, respectively, and g ₁ · X ₁ ~ _{g h} ·X _h are output in sequence. The amiumulator 87 adds the multiplied values from the multiplier 84 using the adder 89 and the register 91, so that the final value is the accumulated value of all the multiplied values within the period τ ₀ , that is, , one sample of the reverberant signal in fixed form operation is obtained. Therefore, the period of the sample sequence obtained by sequentially repeating is the fixed period τ ₀ . In addition, the AND circuit 93
After the sample is obtained, the register 91 is cleared to zero at the timing of clock C3 in preparation for accumulation within the next period τ ₀ . Data read out sequentially from data memory 34
In the multiplier 86, X _i is
are multiplied by the level parameters g _i sequentially output from , respectively, and g _i ·x _i (i is a variable predetermined number selected from h+1 to n) are sequentially output. The accumulator 88 adds the multiplication value from the multiplier 86 to the addition value 90 and the register 92, so that the final value is the accumulated value of all the multiplication values within the period τ ₀ ', i.e. , one sample of the reverberant signal in adaptive operation is obtained. Therefore, the period of the sample sequence obtained by sequentially repeating is a variable period τ ₀ '. The sampling period conversion circuit 95 converts a sample string of the reverberant signal with a variable period τ ₀ ' obtained by the adaptive operation into a sample string with a period τ ₀ based on the clocks C1 and C1'. The adder 60 includes a sampling period conversion circuit 95
Then, the adaptive reverberation sample string whose period has been returned to τ ₀ is band-limited via the frequency characteristic control circuit 24, and the fixed reverberation sample string from the accumulator 87 are added to obtain the final result. This is for outputting a series of reverberant signal samples. The zero detection circuit 37 outputs the output of the pre-memory 32.
X ₁ to X _h are each squared by the multiplier 96 to obtain X ₁ ² to
X _h ² is determined and accumulated by the adder 90 and the register 100 every clock C5, and the accumulated value within the period τ ₀ is transferred to the register 102 by the clock C1. The register 100 is also reset every period τ ₀ by the clock C1. An example of addresses of parameter data used in adaptive convolution is shown in Table 1 below. In addition to the parameter contents in part b of FIG.
0 data is added as .

[Table] Here, the delay time parameters are based on one sampling period τ ₀ of the input signal, and are stored in the form of how many of this period τ ₀ they correspond to. Next, an example of addresses of parameter data used in fixed-form convolution is shown in Table 2 below. In addition to the parameter contents in part a of FIG.
0 data is added as .

[Specific example of frequency characteristic control circuit 24]

Next, a specific example of the frequency characteristic control circuit 24 shown in FIG. 1 is shown in FIG. 15. This is composed of an FIR (finite impulse response: acyclic filter), and conceptually, for example, as shown in FIG. 16, the input signal x ₀ is delayed by one sampling period τ ₀ by a delay element 130. Then, the multiplier 132 assigns coefficients a ₁ to a ₂₀ to the delayed output of each stage (here, an example is shown in which filter characteristics are expressed using 20 sample points), and each output a ₁ x ₀
~a ₂₀ x ₀ is accumulated in the adder 134 (that is, by performing a convolution operation) to give the input signal X ₀ the characteristics of a low-pass filter. Filter characteristics are set by the values of coefficients a ₁ to a ₂₀ .
In the circuit shown in FIG. 15, this is achieved through program control using RAM in particular. Note that each control signal used in the circuit of FIG.
It is shown in Figure 7. In FIG. 17, the clock C1 is connected to the thirteenth clock.
The same signal as clock C1 in the figure, clock C7 is a signal that is generated m+1 times in one period τ ₀ of clock C1,
Clocks C8 and C9 have the same period as clock C1 τ ₀
It is a signal with In FIG. 15, the filter characteristic parameter memory 146 stores coefficients a ₁ to a _n that determine the frequency characteristics for each filter characteristic to be set (for example, the characteristics a, b, ..., i in FIG. 18). , b ₁ ~
The values _{of n ,} .

[Table] The filter characteristic selection circuit 148 selects two filter characteristics from among the filter characteristics (a to i) stored in the filter characteristic parameter memory 146. The data memory 150 has m+1 addresses, and updates the samples of the input signal in order from the address where the oldest samples are stored, and writes new samples. As a result, data memory 1
50 always stores m+1 past samples from the current time. The counter 152 instructs the write address of the data memory 150, and is counted up by the clock C1 generated every sampling period τ ₀ of the input signal, and when the count reaches m, the count is repeated from 0 again. The counter 154 instructs the read address of the filter characteristic parameter memory 146 and the data memory 150, and counts up from 0 to m in response to m+1 clocks C7 generated during the sampling period τ ₀ of the input signal. counter 1
The value of 54 is stored in the counter 152 in the subtracter 156.
is subtracted from the value of and added to the data memory 150 as an address command. The data memory 150 is switched to the write mode by the clock C8, which is generated when the value of the counter 154 is 0, and is in the read mode when the value is other than that. Therefore, in the write mode, the value of the counter 152 is directly added to the data memory 150 as a write address, and the input sample is written to that address. When the writing is completed, the data memory 150 returns to the read mode, and the counter 154 is sequentially incremented to 1, 2, . . . , m by the clock C7. Then, in the subtracter 156, the value of the counter 152 (address of the latest data) is subtracted, and one sample, two samples, ..., m samples before the current time are found within the period τ ₀ . are read out sequentially. In addition, the filter characteristic parameter memory 146
uses the value of the counter 154 as an address to calculate the coefficients (a ₁ to a _n , b ₁
~b _n ) are output sequentially in parallel. The output data of the data memory 150 is led to two systems A and B, and multipliers 158 and 160 add coefficients of the filter characteristics sequentially output from the filter characteristic parameter memory 146. Since the reading of the delay data from the data memory 150 and the reading of the coefficient of the filter characteristic from the filter characteristic parameter memory 146 are synchronized by the counter 154, the multipliers 158 and 160 have a function corresponding to the delayed data being read. A coefficient is given. The output data of the multiplier 158 is sequentially accumulated in an accumulator consisting of an adder 162 and a register 164, and the total accumulated value of m data obtained within a period τ ₀ is stored in the register 166 by the clock C1. Latched. Once the accumulated value is latched into register 166, register 164 is reset by the inverted signal of clock C1 to prepare for accumulation in the next period. The output data of multiplier 160' is similarly processed. As described above, the registers 166 and 172 output data in which the filter characteristics selected by the filter characteristic selection circuit 148 are added to the input signals, and these data are provided with crossfade coefficients x and y in the multipliers 174 and 176, respectively. be done. The crossfade parameter memory 178 is
For example, values shown in Table 4 below are stored as coefficients x and y at each address.

〔Effect of the invention〕

As explained above, according to the present invention, the sampling period for creating the reverberant signal is lengthened in accordance with the band limit of the reverberant signal, so the number of convolution points for creating the reverberant signal can be increased. , can create a more natural reverberant sound.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. FIG. 2 is a diagram showing an impulse response in a certain acoustic space. FIG. 3 is a conceptual diagram of a reverberation adding device using the impulse response of FIG. 2 as a parameter. FIG. 4 is a block diagram showing a specific example of the apparatus shown in FIG. 3. FIG. 5 is a diagram showing a region of parameters selected in conventional adaptive convolution. FIG. 6 is a block diagram showing a configuration for imparting filter characteristics to a reverberation signal. FIG. 7 is a time chart showing how the filter characteristics of the reverberation signal are sequentially changed by the circuit shown in FIG. FIG. 8 is a diagram showing the characteristics of each filter in FIG. 7. FIG. 9 is a diagram showing an example of the relationship between the frequency band of filter characteristics and the sampling period for creating a reverberation signal according to the present invention. Figure 10 shows
FIG. 3 is a diagram illustrating an example of how the number of convolution points changes as the sampling period changes according to the present invention. FIG. 11 is a diagram showing an example of a region of parameters selected according to the present invention. FIG. 12 is a block diagram showing a specific example of the reverberation adding circuit 22 shown in FIG. FIGS. 13a and 13b are diagrams for explaining the storage method of the parameter memory, respectively. FIG. 14 is a time chart showing the operation of the circuit of FIG. 12. FIG. 15 is a block diagram showing an example of the structure of the frequency characteristic control circuit 24 of FIG. 1, which is constructed using an acyclic filter. 1st
FIG. 6 is a diagram showing the principle of an acyclic filter. FIG. 17 is a time chart showing the operation of the circuit of FIG. 15. FIG. 18 is a diagram showing characteristics of each filter used in the operation of FIG. 19. FIG. 19 is a time chart showing a state in which the frequency characteristic control circuit 24 of FIG. 15 is used to sequentially change the filter characteristics with respect to the attenuating reverberant signal. 22... Reverberation addition circuit, 24... Frequency characteristic adjustment circuit.

Claims (1)

[Claims] 1. Means for creating a reverberation signal of an input signal by performing a convolution operation using a part of the impulse response as a coefficient parameter, means for band-limiting the reverberation signal, and the band-limiting. and means for increasing the number of convolution calculation points by lengthening the cycle for creating one sample of the reverberation signal.