JPS6073695A - Reverberation adder - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a device for artificially adding reverberation to a musical tone signal or the like. More specifically, the present invention relates to a reverberation adding apparatus mainly including a convolution calculation circuit that generates a reverberation signal by convolution calculation of a time function of a predetermined reverberation characteristic and an input signal.

The basic configuration of a convolution calculation circuit as a reverberation addition device is shown in FIG. The delay memory 1 stores the input signal X(t) while sequentially updating it for a predetermined period of time. As a result, the input signal X(t) is delayed by the delay memory 1. Signal taken out from delay memory 1 x 1
~X111 is input signal x ([) at time T1~T, respectively.
This is a delayed signal. Each delayed signal Xl-X
ll1 is multiplied (weighted) by coefficients (gain data) 01 to Qm in coefficient multipliers 21 to 2m, respectively, and these respective outputs are added and combined in an adder 3. In other words, the adder 3 outputs the convolution result Y shown in the following equation.

Y-1ΣQi +X+ , -1 This output Y becomes a reverberation signal.

Here, the above delay time Ti and gain data Gi (i=
1 to m) correspond to reverberation characteristics based on impulse responses as shown in FIG. In other words, when the desired reverberation is achieved with parameters Ti and Gi, 1! A time function of l is expressed and convolved with the input signal X (t ) to produce a reverberant signal Y.

The problem with this type of convolutional reverberation adding device is that the number of convolution calculation points, that is, the m points in the example shown in Figure 1, is severely restricted in terms of hardware, and it is difficult to freely increase this That's true.

In the principle configuration shown in FIG. 1, individual coefficient multipliers 21 to 2
The convolution operation is performed using m, but it is easy to understand that if the river is made larger in this case, the hardware will become enormous.

Furthermore, in practice, it is common to have a configuration in which the above-mentioned total convergence calculation is not performed using individual coefficient multipliers, but is performed by serial sequential processing.

In this case, if the river is made larger, the number of calculations that must be performed within a certain amount of time increases.Of course, there is an upper limit to m in terms of calculation speed.

The fact that the number m of convolution calculation points cannot be increased means that reverberation with a very long delay time cannot be created. In Naginara, the number of calculation points is IIIEj:t, that is, the number of parameters 7i and Qi used in the calculation is m, and it is difficult to adequately express the reverberation characteristics over a long delay time with a small number of parameters. .

This can be easily understood from FIG. If the delay time data T+ are made very consistent on the time axis, reverberation characteristics over a long time period can be expressed with a small number of parameters. However, even if this satisfies the reverberation length,
The quality of reverberation cannot be satisfied (this method is called parameter thinning). Achieving the desired natural reverberation generally requires a large number of parameters that are spaced sufficiently closely together on the time axis.

For these reasons, in most conventional systems, reverberation of only the initial delay time period of a desired reverberation characteristic is created by convolution calculation. As long as there is only a limited initial delay time period, the reverberation characteristics can be expressed with high density even with m parameters. However, in this case, the latter part (later delay time range) of the originally desired reverberation characteristics over a large time range is omitted, and it is desirable to compensate for this in some way.

This invention was made against the above background, and its purpose is to create reverberation in the initial delay time period of the reverberation characteristic using a convolution calculation circuit, and to create reverberation in the subsequent late delay time period by using a convolution calculation circuit. An object of the present invention is to provide a reverberation adding device that can obtain a more natural reverberation effect by supplementing with cylindrical hardware.

In order to achieve the above object, the present invention includes a convolution calculation circuit that generates a reverberation signal in an initial delay time period, a plurality of cascade-connected delay circuits that delay the output of this convolution calculation circuit, and a convolution calculation circuit that delays the output of the convolution calculation circuit. an adder circuit that adds the outputs of the delay circuits in each stage of the circuit and the delay circuits to obtain a composite output; and a filter inserted in a signal path from the output of the delay circuits in each stage to the final addition point by the adder circuit. It is characterized by having the following.

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 3 shows the configuration of the reverberation adding device according to the present invention. The convolution arithmetic circuit CU in the same figure has the basic configuration shown in FIG.
X(t) is applied. The reverberation signal output from the convolution arithmetic circuit CU is transmitted through a cascade-connected 0-stage delay circuit D L
It is supplied to J1 to DIJn and is delayed. The output of the convolution operation circuit CU and the delay circuits DU1 to [) of each stage
The outputs of Jn are summed and combined by n adders KUI~t<Un, and are output to the output terminal OUT. At this time, the outputs of the delay circuits DU1 to DIJn at each stage are filtered by the filters F1 to Gn before reaching the adder KUl at the final addition point.
pass through.

Specifically, the output of the first stage delay circuit DU1 is the filter F1
The output of the second stage delay circuit DU2 passes through the filters F2 and Fl, and the output of the final stage slow kE times IDUn passes through all the filters Fn -Fl, respectively RI? It is input to the addition point of the stage.

Therefore, the configuration of FIG. 3 is different from each filter F1 as shown in FIG.
~Fn is installed between the stages of each delay circuit DU1~Dun.
This is equivalent to a 6-1 configuration in which a combined output is obtained using two adders KU. Here, the output of the convolution arithmetic circuit CU is denoted as Y, the output that is delayed by the delay circuit DU1 and passed through the filter "1" is denoted as Yl, and the output that is delayed by the delay circuits DU1 and DU2 and passed through the filters F1 and F2 is denoted as Y2.

FIG. 5 shows the above-mentioned outputs Y, Y1. Y2 and their combined output are shown in the form of an impulse response waveform. The convolution calculation circuit CU outputs a reverberation signal @Y with a maximum delay time Tm with respect to the input impulse. This time m is called the convolution time.

In the waveform example shown in FIG.
It is set equal to l+.

With this setting, when the reverberation component of the convolution calculation circuit CU becomes zero, the delayed reverberation component Y1 follows without any blank time, and the reverberation component of the output Y1 disappears. When, this (continuation without creating a blank time)
A delayed reverberation output Y2 is generated. As a result, the composite output OU
As shown in FIG. 5, T is a signal with a continuous reverberation characteristic that includes the output Y of the convolution arithmetic circuit CU and the two-way outputs Y1 to Yn of each stage without any overlap or blank space.

Note that the present invention is not limited to making the delay times of each stage equal, such as the convolution time Tn+. For example, delay time D
"I' 1 is made larger than the convolution time l"m and the output Y
A blank time may be created between the reverberation components of the outputs Y and Yl, or D1'1 may be made smaller than Tm to cause the reverberation components of the outputs Y and Yl to overlap. In this way, it is preferable to appropriately set the delay time of each stage to prevent unnatural reverberation from occurring at the connection portion of the output of each stage.

Further, instead of setting the μ delay time of the delay circuit fixedly, the delay time may be changed over time. In that case, the way in which the reverberation components of the output of the subsequent stage are connected is not constant but changes randomly, so the periodicity of the reverberation components of each stage becomes inaudible, and a more natural reverberation effect can be obtained.

Next, the functions of the filters F1 to Fn will be explained. The filters F1 to Fn are generally designated as high filters. In this case, the reverberation time of the low frequency components of the input signal becomes long, and the reverberation time of the wide range components becomes short. That is, as described above, when viewed from the output terminal 0IJT, signal components with large reverberation times (delay times) have passed through the filters F1 to [n in multiple stages. The frequency characteristics of this unique reverberation are close to natural and are generally set in this way, but the present invention is not limited to this, and the filter F
It is also possible to obtain special acoustic effects by selecting various characteristics from 1 to Fn.

According to this invention, like a twin, the convolution operation circuit CU
(However, the reverberation that should follow this is created by the delay circuits DU1-DUn, the filters F1 to n45, and the filter, and repeats the reverberation characteristics in the convolution operation circuit CU.) This creates a natural reverberation that lasts for a very long time.

Next, a specific example of the configuration of the convolution arithmetic circuit CLJ will be explained in detail with reference to FIGS. 6, 7, and 8.

The convolution calculation circuit CU shown in FIG. 6 uses an input signal X (
a data memory 23 that sequentially stores predetermined samples of t), a parameter memory 20 that stores reverberation characteristics corresponding to the impulse response of a virtual room, etc., and performs a convolution operation according to the data in both memories 20 and 23 to generate a reverberation signal. A convolution operation means for obtaining OUT is provided.

The data memory 23 enters the write mode every time the clock C2 with a period T outputted from the timing controller 1 roller 32 is generated, and the output of the counter 24 incremented by the clock C1 with the same period T is given as a write address. (Note that the output of the counter 24 is given via the subtracter 27, and the subtraction input at this time is O, as will be described later).

In other words, the input signal X (t) is sequentially input to and output from the data memory 23 at a constant sampling rate, and a predetermined number of latest ripple data x 1 to Xj (XI,
X2...) are stored while being updated sequentially.

In the parameter memory 20, the impulse response characteristics shown in FIG. 2 are stored in the data format shown in FIG. One parameter consists of delay time data Di and gain data G21 (i...1 to 1) 1), which includes delay time data Di at m points on the time axis and gain data corresponding to each point. Desired reverberation characteristics are expressed by Gi. The parameter memory 2 has m-11 addresses, data 0 is written to the first address O, and parameters l)i and Qi are stored in the subsequent addresses in order (note that the Do data O, G
o).

The delay time data Di here is given as an integer value indicating how many times the sampling period T of the input signal is. In other words,
Dixi--Ti.

Writing of this parameter is performed by the controller 22 in advance. Note that the multiplexer 26 connected to the address input of the parameter memory 20 is selected by the controller 22 when the controller 22 writes data. Under other normal operating conditions, counter 25
The output of is applied to the parameter memory 20 via the multiplexer 26 as a read address.

The counter 25 is cleared by the clock C4 generated immediately after the first clock C1, and the counter 25 is cleared by the clock C4 generated immediately after the first clock C1,
II] Clock C5 with a period of 1/(m→1) of 'T-
The coefficient output is given to the parameter memory 2 as a successive address. Therefore, data stored in the parameter memory 20 is sequentially read out every sampling period T. The delay time data Di among the parameters read from the memory 20 is the subtraction input of the subtracter 27. Further, the gain data Qi is input to the multiplier 28 and multiplied by the data Xi read out from the data memory 23 as described later. The multiplication output is input to an accumulator 29 consisting of a tightener 30, a register 35, and an AND circuit 31.

To be more specific, as shown in FIG.
l becomes 1-level and the counter 25 is cleared.

Therefore, the address O is designated by the output of the counter 25 in the parameter memory 20, and the data D stored at the address O as described above is stored in the parameter memory 20.

=O, Go=O is read.

Then, when the next clock C5 rises, the clock C2 also rises, and the data memory 23 enters the write state. At this time, since the output of the parameter memory 20 is O, the subtracter 2
7) is the output of the counter 24 itself. Therefore, the input signal X(t> at this time is 11 inputted to the address indicated by the output Ak of the counter 24. This is the latest sample data X1, and similarly, the latest past sample data x1 to Xj are the data It is stored in the memory 23.

When writing of the 1'+l sample data to the data memory 23 is completed, the data memory 23 enters the read mode. Also, until the next rising edge of clock C1, counter 25
is stepped in synchronization with the clock pulse C5, address n of the parameter memory 20 is sequentially specified, and parameters Di and G are sequentially read out.

When the delay time data Di is output from the parameter memory 20 or 13-, the value Ak-[)i obtained by subtracting Dl from the output Ak of the counter 24 is output from the subtracter 27, and this becomes the read address of the data memory 23. The corresponding data is read out from the memory 23.

Address 8 of the data memory 23 is the storage address of the latest sample data X1, and address Ak
-Di is the storage address of past sample data Di times. The sample data read from -Di is added to this address 8 by 1. This data Xi is data obtained by delaying the input signal X(t) by a time Ti = l) i xT tJ.

The above delayed data read from the data memory 23×
1 is a parameter memory 2 along with delay time data Di.
The multiplier 28 multiplies (weights) the gain data Gi read from 0. The output Gi xXi of the multiplier 28 is input to an accumulator 29.

The accumulator 29 sequentially accumulates the output ()GiXXi of the multiplier 28 using the adder 30 and the register 14-star 35 in synchronization with the clock C5. Immediately after the next rise of clock C1, the cumulative result for one cycle is Y-ΣGi
xXi is obtained, which becomes the reverberation signal output OUT.

Thereafter, during the period when the output of the counter 25 becomes 1, the clock C3 becomes L level, and this causes the A of the accumulator 29 to become low.
ND circuit 31 is cut off. In other words, accumulator 29
The contents of -U are cleared at this point, and the accumulation for the next cycle is started again.

Next, a specific circuit configuration including one delay circuit DUi and a filter Fi based on the configuration of FIG. 4 will be described with reference to FIG. 9.

In FIG. 9, the input signal In is input to the delay memory 60 and written to the address specified by the output of the counter 65, which is incremented by the aforementioned clock signal C1 of period T. When the output of the counter 65 is set to Al1, the delay memory 60 is controlled to read the data written to the address Ap immediately before writing the input to the address Ap. Therefore, from the delay memory 60, signals delayed by the input signal IN by the capacity of the memory 60 are sequentially outputted in a periodic manner. This is the configuration of the delay circuit DUi.

The delay data output from the delay memory 60 is supplied to a filter "i" consisting of multipliers 61 and 62, an adder 63, and a register 64.
In response to this, the old data corresponding to one cycle lower is latched. If the output of the delay memory 60 is Yp, the register 64 outputs Yp-1 one cycle before. The signal Yp is multiplied by a coefficient Δ0 in a multiplier 61, the signal Yp-1 is multiplied by a coefficient A1 in a multiplier 62, and the results are multiplied by an adder 63.
are added to form the output signal OUT. This is a well-known first-order filter configuration.

FIG. 10 shows a modification of the delay circuit part in FIG. ). When writing the input signal IN to the delay memory 60, the output of the counter 65 becomes the address input of the delay memory 60 via the multiplexer 69. However, when data is read immediately before writing, the address is determined by adding the data stored in the register 67 and the output of the counter 65 to an adder 68.
The added value is given via multiplexer 69. Random data generated from the random number generator 66 is latched into the register 67 in synchronization with the clock C9. The period of this clock C9 is equal to the above-mentioned convolution time of the convolution calculation circuit CU. Further, the random number generator 66 operates at a cycle sufficiently faster than the convolution time Tm, and generates, for example, M-sequence random numbers. As a result, the delay time caused by the delay memory 60 changes randomly to the convolution time Tmf7j.

As explained in detail above, according to the reverberation adding device according to the present invention, by adding relatively simple hardware to the convolution calculation circuit, it is possible to realize natural reverberation characteristics over a sufficiently long time period. I can do it.

[Brief explanation of drawings]

17- Fig. 1 is a block diagram showing the principle configuration of a convolution calculation circuit, Fig. 2 is an explanatory diagram of the time function of reverberation characteristics due to impulse response, and Fig. 3 is a basic diagram of the reverberation adding device according to the present invention. FIG. 4 is a block diagram showing another embodiment of the present invention equivalent to FIG. 3, FIG. 5 is an explanatory diagram of the operation of the device shown in FIG. 4, and FIG. FIG. 4 is a block diagram showing a specific configuration example of the convolution arithmetic circuit CU, FIG. 7 is a timing chart h for explaining the operation of the device in FIG. 6, and FIG. An explanatory diagram showing the contents of the memory 20, FIG. 9 is an explanatory diagram showing the contents of the memory 20 (
10 is a block diagram showing a modification of FIG. 9. FIG. 10 is a block diagram showing a modification of FIG. 9. CU...Convolution operation circuit DU1~DUn...Delay circuit F1~Fn...Filter KU1~KUn---Adder 18-

Claims (1)

[Claims] (1) A convolution calculation circuit that generates a reverberation signal by convolving an input signal with a time function of a predetermined reverberation characteristic; A plurality of cascade-connected delay circuits that delay the output of the convolution calculation circuit; The above convolution calculation circuit and - an adder circuit that adds the outputs of the delay circuits at each stage described in F to obtain a composite output; A reverberation adding device characterized by comprising: and;