JPH0410045A - Microprocessor - Google Patents

Abstract

PURPOSE:To omit an external bus control circuit and the bus synchronizing signal provided from the external and to attain the bus transfer at a high speed by providing a bus synchronization timing generating circuit into a microprocessor and varying the timing for synchronization of buses. CONSTITUTION:A microprocessor includes a bus synchronization timing generating circuit consisting of a register 21 which sets programmably the bus synchronization timing, a counter 22 which is updated for each clock supplied from outside and counts the duration of working, and a comparator 23 which compares in sequence the values set to the register 21 and the counter 22 with each other and produces a bus working end signal to secure the coincidence of buses. Then the timing for synchronization is varied. As a result, an external bus control circuit can be omitted and at the same time no external bus synchronizing signal is required neither. Thus the high speed bus transfer is attained and a synchronous bus can be offered to any equipment connected to the bus regardless of the timing types of the equipment.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a microprocessor that transfers data using a bus.

(Prior Art) Due to recent advances in semiconductor technology, microprocessors, memory LSIs, and peripheral control LSIs have become available at very low prices, and by simply combining these as appropriate via a bus, relatively high-performance microprocessors can be created. You can now build processor systems.

By the way, the bus data transfer method is synchronous.

There are two types of asynchronous methods. A synchronous bus is uniquely determined by the microprocessor that controls the bus, and peripheral devices that are connected to the bus and have different timings may need to have registers inserted between the bus and the device to match the timing. control is necessary. FIG. 5 shows the connection configuration. In the figure, 51 is a macro processor;
52 is a main memory, 53 is an input/output device, 54 is an input/output register, ADH is an address bus, and DAT is a data bus.

Additionally, an asynchronous bus must have an address decoder to detect devices with different timings connected to the bus, and a bus synchronization signal to the microprocessor to generate bus timing that matches the timing of the device recognized by decoding. Must be. As the synchronization frequency of microprocessors increases, it has become much more difficult to generate this bus synchronization signal. FIG. 6 shows the connection configuration.

In the figure, 61 is a microprocessor, 62 is a main memory, and 63 is a microprocessor.
1 is an input/output device, and 64 is an address decoder and a bus timing generation circuit.

(Problems to be Solved by the Invention) The conventional bus synchronization method described above requires a circuit that is complex and difficult in terms of timing for bus-connected devices, which is expensive and has a negative effect on processing speed.

This invention was made in view of the above circumstances, and by providing a circuit that generates bus synchronization timing inside a microprocessor and making the clock timing variable, it is possible to achieve high-speed data transfer via a bus and an external bus control circuit. The purpose is to provide a means to omit it.

[Structure of the Invention] (Means and Effects for Solving the Problems) The microprocessor of the present invention includes a timing register in which bus synchronization timing is fully set by the programmer;
A counter that is updated every clock that arrives from the outside and measures the operation duration is successively compared with the values set in the above register and counter, and when they match, a bus operation end signal is generated and the bus is synchronized. It consists of a bus synchronization timing generation circuit consisting of a bus synchronization timing generator, and is characterized in that the timing for synchronization is variable. Another feature is that a specific value is written to a specific address in an externally connected memory, the value is read during the initialization stage, and compared with the value in the timing register above, and when they match, bus synchronization timing is generated. do. Furthermore, it has a first table that stores synchronization timing values, and by indexing this table when a bus transfer is requested, it is possible to select the value to be set in the timing register and perform bus transfer with devices that have different timings. Features. and a second one that stores a timing value that increases when the timing is different.
The timing select signal that arrives from the outside allows bus synchronization with the basic timing count value according to the contents of the first table, or the incremental timing obtained by indexing the second table. Another feature is that it is possible to select whether to perform bus synchronization using a timing value obtained by adding a count value to a basic timing count value, and to perform synchronization using either one of the bus timings.

This provides the effects listed below.

(1) No external bus control circuit is required.

(2) High-speed bus transfer is possible because a bus synchronization signal applied from the outside is not required.

(3) A synchronous bus can be provided to devices with any timing that are connected to the bus.

(Example) Hereinafter, an example of the present invention will be described in detail using the drawings. 1 to 4 are block diagrams each showing an embodiment of the present invention. First, the embodiment shown in FIG. 1 shows the internal configuration of a basic microprocessor with a built-in bus synchronization timing generation circuit. A bus control circuit 1 receives a bus transfer request generated inside the microprocessor/system and transfers data with an externally connected device (not shown).

The bus synchronization timing generation circuit 2 receives the bus transfer request at the same time as the bus control circuit 1 . The inside of the bus synchronous timing control circuit 2 is shown in a circle indicated by a dashed line. A predetermined synchronization timing time is set in advance in the timing register 21, and the timing counter 22 starts measuring time at the same time as receiving the bus transfer request, and the timing counter 22 starts measuring the time, and the time matches the contents of the timing register 21 (comparator 23).
and sends a timing control signal to the bus control circuit to end the data transfer. Upon receiving the timing control signal, the bus control circuit 1 ends the data transfer. In addition, in the figure,
3 is an instruction decoder, and 4 is an arithmetic processing unit.

In the embodiment described above, a predetermined value must be set in the timing register 21 in advance, or in the embodiment shown in FIG. 2, the microprocessor can automatically set the data transfer timing with the device. The embodiment shown in FIG. 2 will be explained as follows. Specific data is written to a specific address on the main memory 6 connected to the outside. During initialization after reset, the microprocessor reads data at that specific address.

In this case, an initial value is set in the timing register 21 shown in FIG. If the read data is not recognized as specific data by the data detection circuit 5, the value of the timing register 21 is increased again, the specific address of the main memory 6 is read, and it is determined whether the data matches the specific data. .

When specific data is detected while repeating this operation,
The subsequent bus synchronization timing is performed at the synchronization timing at which the specific data is detected.

Next, in the above example, the bus synchronization timing becomes unique. The configurations in Figures 3 and 4 each have a table that stores synchronization timing values internally, generate a timing count value to be set in the timing register in Figure 1, and perform bus transfer with devices that have different timings. This is an example of doing this. The timing count table 60 shown in FIG. 3 is searched using the bus address output to the internal bus at the time of a bus transfer request generated from inside the microprocessor, the corresponding timing count value is read out, and set in the timing register 21. This makes it possible to transfer data with devices that have different timings set on the bus. This timing table 6
0 may be implemented in non-volatile memory on the microprocessor, or may be read from external storage. Alternatively, it may be set by software.

In the above example, identical devices connected to the bus can only have unique timings. This is inconvenient for a main memory with a cache memory or a main memory whose timing differs depending on the dynamic RAM refresh operation. Fig. 4 has a timing count table that stores basic bus timing values and a second timing count table that stores timing values that increase when the timing is different, and that is determined by a timing select signal from outside the microprocessor. This is an example in which it is possible to select whether bus synchronization is performed using a basic timing count value or using a timing value obtained by adding an increased timing count value to the basic timing count value. Therefore, two tables (6
01, 602), adder 603 and selector 6
04 is required. This example also enables bus synchronization of devices with different timings within the same device.

[Effects of the Invention] As explained above, according to the present invention, the following effects can be obtained.

(1) An external bus control circuit becomes unnecessary.

(2) High-speed bus transfer is possible because no external synchronization signal is required.

(3) A synchronous bus can be provided to devices with any timing that are connected to the bus.

[Brief explanation of drawings]

FIGS. 1 to 4 are block diagrams showing the configuration of an embodiment of the present invention, and FIGS. 5 and 6 are block diagrams showing the conventional configuration, respectively. DESCRIPTION OF SYMBOLS 1... Bus control circuit, 2... Bus synchronization timing generation circuit, 21... Timing register, 22... Timing counter, 23... Comparison circuit, 60... Timing count table.

Claims (4)

[Claims] (1) A microprocessor characterized in that the microprocessor is provided with a bus synchronization timing generation circuit having the following configuration inside the microprocessor, and the timing for synchronization is variable. a) Timing register in which bus synchronization timing is programmably set. b) A counter that is updated every time a clock arrives from the outside and measures the operation duration. c) A comparator that successively compares the values set in the register and counter, and when they match, generates a bus operation end signal and synchronizes the bus. (2) A specific value is written to a specific address of an externally connected memory, the value is read during the initialization stage, and compared with the value in the timing register, and when they match, bus synchronization timing is generated. The microprocessor according to claim (1). (3) It has a first table that stores synchronization timing values, and when a bus transfer is requested, by indexing this table, the value to be set in the timing register is selected, and bus transfer is performed with devices that have different timings. The microprocessor according to claim 1, characterized in that: (4) Have a second table that stores timing values that increase when the timings are different, and perform bus synchronization using the basic timing count value according to the contents of the first table using a timing select signal that arrives from the outside. , select whether to perform bus synchronization using the timing value obtained by adding the incremental timing count value obtained by indexing the second table to the basic timing count value, and synchronize using either one of the bus timings. 4. The microprocessor according to claim 3, characterized in that: