JPH04100093A - Lcd display control system - Google Patents

Abstract

PURPOSE:To improve display quality by temporarily storing a video signal inputted at CRT timing in a memory and reading it out so that the display of an LCD is performed as long as possible. CONSTITUTION:Based on the serial video signal inputted at the CRT timing, the CRT 6 is driven to perform display and the video signal is temporarily stored in them memory 2, then it is successively read out from the memory 2 by one picture element(or plural picture elements) in synchronism with a display clock 1-1 and the LCD 3 is driven to perform display. It is successively read out from the memory 2 by one picture element(or plural picture elements) in synchronism with a display clock 1-2 as many as the number of LCD simultaneous display lines and the LCD 3 is driven so that plural lines are simultaneously displayed. Therefore, the serial video signal is displayed on the CRT 6 and successively read out from the memory 2 based on the display clocks 1-1 and 1-2 so as to drive the LCD 3 to perform display, so that the CRT display is performed and the display driving time of the LCD 3 is made as long as possible, and the display quality is improved.

Description

[Detailed description of the invention] [IA required] LC that displays CRT timing video signals on LCD
Regarding the D display control method, the video signal input at the CRT timing is temporarily stored in the memory, and is read out and driven so that the LCD is displayed as long as possible within the time between the vertical synchronization signal 2 of the CRT timing, The purpose is to improve the display quality of the LCD that is displayed simultaneously with the CRT, and the video signal input at the CRT timing is controlled to be displayed on the CRT based on the vertical synchronization signal ■a and horizontal synchronization signal H of the CRT timing. , the time between the vertical synchronization signals V of the CRT timing is divided by the number of lines (or the number of lines - 1), and the divided time is divided by the number of pixels in the line direction (or the number of pixels simultaneously displayed in the line direction). After generating a display clock and temporarily storing the video signal inputted at the CRT timing in a memory, it sequentially reads lWJ pixels (or multiple pixels) from this memory in synchronization with the display clock to drive the LCD for display. Configure.

[Industrial application field]

The present invention relates to an LCD display control method for displaying a CRT timing video signal on an LCD.

[Problems to be solved by conventional technology and invention] Conventionally, C
When displaying RT and LCD (liquid crystal) simultaneously in parallel, is it possible to use the CRT interface to make the LCD the display side? I was in BL. For this reason, it depends on the display timing of the CRT, and during the display period shown in the shaded area in FIG. 7(A), the LCD cannot be driven at the optimum timing. The problem was that I couldn't do it. Specifically, the LCD has a property that the shorter the vertical retrace time, the less flickering occurs and the display quality can be improved. Further, the longer the horizontal display time, the more the brightness can be improved. Due to these characteristics, in the conventional CRT display timing determined from the characteristics of CRT, the vertical retrace period is too long, as shown in Figure 7 (B) vertical timing, and furthermore, as shown in Figure 7 (C), the display timing is too long. As shown, if the horizontal synchronization signal *H8 was used as it was for *LOAD of the LCD, the horizontal display timing would be too short, resulting in a problem that the display quality of the LCD would deteriorate.

The present invention temporarily stores the video signal inputted at the CRT timing in a memory, and drives the LCD by readout so as to display it as long as possible within the time between the vertical synchronization signal V of the CRT timing. The purpose is to improve the display quality of the LCD that displays at the same time.

The time between the screen sync signals (number of lines on the entire screen/LC)
D (the number of simultaneously displayed lines), and the divided time is divided by the number of pixels in the line direction (or the number of simultaneously displayed pixels in the line direction).

The memory 2 is a memory for storing Norial video signals input at CRT timing, reading out pixel data based on display clocks 1 to 1.1-2, and performing timing conversion.

[Means to solve the problem]

Explain the means to solve the problem with reference to the first section.

In FIG. 1, the display clock 1-1 divides the time between the vertical synchronizing signals V of the CRT timing by the number of lines (or the number of lines + 1), and divides the divided time by the number of pixels in the line direction (or the number of pixels in the line direction). (number of simultaneously displayed pixels)
This is the clock divided by .

The display clock 1-2 is a function of the CRT timing. As shown in FIG. 1, the present invention drives the CRT 6 for display based on a serial video signal input at the CRT timing, and is stored in the memory 2, and then sequentially read out from the memory 2 one pixel (or multiple pixels) at a time in synchronization with the display clock 1-1, and then the LC
Drive D3 for display. Also, regarding the number of lines simultaneously displayed on the LCD in synchronization with the display clock 1-2 from the memory 2,
Sequential reading of lWJ elements (or multiple pixels), LC
D3 is driven to display multiple lines at the same time.

Therefore, by displaying the serial video signal on the CRT 6 and sequentially reading it out from the memory 2 based on the display clock 1-1.1-2 and driving the LCD 3 for display,
In addition to CRT display, it is possible to improve the display quality by extending the display drive time of the LCD 3 as much as possible.

〔Example〕

Next, the configuration and operation of one embodiment of the present invention will be explained in detail using FIGS. 1 to 6.

In FIG. 1, an LCD display control unit (LCD display control control SI) 1 inputs a video signal of CRT timing and controls the LCD 3 by using the time between vertical synchronization signals V of CRT timing as effectively as possible. It controls the display and is composed of 1-1 to 1-7.

The display clock 1-1 divides the time between the vertical synchronizing signal V of the CRT timing and the next vertical synchronizing signal ■ by the number of lines, and divides the divided time by the number of pixels in the line direction or multiple pixels in the line direction. When displaying simultaneously, the clock has a time divided by the number of pixels simultaneously displayed.

The display clock 1-2 divides the time between the vertical synchronizing signal V of the CRT timing and the next vertical synchronizing signal V by (number of screen display lines/number of LCD simultaneous display lines), and divides the divided time in the line direction. When simultaneously displaying a number of pixels or a plurality of pixels in the line direction, this clock has a time divided by the number of pixels simultaneously displayed, and is a clock for displaying a plurality of screens on the LCD 3 at the same time.

Gradation control SJi! 51I control section 1-3 is tone control LSI
4 and generates ia data (for example, gradation data of 1 pixel and 1 dot) from the image data (for example, 4-bit image data of GRBI).

The display data generating section 1-4 generates image data to be displayed (for example, GRBI 4-bit image data) from a CRT timing video signal (for example, an RGB 12-pin video signal).

The buffer memory control unit 1-5 includes D
It controls the P memory SAM21 and the DP memory RAM2-2, and controls writing and reading of gradation data.

The display data recombination control section 1-6 performs recombination of the pixel data read from the memory 2 so as to display the data one line at a time on the upper and lower sides on the LCD 3 (see the fifth circle).

LcI)@key signal generation unit 1-7 generates a display drive signal for driving the LCD 3 to display.

Memory 2 is a dual port memory (DP), and includes a DP memory SAM2 in which serial gradation data is written.
-1, and the gradation data stored in this DP memory SAM2-1 can be transferred and stored in blocks, and the stored data can be read in parallel to the P memory RAM2-2.
It consists of:

LCD3 is a liquid crystal.

The gradation control LSI 4 converts image data (for example, GBR■ 4-bit image data) into serial [1 data (for example, 1
gradation data of one pixel) is generated.

The CRT display control section 5 displays an image on the CRT 6 based on the video signal of the CRT timing.
It is composed of an RT control section 5-1 and the like.

FIG. 2 shows a conceptual explanatory diagram of the present invention.

FIG. 2(a) shows a division explanatory diagram. Here, LCD3
It is assumed that the screen is composed of the number of lines n×the number of pixels m.

FIG. 2(b) shows vertical timing. Here, CR
T timing vertical synchronization signal *V and next vertical synchronization signal *
The time between V and V is the time (period) per screen.

The conventional CRT display displays only when CRT-ON in the figure is "1".

On the other hand, in the LCD display according to the present invention, LCD0N in the figure is “
1" time (the time from the vertical synchronizing signal *V to the next vertical synchronizing signal *v length), and
It is displayed for a longer time than the actual display, and the retrace period (period when it is not displayed) is shortened.

FIG. 2(C) shows horizontal timing. Here, L.C.
The horizontal timing to display D3 is determined by *LOAD in Figure A. This 1kLOAD is as shown in Figure 2 (b) LCD-
The time when ON is 11” (for example, display area + 1 line (second
The time from the vertical synchronizing signal *■S to the next vertical synchronizing signal *■S is divided by (number of LCD drives m-1) shown in figure (a), and the display area is divided from among these divided times. Regarding the line time), the pixels of the LCD 3 are sequentially, so to speak, continuously driven for LCD display in the line direction. Yabuta, in the case of two-screen drive (in the case of screen drive that displays sequentially from the top edge to the center of the LCD 3 and sequentially displays from the center to the bottom edge at the same time), *LOAD is as shown in Figure 2 (b) LCD ~ ON is 1°, the display area 3j3/
Divide the time from the vertical synchronizing signal *vS to the next vertical synchronizing signal *vS by 2 + 1 lines (shown in Figure 2 (a) (number of LCD drives m/2-1)), and divide the time between these divided times. The LCD display is sequentially driven in the line direction for the time of the line in the display area @/2 from the beginning.

As described above, regarding the time from the vertical synchronizing signal umbrella V of the CRT timing to the next vertical synchronizing signal *■, the LCD3
By dividing the screen based on the number of display lines and devoting as much time as possible to driving the LCD display,
Compared to the conventional display that relies on CRT timing, it is possible to minimize the vertical retrace period and reduce flutter, and to maximize the horizontal period
It becomes possible to improve the brightness of CD3. 3rd below
2 dual port memory using leap or 6th
The configuration and operation when using (DP memory) will be explained in detail.

FIG. 3 shows an operational waveform diagram of the present invention.

FIG. 3(a) shows a waveform diagram of serial write to the DP memory SAM. This shows the waveform when serial gradation data in FIG. 1 is written into the DP memory SAM2-1 which is the memory 2.

In Figure 3 (a), *H8 is the horizontal synchronization signal of CRT timing, CRT-O
N is a period during which the image data at the CRT timing is significant; the image data is the image data (for example, GRB I
4-dot image data), the gradation data is the data after the gradation control LSI 4 converts the image data into data of 1 pixel and 1 dot, for example. This is the DP memory SAM2-1 in the figure.

As shown in Figure 3 (a), the CRT timing C
During the RT-ON period, the CRT display data generation unit 1-4 in FIG. 1 generates image data (for example, GRBI 4-dot image data) from a CRT timing video signal (for example, an RGB 2-pint video signal). Further, from this image data, the gradation control LSI 4 in FIG. 1 generates serial gradation data (for example, gradation data of one pixel and one dot), and sequentially writes it into the DP memories SAM2-1 in serial.

FIG. 3(b) shows block transfer from the DP memory SAM2-1 to the DP memory RAM2-2.

Here, CRT-ON (Figure 3 (a) CRT-ON)
Serially write the gradation data for two lines into the DP memory SAM2-2 as shown in the figure, and collectively transfer the gradation data for the two lines to the DP memory RAM 22 in a block (see section 6). .

FIG. 3(c) shows an LCD read cycle.

This is the CR within the period of one screen from the vertical synchronizing signal *Vs of the CRT timing to the next vertical synchronizing signal *vS.
Regarding T6, display control is performed using the period of the illustrated CRT-〇N determined by conventional standards (for example, NTSC), while regarding LCD3, according to the present invention, the display is controlled using two lines according to FIGS. DSP memory R
From the gradation data written to AM2-2, the illustrated LCD-
Display control is performed by sequentially reading the longest possible period of 0N. As a result, when the LCD display limit is 0, the display side aI1 period becomes longer, making it possible to reduce flicker and increase brightness.

Figure 4 shows data from DP memory SAM2-1 to DP memory RA.
A block transfer waveform diagram to M22 is shown.

Here, the write cycle is the DP memory SAM2 in FIG.
-1 to DP memory RAM2 2.

This is a cycle for transferring data. The read cycle is a cycle in which pixel data is read in parallel from the DP memory RAM 2-2 in FIG. This read pixel data is used for recombination in the display data recombination control section 1-6.
The 5th screen is temporarily stored on the N sofa for simultaneous display of two screens.
(see figure). Note that *RAS and *CAS are DP memory RAM
This is an address signal for supplying an address signal for accessing the dynamic RAM forming part 2-2 in two parts. TR/○E is a transfer/output enable signal. *WE is the write signal, *SE
is the real enable signal.

WTREQ is a write transfer request signal.

FIG. 5 shows a display data recombination waveform diagram of the present invention.

Here, as the DP memory, two 25
Using 6KB dual port RAM, 2 lines are simultaneously displayed from the top line to the center and from the center line to the bottom edge of the LCD screen, and 4 pixels are taken in each line direction and displayed on the LCD 3. Display simultaneously. Therefore, pixel data destination -1 is the 1st pixel to the 4ith pixel of the 1st line.
! ii element, 1-5 is the 5th pixel of the 1st line L'
L represents the 8th pixel. Similarly, the pixel data 24L1 is 2
41 represents the first to fourth pixels of line 24
1-5 L represents the 5th to 8th pixels of the 241st line.

This will be explained below.

(1) From the 256KB dual port (Figure 6) RAM by READEN (read enable) in
The 4-bit pixel data is read out as shown in (1-1) and (1-5).

(2) The IIBMDLT (read data raft clock) in (■) converts the image data of (1) 1-1 of (1), 1 = 5 of (2) read in (1) to the image data of (2)? 1-1 of 1SID7-4 (memory shift 1 data 7-4) and MSl[13 of
As shown in 1-5 of 0 (memo 1st data 3-0), G is stored in the recombination buffer of the display data recombination control unit 1-6 in FIG. 1 (first half image data 1-1.
15 in the buffer). Similarly, in C2, the second half of the image data 241-1, 241-5 is stored in 71 years in the next cycle (2414 in ■ and 241-5 in ■) are stored each year.

(3) o's tiLDLT (display pool clock)
Then, the display data indicated by diagonal lines in the figure, for example 1-1 of Lf■, 241-1 of
(1st pixel to 3rd pixel of 1st line), 241-1
(the first pixel to the third pixel on the 241st line) are simultaneously driven for display. Similarly, in the next step, @1-5,
Lunch 241-5 of [phase] and use it 1. zte LC
1-5 of D3 (5th pixel to 8th pixel of 1st line)
, 241-5 (the fourth pixel on the 241st line) to the eighth pixel) are simultaneously driven for display. Thereafter, simultaneous display driving is performed in the same manner.

By the above display data recombination control, two 256
The display data read sequentially from the KB dual port RAM is temporarily stored in buffer 1 (shift register), and the display data is taken out from there and transferred in the line direction from the top edge of the LCD 3 toward the center, and from the center to the bottom edge in the line direction. It becomes possible to sequentially and simultaneously drive display in units of four pixels.

FIG. 6 shows an example of a dual port RAM. As mentioned above, this includes two 256KB dual port RAMs.
This is the case when using . Here, (1) Among the two lines of serial tone data explained in FIG.
-3.1-4 is stored in one SAM, and gradation data 1-5.1-6.1-7.1-8 is stored in another SAM. (2) Regarding the two lines of gradation data stored in these SAMs, the entire data is transferred to the RAM by the write transfer described above in Figure 4.
-3+ 1-4 and 1-5.1-6.1-7.1-8
Store as shown. (3) From the gradation data stored in the RAM, as shown in 1-1 and 1-5 of Fig. 5, Stored in Hanwha for string replacement. and,
The gradation data of the shaded part in Fig. 5, for example l-1,
241-1 is read out and used as display data, and the LCD 3 is simultaneously driven for display. As a result, 4
It becomes possible to simultaneously display in WJ elementary units.

〔Effect of the invention〕

As explained above, according to the present invention, the CRT is driven for display based on the video signal of the CRT timing, and
This video signal is temporarily stored in the memory 2, and a display clock generated from the time between the vertical synchronization signals V of the CRT timing is sequentially read out from the ζ2 memory 2 to drive the LCD 3 for display. Therefore, display quality can be improved by lengthening the display drive time of the LCD 3 as much as possible. This reduces the vertical vA period,
It is possible to reduce the flicker and increase the horizontal period to lengthen the horizontal LCD display drive M darkness,
It is possible to increase the brightness of a CD.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of one embodiment of the present invention. FIG. 2 is a conceptual diagram of the present invention. FIG. 3 is an operational waveform diagram of the present invention. FIG. 4 is a SAM→RAM block transfer waveform diagram. Display data recombination waveform diagram FIG. 6 shows an example of a dual port RAM, and FIG. 7 shows an explanatory diagram of the prior art. In the figure, 1: LCD display control section 1-1.1-2: Display clock 1-4: Display data generation section 1-5 = Backup memory control section 1-6 = Display data recombination control section 1-7: LCD *J control signal generation section 2: Memory 2-1: DP memory SAM 2-2: DP memory RAM 3: LCD (liquid crystal) 4: Gradation control LSI 5: CR7 display control section 6: CRT Patent applicant Pfn Co., Ltd.

Claims (2)

[Claims] (1) In the LCD display control method that displays the video signal at CRT timing on the LCD, the video signal input at CRT timing is displayed on the CRT (6) based on the vertical synchronization signal V and horizontal synchronization signal H at CRT timing. In addition to controlling the display, the time between the vertical synchronization signals V of the CRT timing is divided by the number of lines (or the number of lines + 1), and the divided time is divided by the number of pixels in the line direction (or the number of simultaneously displayed pixels in the line direction). Generates a divided display clock (1-1) and stores the video signal input at CRT timing in memory (2-1).
) and then sequentially read out one pixel (or multiple pixels) from this memory (2) in synchronization with the display clock (1-1) to drive the LCD (3) for display. Characteristic LCD display control method. (2) Divide the time between the vertical synchronizing signals V of the CRT timing by (the number of lines of the entire screen/the number of simultaneously displayed lines on the LCD), and divide the time divided by the number of pixels in the line direction (or the number of simultaneously displayed pixels in the line direction). 1 pixel (or multiple pixels) for the number of simultaneous display lines of the LCD, in synchronization with this display clock (1-2) from memo 1 (2) above. The LCD display control system according to claim 1, characterized in that the LCD (3) is configured to read data sequentially one by one and drive the LCD (3) to display a plurality of lines at the same time.