JPH0399520A - A/d converter - Google Patents

Abstract

PURPOSE:To reduce an influence of offset with a simple constitution by outputting the analog signal, whose polarity is inverted with a prescribed period, from a modulating circuit to demodulate an A/D-converted digital signal. CONSTITUTION:The analog signal whose polarity is inverted with a prescribed period is outputted from a modulating circuit 3 by a chopper. The signal is amplified in an amplifier 5 by the control of a clock generator and is supplied to an A/D converter 6. When a voltage Vc(N) of a first digital signal Pc obtained from the converter 6 has a DC offset OF(N)N. Vc(N) is expressed with a formula I. A voltage Vd(N) of a second digital signal Pd outputted from a demodulating circuit 7 is expressed with a formula II. Offset components OF(2m) and OF(2m+1) are the frequency component of a half of 80kHz sampling frequency, namely, 40kHz frequency in this case and are eliminated by an LPF 8.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to an A/D conversion device.

[Summary of the invention]

The present invention relates to an A/D conversion device, in which a first analog signal is supplied to a modulation circuit consisting of a chopper, a second analog signal whose polarity is inverted at every predetermined period is output, and the second analog signal is The first signal is supplied to the A/D conversion circuit.
A digital signal is output, the first digital signal is supplied to the demodulation circuit and demodulated, and the second digital signal is output, thereby simplifying the configuration.
This is intended to reduce the influence of offset in A/D conversion.

[Conventional technology]

Conventional A/D conversion circuits include fresh type, two-step refresh type, successive approximation type, series-parallel type, series type, integral type, double integral type, multiple integral type, high-speed integral type, and oversampling delta type.・There are various types such as sigma modulation type.

Incidentally, Japanese Patent Application No. 63-24038 can be mentioned as a conventional example of a parallel type A/D conversion circuit using a chopper type comparison circuit.

[Problem to be solved by the invention]

In this way, there are various types of conventional A/D conversion circuits, but in any case, the analog cog signal is supplied to the A/D conversion circuit and converted into a digital signal, including direct current. In this case, it is necessary to provide an automatic zero adjustment circuit and to design the circuit to have good stability, which results in an increase in price.

In view of this, the present invention provides an A/D converter that can simplify the configuration and reduce the influence of offset in A/D conversion.
This paper attempts to propose a D-conversion device.

[Means to solve the problem]

The A/D conversion device according to the present invention includes a modulation circuit (3) comprising a chopper to which a first analog signal is supplied and a second analog signal whose polarity is inverted at predetermined intervals is output.
, an A/D conversion circuit (6) to which the second analog signal from the modulation circuit (3) is supplied and a first digital signal is output, and a first digital signal from the A/D conversion circuit. and a demodulation circuit to which a signal is supplied, demodulated, and a second digital signal is output.

[Operation] According to the present invention, the first analog signal is supplied to the modulation circuit (3) consisting of a chopper, and the second analog signal whose polarity is inverted at every predetermined period is output. Then, this second analog signal is sent to the A/D conversion circuit (6).
and is converted into a first digital signal. This first digital signal is supplied to a demodulation circuit (7), where it is demodulated and a second digital signal is output.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to FIG. The analog signal from the input terminal (1) is supplied to the low-pass filter (2), and the analog signal (first analog signal) (D in Figure 2) Pa from this is sent to the modulation circuit (chopper) (3). Here, an analog signal (second analog signal) whose polarity is inverted every time the clock signal a of 40 kHz (A in FIG. 2) arrives from the clock generation circuit (10) (FIG. 2). E) Converted to Pb.

In this case, the first analog signal Pa is set to 1/f (however,
f indicates the frequency) When noise is included, the signal component of the second analog signal Pb is distributed within a predetermined band on both sides centered on 4 Q k Hz, and is different from the band of 1/f noise. The overlapping portion of the bands in between is extremely small.

This second analog signal Pb is transmitted through an amplifier (AC amplifier)
(5) to the A/D conversion circuit (6), and has a frequency twice that of the clock signal a, that is, 80kHz.
D
/A conversion, it is converted into a digital signal (first digital signal) Pc. This A/D conversion circuit (
The sampled signal p c / of the second analog signal in 6) is shown in FIG. 2F.

Note that this A/D conversion circuit (6) includes fresh type, two-step fresh type, successive approximation type, series-parallel type, series type, integral type, double integral type, multiple integral type, high-speed integral type,
Various A/D conversion circuits such as oversampling delta-sigma modulation type are possible.

This first digital signal Pc is supplied to a demodulation circuit (7) as an inverse conversion circuit of the modulation circuit (chopper) (3), and is alternately converted to +1 and -1 every time the 40kHz clock signal e arrives. A digital signal (second digital signal) P that is multiplied and whose phase is inverted every time the clock signal e arrives.
d (Figure 2G). In this second digital signal Pd, the band of the signal component is returned to its original position,
Conversely, 1/f noise shifts to predetermined bands on both sides of 40 kHz.

This second digital signal Pd is supplied to the low-pass filter (8), thereby converting it into a frequency component of 1/2 of 80 kHz, which is the sampling frequency in the A/D conversion circuit (6), that is, a frequency component of 40 kHz. The output from which the 1/f noise has been removed is output to the output terminal (9).

Next, the circuit configuration of the chopper (3) will be explained.

The input terminal of the chopper (3) is the on/off switch S
It is grounded through a series circuit of W a 1 , S W a 2 and a capacitor (4) inserted in series therebetween. Then, the switch S W a H and the capacitor (
The middle point of connection in 4) is the on/off switch swb.

It is connected to the output terminal of the chopper (3) through the on/off switch 5Wcl and grounded through the on/off switch 5Wcl. Further, the connection midpoint between the switch S W a 2 and the capacitor (4) is connected to the output terminal of the chopper (3) through the on/off switch S W c 2 and grounded through the on/off switch swb2.

Here, the switches 5Wa1.5Wa2 are simultaneously controlled on and off by a 40kHz clock signal a (FIG. 2A), and when the clock signal a is at logic level "1",
Switches 5Wal and 5Wa2 are turned on at the same time,
The charge based on the first analog signal Pa is transferred to the capacitor (
4), and when the logic level is rOJ, it is simultaneously turned off and the charge is held.

In addition, the switches S W b 5 and S W b 2 are controlled on and off simultaneously by the clock signal b (FIG. 2B), which is the frequency of the clock signal a divided by half, and the clock signal A is controlled on and off at the same time as the logic level rlJ. When switch SWJ,
5Wb2 is turned on, and at this time the switch S W a
Since I and S W a 2 are off, the capacitor (
4) is applied to the amplifier (5), and the clock signal reaches the logic level "0".
”, the switch 5Wb1.5Wb2 is turned off.

In addition, the switches 5Wc1.5Wc2 are simultaneously on/off controlled by a clock signal C (FIG. 2C) in which the clock signal a is divided into half and has a phase difference of 180 degrees with respect to the clock signal a. C is the logical level
1", the switch 5Wc1.5Wc2 is on, and at this time the switch 5Wa1.5Wa2 and the switch s
Since wb, , and swb2 are both off, a voltage based on the charge on the capacitor (4) (which becomes a negative voltage) is applied to the amplifier (5), and the clock signal C reaches the logic level "
When OJ, switch S W c 3, S W c
2 is off.

In addition, the black/7 signal d supplied to the A/D conversion circuit (6)
For example, when the frequency of the clock signal e is set to 160 Hz, the frequency of the clock signal e supplied to the demodulation circuit (7) may be set to one half of that frequency, that is, 80 Hz.

Next, the operation of this A/D converter will be explained using mathematical formulas. It is supplied to the input terminal of the chopper (3). 1st
The voltage of the analog signal Pa is Va(N), and the voltage of the second analog signal Pb obtained at the output terminal of the chopper (3) is
Letting the voltage of Vb(N) be Vb(N), Vb(N) is expressed as follows. However, N indicates a sample point, and m is m-0, 1, 2, . . . .

First digital signal P obtained from the A/D conversion circuit (6)
The voltage of c is expressed as Vc (N), and this is the DC offset O
F (N), Vc (N) is expressed as follows.

Further, assuming that the voltage of the second digital signal Pd output from the demodulation circuit (7) is Vd (N), this is expressed as the following equation.

Here, the offsets OF(2m) and oF(2m+1
) is 1/2 of the sampling frequency of 80kHz, that is, 4
This is a frequency component of 0 kHz, which is removed by a low-pass filter (8).

〔Effect of the invention〕

According to the present invention described above, the A/D converter can have a simple configuration and reduce the influence of offset in A/D conversion.
A D conversion device can be obtained.

Furthermore, when an amplifier is inserted between the modulation circuit and the demodulation circuit, an AC amplifier may be used, which simplifies the circuit configuration accordingly.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a waveform diagram for explaining the same. (2) is a low-pass filter, (3) is a chopper, (5
) is an amplifier, (6) is an A/D conversion circuit, (7) is a demodulation circuit, and 8) is a low-pass filter. Agent Hidemori Matsukuma

Claims (1)

[Claims] A modulation circuit comprising a chopper to which a first analog signal is supplied and a second analog signal whose polarity is inverted every predetermined period is output; and a second analog signal from the modulation circuit. is supplied first
an A/D conversion circuit to which a digital signal is output; and a demodulation circuit to which a first digital signal from the A/D conversion circuit is supplied and demodulated to output a second digital signal. An A/D conversion device characterized by: