JPH0398234A - Monocrystal silicon electron emission gun array and manufacture thereof - Google Patents

Abstract

PURPOSE:To form a monocrystal silicon electron emission gun and a voltage applying electrode without the necessity of an assembly process by etching embedded monocrystal silicon through etching holes, etching-formed on the surface of a monocrystal silicon substrate. CONSTITUTION:A silicon oxide film 2 and a silicon nitride film 3 are formed in sequence on a monocrystal silicon substrate 1. In the silicon nitride film 3 and the silicon oxide film 2, there are a number of square electron emission holes 4 formed at equal spaces in array. Etching holes 5 are arranged at equal spaces with each other on one circle with the respective electron emission holes 4 as centers. Just under the electron emission holes 4, monocrystal silicon electron emission guns 6 are formed by isotropically etching the monocrystal silicon substrate 1 through the respective etching holes 5.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention provides a single unit suitable for use in flat panel displays, electron beam lithography, scanning electron microscopes, scanning tunneling microscopes, etc. that excite phosphors with electron beams. The present invention relates to an electron emission gun array made of crystalline silicon and a method for manufacturing the same.

[Conventional technology]

Conventionally, as an electron emission gun array using single crystal silicon, for example, H.H. Bus
ta), A.D. Feinerman (A.D.
．． Feinerman), J.B. Ketterson and R.D. Cueller
“STRINGS, LOOPS AND
PYRAMIDS-BUILDING BLOCKS
FOR MICROSTRUCTURES) J
(Proceedings of Micro R
robots and teleoperators W
orkshop). ．． Hyannis, Massachusetts (
lyann i,s) November, 9-LH1987)
) is known. The outline is as follows.

That is, first, an etching protection film such as a silicon oxide film is formed on a single crystal silicon substrate. Next, this etching protective film is patterned by etching to form a large number of square patterns each side having a length of about 5 μm, for example, at appropriate intervals. Next, using this etching protective film as an etching mask, anisotropic etching is performed on single-crystal silicon, such as a potassium hydroxide aqueous solution or an ethylene diagonal pyrocatechol aqueous solution, in which the etching rate is dependent on crystal orientation (anisotropy). By etching the single-crystal silicon substrate with a liquid, a flat-shaped single-crystal silicon is formed under the etching protection film.

This forms a single crystal silicon electron emission gun array from the pyramidal single crystal silicon. At this time, a square patterned etching protective film remains on the tip of each single-crystal silicon electron emission gun.
This etching protective film is removed by etching with an etching solution that etches the material of this etching protective film but does not etch single crystal silicon (for example, buffered monofluoric acid if the etching protective film is a silicon oxide film). Thereafter, if necessary, tungsten is selectively grown on the single crystal silicon electron emission gun by LPCVD.

As an electron emission gun array using a material other than single crystal silicon, a molybdenum electron emission gun array has been proposed (for example, C.A. Sp.
tndt), I Brodie (1.Brodie)
, L. Humphrey and R.R.H.
``Journal of Ablide Physics (J. Appl. Ph.
ys. ) J, Vol. 47, p. 5248 (1976)
).

[Problem to be solved by the invention]

In order to finally perfect the conventional single-crystal silicon electron-emitting gun described above, it is necessary to provide a counter electrode, that is, a gate electrode, for extracting electrons from the single-crystal silicon electron-emitting gun. , a mechanical assembly process for this gate electrode is required. By the way, in order to emit electrons efficiently, it is necessary to apply a large electric field to the electron emission gun. This can be achieved by doing. In the latter method, the voltage applied between the electron emission gun and the gate electrode does not need to be very large. When these electron-emitting guns are controlled and used by a semiconductor integrated circuit, it is desirable that the voltage applied to the electron-emitting guns is at most several tens of microns. Also, from the viewpoint of safety and reliability, the lower the applied voltage, the better, so it is better to make the distance between the electron emission gun and the electrode as small as possible to achieve a high electric field. However, as a practical matter, when using a mechanical assembly process to form the gate electrode, it is difficult to reduce the distance between the electron emission gun and the electrode to less than several tens of micrometers due to the limits of handling accuracy. . In order to operate at a voltage of several tens of square meters, which is a controllable voltage in a semiconductor integrated circuit, it is necessary to keep the distance between the electron emission gun and the electrode at least several hundred nanometers or less.

In addition, in the conventional single-crystal silicon electron emission gun of the single-crystalline silicon electron emission gun described above, the single-crystal silicon electron-emitting gun suffers from the difference in orientation, which is essentially determined by the difference in etching rate due to the plane orientation of the single-crystal silicon with respect to the anisotropic etching solution. Since the sides of the tube are surrounded, it is not possible to reduce the cone angle of the tip of the electron emission gun beyond a certain degree, and as a result, it is difficult to reduce the radius of curvature of the tip. Therefore, sufficient electric field concentration does not occur at the tip of the electron emission gun, and as a result, the voltage applied to the electron emission gun must be increased.

The present invention solves these problems and provides a single-crystal silicon electron emission gun array that can be controlled by a semiconductor integrated circuit and that can be manufactured using only planar technology, which is a common semiconductor manufacturing technology, and a method for manufacturing the same. With the goal.

[Means to solve the problem]

The single-crystal silicon electron-emitting gun array of the present invention for solving the above problems includes an electron-emitting gun formed on a single-crystal silicon substrate by etching such as isotropic etching, and a single crystal on which the electron-emitting gun is formed. An insulating film made of, for example, a silicon oxide film, a silicon nitride film, etc., provided on the surface of a silicon substrate, and an insulating film formed at equal intervals on one circumference centered on the tip of the electron emission gun. A plurality of first openings that are etching holes, a second opening for electron emission formed in an insulating film directly above the electron emission gun, and an electrode formed on the insulating film around the second opening. A plurality of elements are arranged in an array on the single crystal silicon substrate.

9 l0 Preferably, a metal thin film is formed on the single crystal silicon of the electron emission gun portion.

The manufacturing method of the present invention for manufacturing the above-mentioned single-crystal silicon electron emission gun array includes the steps of: forming an insulating film on a single-crystal silicon substrate; a step of forming an opening group consisting of first openings in an array pattern in an insulating film; a step of under-etching a single crystal silicon substrate through the plurality of first openings to form an electron emission gun; After the formation, a step of forming a second opening in the insulating film at the center position of the circle formed by the plurality of first openings, and a step of forming a second opening in the insulating film at the center position of the circle formed by the plurality of first openings;
(t: thickness of the insulating film, d: maximum diameter of the second opening) Forming an electrode on the insulating film around the second opening by obliquely depositing metal from a direction forming an angle θ that satisfies the following: It is equipped with.

In this case, the step of forming the electrode may be performed before the step of forming the second opening.

Further, after forming the electron emission gun, the second opening is formed in the insulating film, and then metal is deposited in a direction substantially perpendicular to the surface of the insulating film to form a single portion of the electron emission gun. A metal thin film may be formed on a crystalline silicon substrate, and then the step of forming the gate electrode may be performed.

Furthermore, instead of forming the metal thin film by vapor deposition, the metal thin film may be selectively grown on the single crystal silicon substrate in the electron emission gun portion by a vapor phase deposition method.

[For production]

The manufacturing process for semiconductor integrated circuits generally involves processing almost two-dimensionally on single crystal silicon substrates or other substrates, and processing on surfaces with large irregularities is basically unsuitable. be.

On the other hand, the tip of an electron emission gun must be made as thin as possible, no matter what material it is made of, so it must be
It becomes a dimensional structure. Therefore, although it has been possible to process single-crystal silicon into an electron emission gun, mechanical assembly processes have been required to form, for example, gate electrodes and peripheral elements to operate it. there was.

In contrast, in the single-crystal silicon electron emission gun according to the present invention, an insulating film that is not etched by an etching solution that etches silicon is formed on the surface of a single-crystal silicon substrate, and then etching holes are formed at predetermined locations in the insulating film. A plurality of first openings are formed, and the underlying single crystal silicon is etched entirely through the etching holes. Therefore, the single-crystal silicon electron emission gun is formed directly under the insulating film formed on the single-crystal silicon substrate, and the surface of the substrate is still flat except for a few etching holes. Therefore, two-dimensional processing can be continued using normal semiconductor integrated circuit manufacturing technology.

Furthermore, in the single-crystal silicon electron emission gun of the present invention, since the electron emission gun is formed in a so-called tunnel formed under the insulating film, the insulating crotch of the part where the electron emission gun is formed is If a conductive layer such as a metal thin film is formed using a normal semiconductor device manufacturing process such as vacuum deposition, electrodes for applying the voltage necessary to extract electrons from the electron emission gun can be easily provided.

Furthermore, since the single-crystal silicon electron emission gun formed according to the present invention and the electrode for applying voltage are separated by a distance approximately equal to the thickness of the insulating film formed on the single-crystal silicon, a small voltage can be applied. It is possible to create a large electric field with a voltage, and an electron emission gun can be sufficiently operated with an applied voltage of only a few volts to several tens of volts.

As mentioned above, conventional single-crystal silicon electron emission guns use etching methods such as potassium hydroxide aqueous solution and ethylenediamine pyrotechol aqueous solution, which have crystal orientation dependence (anisotropy) on the etching rate for single-crystal silicon. By etching the single-crystal silicon with liquid, a virago-type electron-emitting gun was formed. but,
In this case, the sides of the pyramid are defined by a certain plane ({2
1 2} plane), and a sufficient radius of curvature at the tip was not obtained. The radius of curvature of the tip greatly affects the electric field concentration at the tip, and the smaller the radius of curvature, the greater the electron emission efficiency.

In contrast, according to the present invention, for example, isotropic etching (an etching solution that etches at the same rate in any direction of single crystal silicon) alone or a combination of an isotropic etching solution and an anisotropic etching solution is possible. Since etching can be performed using both, it is possible to form a single-crystal silicon electron-emitting gun with a smaller angle formed by the side surface of the electron-emitting gun, the so-called cone angle, and a smaller radius of curvature at the tip than before. As a result, the electric field concentration at the tip increases,
Electron emission efficiency can be improved.

Furthermore, in the single-crystal silicon electron emission gun of the present invention, the electron emission gun is exposed through the second opening, which is an electron emission hole, and a metal with a small work function can be attached here. For example, cesium is heated at 50% under high vacuum.
Approximately 0 people need to evaporate. The work function of cesium is 2.1
Since the voltage is about 4 eV, which is about half that of silicon, the electron emission efficiency is improved. In addition, if a tungsten thin film is formed on the electron emission gun exposed through the electron emission hole using a tungsten selective growth technique such as low pressure vapor deposition, the electrode formed on the insulating film and the electron emission gun can be formed. The spacing can be adjusted, making it possible to apply a higher electric field to the electron emission gun. Since tungsten thin films are formed using low-pressure vapor deposition while preserving the shape of the underlying silicon, it is possible to form tungsten electron-emission gun arrays with a radius of curvature as small as that of single-crystal silicon electron-emission guns. It is possible. Note that in the case of metal thin films other than tungsten thin films, when the film thickness increases, it is difficult to form the film while preserving the shape of the underlying single-crystal silicon electron-emitting gun, so the cone angle and The radius of curvature becomes large, which is not preferable.

15 16 As described above, the single-crystal silicon electron emission gun according to the present invention has the feature that the gate electrode can be easily formed using substantially only ordinary semiconductor integrated circuit manufacturing techniques. The distance between the electron emission gun and the electrode can be reduced to several hundred nanometers or less, and the tip of the electron emission gun can also be formed thinner than before, so the operating voltage can be controlled directly by the semiconductor integrated circuit. It is possible to lower it to.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

In addition, in all the figures of the embodiment, the same or corresponding parts are given the same reference numerals.

FIG. 3 shows the overall structure of a single crystal silicon electron emission gun array according to the first embodiment of the present invention, and FIGS.
The main parts of the single-crystal silicon electron emission gun array shown in the figure are shown. FIG. 1 is a sectional view taken along line 1--1 in FIG. 2.

As shown in FIG. 1, in the single crystal silicon electron emission gun array according to the first embodiment, the single crystal silicon substrate l
A silicon oxide film 2 and a silicon nitride film 3 are sequentially formed thereon. Here, the single crystal silicon substrate I may have any plane orientation if only an isotropic etching solution is used when forming an electron emission gun, which will be described later, but if an anisotropic etching solution is used, The plane direction is (001)
It is preferable to use one that is. Further, the conductivity type of this single crystal silicon substrate 1 is preferably n-type, which has high electron emission efficiency. Specifically, this single crystal silicon substrate l has, for example, a surface orientation of (001) and a resistivity of 0.
An n-type single crystal silicon substrate of 8 to 1.2 Ωcm is used.

On the other hand, the film thicknesses of the silicon oxide film 2 and the silicon nitride film 3 are set to have a mechanical strength capable of supporting a gate electrode 7, which will be described later. Specifically, silicon oxide film 2
The film thickness of the silicon nitride film 3 is, for example, 50 nm, and the film thickness of the silicon nitride film 3 is, for example, 500 nm.

As shown in FIGS. 1 to 3, a large number of square l7 l8 electron emission holes 4 are formed in an array in the silicon nitride film 3 and the silicon oxide film 2 at equal intervals. The distance between the electron emission holes 4 is, for example, about 40 μm. Reference numeral 5 indicates an etching hole formed in the silicon nitride film 3 and the silicon oxide film 2, which is used when forming a single crystal silicon electron emission gun as described later. The etching holes 5 are arranged at equal intervals on one circumference with each electron emission hole 4 at the center. In this first embodiment, four etching holes 5 are arranged around each electron emission hole 4.

The shape of the etching hole 5 is a regular polygon or a circle so that the tip of the single crystal silicon electron emission gun is formed directly below the electron emission hole 4 as described later. Although it is functionally possible to set the size of this etching hole 5 to 1 μm square or less, it may be set to an appropriate size taking into consideration the physical constraints when performing photolithography, which will be described later, and the spacing of the electron emission gun array to be formed. Satoru. Specifically, the size of this etching hole 5 is, for example, 2 μm square. Further, the distance between the etching holes 5 arranged around each electron emission hole 4 is, for example, about 10 μm.

Note that the number of etching holes 5 arranged around each electron emission hole 4 does not necessarily have to be four;
If there are three or more, it is possible to form a single crystal silicon electron emission gun.

In this embodiment 1, a single crystal silicon electron emission gun 6 is formed directly below the electron emission hole 4 described above. As will be described later, this single-crystal silicon electron emission gun 6 is formed by isotropically etching the single-crystal silicon substrate 1 through each etching hole 5. In this case, the single crystal silicon electron emission gun 6 has side surfaces formed by four spherical surfaces centered around each etching hole 5 arranged around the electron emission hole 4, and has an approximately conical or polygonal pyramidal shape as a whole. It has the shape of The shape of the single-crystal silicon electron-emitting gun 6 varies depending on the number of etching holes 5 arranged around each electron-emitting hole 4, but in any case, it has a substantially conical or polygonal pyramidal shape. An electron-emitting gun with a sharp tip is formed.

In FIG. 1, reference numeral 7 denotes a gate electrode formed on the silicon nitride film 3. As shown in FIG. The gate electrode 7 may be made of any material that can be used as an electrode material, such as aluminum, gold, or copper. The thickness of this gate electrode 7 is, for example, about 0.3 to 1.0 pm.

In this first embodiment, a large number of single crystal silicon electron emission guns 6 as shown in FIGS. 1 and 2 are arranged in an array as shown in FIG.

Next, a method of manufacturing the single-crystal silicon electron emission gun array according to the first embodiment configured as described above will be described.

First, as shown in FIG. 4A, a silicon oxide film 2 is formed on a single crystal silicon substrate 1 by, for example, a thermal oxidation method.
A silicon nitride film 3 is formed by a method such as a plasma CVD method or a plasma CVD method. Thereafter, a resist pattern 8 having openings corresponding to the electron emission holes 4 and etching holes 5 described above is formed on the silicon nitride film 3 by lithography.

Next, as shown in FIG. 4B, the silicon nitride film 3 is etched by, for example, active ion etching (RIE) using the resist pattern 8 as a mask, and then the resist pattern 8 is removed. This results in
As shown in the figure, electron emission holes 4 in the silicon nitride film 3
A portion corresponding to the etching hole 5 is opened. Note that the etching of the silicon nitride film 3 is performed by further forming a silicon oxide film (not shown) with a thickness of, for example, several hundred nm on the silicon nitride film 3, and then forming a resist on the silicon oxide film by lithography. After forming the pattern, the silicon oxide film may be patterned by etching the silicon oxide film using the resist pattern as a mask, using hot phosphoric acid, for example, using the silicon oxide film as a mask.

21 22 Next, a resist pattern (not shown) is formed to cover the opening corresponding to the electron emission hole 4 described above, and using this resist pattern as a mask, the silicon oxide film 2 is etched with, for example, buffered monofluoric acid. As a result, as shown in FIG. 4C, an etching hole 5 is formed to expose that portion of the single crystal silicon substrate 1, and then the resist pattern is removed.

Next, as shown in FIG. 4D, the single crystal silicon substrate 1 is isotropically etched using, for example, a hydrofluoric acid mononitric acid based etching solution through the etching holes 5 formed in the silicon nitride film 3 and the silicon oxide film 2. . In this isotropic etching, as shown in the figure, the silicon oxide film 2
The lower portion of the single crystal silicon substrate 1 is largely under-etched. The progress of this under-etching is as follows:
By temporarily suspending etching and observing with an optical microscope such as a metallurgical microscope, it is possible to observe through the silicon oxide film 2 and silicon nitride film 3, so by repeating etching for an appropriate time, washing with water, and observing. Etching is made to end immediately after all the under-etched regions from each etching hole 5 are connected.

Note that the single crystal silicon substrate 1 may be etched using both an isotropic etching solution and an anisotropic etching solution, or only an anisotropic etching solution. A silicon electron emission gun can be formed using only an isotropic etching solution.
In the case of two-step etching using both an isotropic etching solution and an anisotropic etching solution, a single crystal with a smaller cone angle and radius of curvature at the tip than when formed using only an anisotropic etching solution. A silicon electron emission gun can be made.

In etching the single-crystal silicon substrate 1 using the two-step etching described above, etching is first performed using an isotropic etching solution until the under-etched regions from adjacent etching holes 5 are connected, and then etching is performed using an anisotropic etching solution. , etching is performed until the under-etched regions from all the etching holes 5 are connected by 23 24 .

Note that the above-mentioned etching solution such as the hydrofluoric acid mononitric acid based etching solution for isotropic etching, the potassium hydroxide aqueous solution, and the ethylenediamine pyrotechol aqueous solution used for anisotropic etching can be used for the silicon oxide film 2 and the silicon nitride film 3.
However, the etching speed for these materials is sufficiently slow compared to the etching speed for silicon, and the etching time when forming a single crystal silicon electron emission gun is very short, for example, several minutes. Therefore, it can be almost ignored.

Note that the above-described isotropic etching can also be performed by a method other than wet etching as in this embodiment, such as plasma etching.

Next, as shown in FIG. 4E, a metal material for forming a gate electrode is vacuum-deposited from a direction in which the flying direction of the vapor-deposited atoms forms an angle θ with respect to the surface of the silicon nitride film 3. This vacuum deposition is performed while rotating the substrate 1 around its normal line. Here, the angle θ is when t is the total thickness of the silicon oxide film 2 and the silicon nitride film 3, and a is the length of one side of the etching hole 5 and the electron emission hole 4 formed in the silicon nitride film 3, respectively. , the length d of the diagonal line, which is the maximum diameter of the holes 4 and 5, is selected to satisfy θ≦tan−′ (t/, /Ta) since d=JT a. Gate electrode 7 is formed on silicon nitride film 3 by this vacuum deposition. Note that during this vacuum deposition, the metal material for forming the gate electrode is not deposited on the silicon oxide film l in the electron emission hole 40 portion near the tip of the single-crystal silicon electron emission gun 6, but the silicon nitride film is It will be selectively deposited only on 3. Thereafter, the formed metal thin film for electrodes is patterned by a photolithography process, if necessary.

In this example, the etching hole 5 and the electron emission hole 4 are square-shaped with the same size, but the size and shape of the etching hole 5 and the size and shape of the electron emission hole 4 are made to match each other. They do not have to be, and may be of different shapes and sizes 25 26 . In that case, the flying direction θ of the evaporated atoms
teeth. It may be determined based on the maximum diameter d of the electron emission hole 4, and may be set so that θ≦tan−′ (t/d).

Next, as shown in FIG. 4F, the silicon oxide film 2 on the single-crystal silicon electron emission gun 6 is removed by etching to open this portion. In this case, first, the silicon oxide film 2 on the single-crystal silicon electron emission gun 7 is etched using a reactive ion etching method until the thickness of the silicon oxide film 2 becomes about 100 mm. , the remaining silicon oxide film 2 is removed by etching. As the etching gas for this reactive ion etching, it is preferable to select a gas that does not etch the metal thin film for forming the gate electrode. For example, when aluminum is used as the metal thin film for forming the gate electrode,
By avoiding chlorine-based gas and using hydrofluoric acid monohydrogen-based gas, the aluminum thin film can be used as an etching mask when etching the silicon oxide film 2.

In addition, although buffered monofluoric acid does attack aluminium to some extent, it can be ignored after etching for about 30 seconds.
Furthermore, since the etching rate for silicon nitride is sufficiently slower than that for silicon oxide, only the silicon oxide film 2 can be selectively etched. It should be noted that if the entire silicon oxide film 2 is to be etched by only active ion etching as described above, there is a risk that the single crystal silicon substrate 1 in the electron emission gun 6 portion will also be etched, which is not preferable.

In this first embodiment, even if the silicon oxide film 2 on the single crystal silicon electron emission gun 6 is etched before forming the gate electrode 7, the same single crystal silicon electron emission gun array as described above can be manufactured. be able to.

As described above, 64 single crystal silicon electron emission guns 6
When a single-crystal silicon electron-emitting gun array was manufactured and the current-voltage characteristics were measured by applying a DC voltage to the single-crystal silicon substrate 1 and gate electrode 7, it was found that one single-crystal silicon electron-emitting gun An emission current of approximately 0.3 μA per 6 was obtained.

As described above, according to the first embodiment, since the single crystal silicon electron emission gun 6 is formed by isotropically etching the single crystal silicon substrate 1 through the etching hole 5, the radius of curvature of the tip is A single crystal silicon electron emission gun 6 having a sharp tip of about 100 A can be obtained. Moreover, since the gate electrode 7 can be formed close to the tip of the single-crystal silicon electron-emitting gun 6 with high accuracy by vacuum evaporation, the distance between the single-crystal silicon electron-emitting gun 6 and the gate electrode 7 can be reduced. It can be made extremely small. As a result, the voltage applied to the single-crystal silicon electron emission gun 6 can be small.

In addition, in this Example 1, as shown in FIG.
Etching holes 5 are made independently for each element of each electron emission gun 6.
However, for example, the etching holes of adjacent elements may be shared by each element. That is, by under-etching from one etching hole,
Electron emission guns may be formed on both sides of the etching hole.

Practical Group 1 FIG. 5 shows a single crystal silicon electron emission gun array according to a second embodiment of the present invention.

As shown in FIG. 5, in the single crystal silicon electron emission gun array according to the second embodiment, a metal thin film 9 is formed near the tip of the single crystal silicon electron emission gun 6. As shown in FIG.

Other structures are similar to the single crystal silicon electron emission gun array according to the first embodiment described above.

The reason for forming this metal thin film 9 is, first, to increase the electron emission efficiency of the single crystal silicon electron emission gun 6, and secondly, the reason for forming this metal thin film 9 is to increase the electron emission efficiency of the single crystal silicon electron emission gun 6. This is to further reduce the distance between the gate electrode 6 and the gate electrode 7 so that a higher electric field can be applied to the electron emission gun.

For the first purpose, it is preferable to use a material such as cesium, barium, or cerium, which has a smaller work function than single crystal silicon, for the metal thin film 9. In this case, it is desirable that the metal thin film 9 inherits the shape having a small cone angle and radius of curvature of the tip of the single-crystal silicon electron emission gun, which is formed in the manufacturing process described later. However, if these metals are deposited too thickly, the metal thin film 9 will not take over the shape of the tip of the single-crystal silicon electron-emitting gun, resulting in a large radius of curvature. Therefore, the thickness of the metal thin film 8 is approximately 50 mm.
It is preferable to set the number to about 0 or less.

On the other hand, for the second purpose, as described in Example 3, it is effective to use a technique for selectively growing tungsten on silicon by low pressure vapor phase growth.

Since the tungsten thin film grown by this selective growth technique is formed by a chemical reaction between tungsten and silicon, it is formed in the shape of the underlying single-crystal silicon electron emission gun. Therefore, the radius of curvature and cone angle of the tip of the electron-emitting gun are almost the same as those of the underlying single-crystal silicon electron-emitting gun even after the tungsten thin film is formed.

Next, a method of manufacturing the single crystal silicon electron emission gun array according to the second embodiment configured as described above will be explained.

In the method for manufacturing a single-crystal silicon electron emission gun array according to the second embodiment, the steps are first advanced to the step shown in FIG. 4C of the first embodiment.

Next, the silicon oxide film 2 is etched using buffer monofluoric acid. In this case, the silicon nitride film 3 serves as an etching mask, and as shown in FIG. 6A, the silicon oxide film 2 immediately above the tip of the single-crystal silicon electron emission gun 6 is selectively etched to form electron emission holes. 4 is formed.

Next, as shown in FIG. 6B, a metal with a small work function, such as cesium, is deposited in a direction substantially perpendicular to the surface of the silicon nitride film 3. As a result, the electron emission hole 4
By vapor-depositing a metal such as cesium through the process, a thin metal film 9 of cesium or the like is formed at the tip of the single-crystal silicon electron emission gun 6. Although the metal thin film 9 is also formed on the single crystal silicon substrate 1 below the etching hole 5 by this vapor deposition, it does not affect the functionality of the device in any way. The thickness of this metal thin film 9 may be, for example, several tens of nanometers.

Next, as shown in FIG. 6C, a gate electrode 7 is formed on the silicon nitride film 3 by diagonally depositing metal in the same manner as in Example 1. This completes a single crystal silicon electron emission gun array similar to that shown in FIG.

In the single crystal silicon electron emission gun array in which a cesium film was formed as the metal thin film 9 by vapor deposition, an emission current of about 0.5 μA per electron emission gun was obtained at an applied voltage of 100V.

Figure 7 shows a single crystal silicon electron emission gun array according to a third embodiment of the present invention.

As shown in FIG. 7, in the single-crystal silicon electron emission gun array according to the third embodiment, a metal thin film made of, for example, tungsten is coated on the entire surface of a substantially spherical single-crystal silicon substrate 1 formed by isotropic etching. 9 is formed. Other structures are the same as in the first embodiment.

Next, a method of manufacturing the single crystal silicon electron emission gun array according to the third embodiment configured as described above will be explained.

In the method for manufacturing a single-crystal silicon electron emission gun array according to this third embodiment, the steps are first advanced to the step shown in FIG. 4C of the first embodiment.

Next, selective growth of tungsten is performed by low pressure vapor phase growth. In this case, as the reactive gas enters through the electron emission hole 4 and the etching hole 5, as shown in FIG. A tungsten thin film 9 is formed on the entire surface of the portion. Since this tungsten thin film 9 is formed by a chemical reaction with silicon, this tungsten thin film 9 is not formed in the portion covered with the silicon oxide layer 2 and the silicon nitride layer 3.

Thereafter, gate electrode 7 is formed in the same manner as in Example 1.

In the single-crystal silicon electron emission gun array formed by selecting tungsten as the metal thin film 9, 10
Approximately 0.0 V per electron emission gun at an applied voltage of 0 V.
An emission current of 4 μA was obtained.

Although the embodiments of the present invention have been specifically described above, the present invention is not limited to the above embodiments, and the above embodiments may be modified in various ways without departing from the technical idea of the present invention. It is possible.

For example, in Examples 1 to 3 above, two layers of silicon oxide film 2 and silicon nitride film 3 are formed as insulating films on single crystal silicon substrate 1, but insulating films are not necessarily formed in two layers in this way. It is not necessary to have one layer or three or more layers as necessary. In addition, the above Example 2
In this case, the metal thin film 9 can also be formed by, for example, a lift-off method.

〔Effect of the invention〕

As explained above, according to the present invention, a single-crystal silicon electron emission gun and an electrode for applying voltage can be easily and accurately manufactured using only ordinary semiconductor integrated circuit manufacturing techniques without the need for an assembly process or the like. can be manufactured.

Furthermore, it is possible to easily realize a single-crystal silicon electron emission gun whose tip has a smaller radius of curvature than conventional ones.

Furthermore, the electrode for applying voltage can be formed very close to the electron emission gun at an interval of several hundred nm or less,
Thereby, the operating voltage of the electron emission gun can be reduced.

[Brief explanation of drawings]

FIG. 1 is a sectional view of a main part of a single crystal silicon electron emission gun array according to a first embodiment of the present invention, FIG. 2 is a plan view of a main part of the same single crystal silicon electron emission gun array, and FIG. A perspective view showing the overall structure of a crystalline silicon electron emission gun array;
4A to 4F are cross-sectional views for explaining the manufacturing method of the single-crystal silicon electron-emission gun array in the order of steps, and FIG. 5 is a main part of the single-crystal silicon electron-emission gun array according to the second embodiment of the present invention. 6A-6C are cross-sectional views for explaining the manufacturing method of the same single-crystal silicon electron emission gun array in the order of steps, and FIG. FIG. 8 is a cross-sectional view of a main part of the emission gun array, and is a cross-sectional view for explaining the manufacturing method of the single-crystal silicon electron emission gun array in the order of steps. In addition, in the symbols used in the drawings, ■ -... one single-crystal silicon substrate 2 one silicon oxide film 3 silicon nitride film 4- one electron emission hole (second
opening) 5-------1...-------1 etching hole (first opening) 6-----------
Single-crystal silicon electron emission gun 7 - Gate electrode 9 ------------- Metal thin film.

Claims (6)

[Claims] (1) An electron emission gun formed by etching on a single crystal silicon substrate; an insulating film provided on the surface of the single crystal silicon substrate on which the electron emission gun is formed; a plurality of first openings formed in the insulating film at equal intervals on one circumference, and a second opening for electron emission formed in the insulating film directly above the electron emission gun; , a single-crystal silicon electron emission gun array, characterized in that a plurality of elements each comprising an electrode formed on the insulating film around the second opening are arranged in an array on the single-crystal silicon substrate. . (2) Claim 1 characterized in that a metal thin film is formed on the single crystal silicon substrate of the electron emission gun portion.
Single crystal silicon electron emission gun array as described. (3) forming an insulating film on a single-crystal silicon substrate, and forming an opening group consisting of a plurality of first openings arranged at equal intervals on one circumference in an array pattern on the insulating film; forming an electron emission gun by under-etching the single crystal silicon substrate through the plurality of first openings; after forming the electron emission gun, forming a circle formed by the plurality of first openings; a step of forming a second opening in the insulating film at a central position; and a step of forming a second opening in the insulating film at a central position;
) (t: thickness of the insulating film, d: maximum diameter of the second opening) by diagonally vapor depositing metal onto the insulating film around the second opening. A method of manufacturing a single crystal silicon electron emission gun array, comprising the step of forming an electrode. (4) The method of manufacturing a single-crystal silicon electron emission gun array according to claim 3, wherein the step of forming the electrode is performed before the step of forming the second opening. (5) forming an insulating film on a single-crystal silicon substrate, and forming an opening group consisting of a plurality of first openings arranged at equal intervals on one circumference in an array pattern on the insulating film; forming an electron emission gun by under-etching the single crystal silicon substrate through the plurality of first openings; after forming the electron emission gun, forming a circle formed by the plurality of first openings; forming a second opening in the insulating film at a central position, and depositing metal on the single crystal silicon substrate in the electron emission gun portion from a direction substantially perpendicular to the surface of the insulating film; a step of forming a metal thin film on the surface of the insulating film, and θ≦tan^-^1(t/d
) (t: thickness of the insulating film, d: maximum diameter of the second opening) by diagonally vapor depositing metal onto the insulating film around the second opening. A method of manufacturing a single crystal silicon electron emission gun array, comprising the step of forming an electrode. (6) forming an insulating film on a single-crystal silicon substrate, and forming an opening group consisting of a plurality of first openings arranged at equal intervals on one circumference in an array pattern on the insulating film; forming an electron emission gun by under-etching the single crystal silicon substrate through the plurality of first openings; after forming the electron emission gun, forming a circle formed by the plurality of first openings; forming a second opening in the insulating film at a central position; selectively growing a metal thin film on the single crystal silicon substrate in the electron emission gun portion by vapor phase growth; and a surface of the insulating film. θ≦tan＾−＾1(t/d
) (t: thickness of the insulating film, d: maximum diameter of the second opening) by diagonally vapor depositing metal onto the insulating film around the second opening. A method of manufacturing a single crystal silicon electron emission gun array, comprising the step of forming an electrode.