JPH0397332A - Inter-processor communication method - Google Patents

Abstract

PURPOSE:To expand an inter-processor maximum communication capacity by allowing the cell decomposing device of a transmission processor to divide communication information into cells, sending them to a reception processor via an ATM speech path and composing the received cells with a cell assembling device to generate communication information. CONSTITUTION:A processor 110 writes the information desired of communication into a memory 120. A reception module 300 receives a cell with a buffer register 330 and sends information attribute display in a header to decoders 360, 310. A decoder 362 receives a transmission module number from a message register 330 and selects a cell assembling device corresponding to the module number. A memory write register 376 writes inter-processor communication information to the memory 320 according to the reception buffer address to realize simultaneous inter-processor communication from plural transmission modules.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a communication method between distributed processors in a distributed controlled ATM switch. [Prior art] The conventional communication method between processors is the digital switching method (
As described in IEICE (Pages 134 and 135), it is a communication method using a multiprocessor bus, and is a method of arbitrating simultaneous communication from multiple processors using an M aggregation circuit, that is, use of the bus by contention processing. It gave the right to the processor and could only perform one communication at the same time.

[Problem to be solved by the invention]

In the above-mentioned conventional technology, the inter-processor communication capacity is small, which is one of the factors controlling the exchange capacity, and hinders the increase in the capacity of the exchange.

SUMMARY OF THE INVENTION An object of the present invention is to enable simultaneous communication between a plurality of processors, expand communication capacity between processors, and further increase the capacity of an exchange.

[Means to solve the problem]

The above purpose is to use an ATM channel in a distributed control ATM switch as an inter-processor communication bus, and a cell disassembly device that divides communication information into cells in a transmitting processor and transmits the cells to a receiving processor, and a cell disassembly device that divides communication information into cells and sends the cells to a receiving processor. a cell assembly device that assembles the cells and generates communication information;
It has as many reception buffers as the number of processors, enabling simultaneous multiple communications between processors and increasing the maximum processor communication capacity.

[Effect]

The cell disassembly device of the transmitting processor divides the communication information into cells and transmits them to the receiving processor via the ATMi channel. The cell assembly device of the reception processor assembles the received cells and generates communication information. At this time, cell assembly devices and reception buffers are installed for the number of processors to enable simultaneous reception from multiple processors. Enables expansion of inter-processor communication capacity.

〔Example〕

Embodiments of the present invention will be described below with reference to FIGS. 1, 2, and 3. Figure 1 shows the system configuration of an ATM switch. In FIG. 1, the ATV exchange is comprised of a subscriber module 20, a relay module 50, and a self-rating switch 4o. Subscriber 80 is connected to subscriber module 20 via subscriber line 10;
The relay module 50 is connected to other stations by a relay line 60. The subscriber module 20 and the relay module 50 are connected to a self-rating switch 40 by an ATM highway 30. subscriber module 20,
The relay module 50 is composed of processors 70 and 71 that perform call control and credit processing, and a communication path that carries ATM information. On the other hand, the self-routing switch 40 that connects these modules is a self-routing channel that exchanges all information in units of cells in a uniform format (header+information). (The technology was published in Nikkei Electronics 1988.1.11, 132-136) As shown in Figure 2, on ATM Highway 30, frames with a fixed time width (125 μs in the figure) The concept is that a frame accommodates a plurality of fixed-length cells in a uniform format consisting of a header section and an information section. A cell consists of a header and information, and the header is
Consists of sending module number, receiving module number, and information attribute display. The information attribute display is a display for identifying end-to-end transfer information after call setup or inter-processor communication information when the corresponding cell is empty or not empty.
When this display is the end-to-end transfer information after call setup,
Cell component information indicates end-to-end transfer information after call setup. Further, when the information attribute display is inter-processor communication information, the information on the cell component indicates that it is inter-processor communication information.

FIG. 3 shows a hardware configuration for realizing inter-processor communication in an ATM switch by having a plurality of cell assembly devices and reception buffers. In FIG. 3, a transmitting module 100 and a receiving module 300 correspond to the subscriber module 20 or relay module 50 in FIG. The operation when the processor 110 in the transmitting module 100 performs inter-processor communication with the processor 310 in the receiving module 300 will be explained using FIG.

The transmission module 100 includes a processor 110, a memory 1
20, cell division equipment jJ150, message register 13
0, bumper register 140, message inserter 1
80, and the receiving module is configured by the processor 3.
10, memory 320, message register 330, backup register 340, and cell assembly devices 370 to 3nO.

The processor 110 writes information to be communicated into the memory 120. Next, the processor 110 sends the start address of the communication information to the memory readout circuit 15 in the cell disassembly device.
4, the number of transferred words is stored in the word counter 151, and the header (transmission module number, reception module number, information attribute display (interprocessor communication information: 2) is stored in the header register 153.
write to.

The memory read circuit 154 reads out a specific number of edicts (the number of words of inter-processor communication information in cell format) from the memory 120 from the specified address, and transfers the 6 headers to the message register 130 from the hesoder register 153.
and sent to the message register 130. When the cell is completed, the message register 130 synchronizes with the buffer register 140 (a circuit for receiving and transmitting end-to-end information) and sends the completed cell to an empty time slot through the message inserter 180.

The message is sent to the self-notating switch 200, which analyzes the reception module number in the header and sends it to the reception module 300. In the receiving module 300, the buffer register 330 receives the cell and sends the information attribute indication in the header to the decoders 360, 361. When the information attribute display is end-to-end transfer information, the decoder 360 operates,
The end-to-end transfer information stored in the buffer register 340 is transferred to another station. When the information attribute display is inter-processor communication information, the decoder 361 operates and the decoder 362 is activated.

The decoder 362 receives the transmission module number from the message register 330, selects the cell assembly device (temporarily 370) corresponding to the module number, activates the AND circuit 374, and transfers the interprocessor communication information from the message register 330 to the memory. Send to write register 376. On the other hand, in the memory write register 376, the processor 3
10 writes the reception buffer address on the memory 320 in advance. Memory write register 376 writes interprocessor communication information to memory 320 according to the receive buffer address, thereby realizing simultaneous interprocessor communication from multiple transmitting modules. Memory write register 376
When the writing of the inter-processor communication information is completed, the adder circuit 371 is activated, a specific number of words (the number of words of the inter-processor communication information in the cell format) is added, and the storage address of the next cell is written onto the memory write register 376. Set it.

On the other hand, in the transmission module OO, the message register 130 that has finished transmitting the cell activates the subtraction circuit 155 and subtracts the number of transferred words in the word counter 151 by a specific number of words (the number of words of inter-processor communication information in the cell format). However, if the value does not become negative, the adder circuit 156 is activated and the communication information address in the memory read circuit 154 is added by the specific number of words (the number of words of the inter-processor communication information in the cell format). The memory read circuit 154 reads the inter-processor communication information from the memory 120 according to the added communication information address and sends it to the message register 130. Thereafter, by the same operation as described above, the inter-processor communication information is continued to be sent until the number of transferred words in the word counter 151 becomes negative, and inter-processor communication is realized.

〔Effect of the invention〕

According to the present invention, an ATM channel of a distributed control ATM switch is used as an inter-processor communication bus, and a cell disassembly device is provided which divides communication information into cells at a sending processor and transmits the cells to a receiving processor. A cell assembling device or a receiving buffer for assembling received cells into a receiving processor and generating communication information is provided for the number of processors, thereby enabling simultaneous multiple communications between processors and increasing the maximum processor communication capacity.

[Brief explanation of drawings]

Fig. 1 is a system configuration diagram of an ATM switch according to an embodiment of the present invention, Fig. 2 is a diagram of a frame structure on an ATM highway, and Fig. 3 is a system configuration diagram of an ATM switch having a plurality of cell assembly devices for communication between ATM processors. It is a hardware configuration diagram realized by this. DESCRIPTION OF SYMBOLS 10... Subscriber line, 20... Subscriber module, 30... ATM highway, 40... Self-rating, 50... Relay module, 60... Relay line, 70.71... - Processor, 80... Subscriber, 100... Transmission module, 200... Self-rating switch, 300...
- Receiving module, 110, 310... Processor, 120, 320... Memory, 150... Cell disassembly device, 140, 340... Puffer register, 130, 33
0...Message register, 180...Message inserter, 154...Memory reading circuit, 151...Word counter, 153...Hesoda register, 155...Subtraction circuit, 156,371...Addition circuit, 360, 361, 362... decoder, 376...
Memory write register, 374, 375...AND circuit.

Claims (1)

[Claims] 1. Distributed control ATM (AsynchronousTr)
(ansferMode) An inter-processor communication method characterized in that one processor simultaneously receives inter-processor communication information from a plurality of distributed processors using fixed-length packets carried within an ATM communication path in an exchange.