JPH0397228A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

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Publication number
JPH0397228A
JPH0397228A JP23281789A JP23281789A JPH0397228A JP H0397228 A JPH0397228 A JP H0397228A JP 23281789 A JP23281789 A JP 23281789A JP 23281789 A JP23281789 A JP 23281789A JP H0397228 A JPH0397228 A JP H0397228A
Authority
JP
Japan
Prior art keywords
gas
silicon
semiconductor device
manufacturing
silicon substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23281789A
Other languages
Japanese (ja)
Inventor
Akihiro Miyauchi
昭浩 宮内
Hironori Inoue
洋典 井上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP23281789A priority Critical patent/JPH0397228A/en
Publication of JPH0397228A publication Critical patent/JPH0397228A/en
Pending legal-status Critical Current

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  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)
  • Formation Of Insulating Films (AREA)
  • Thin Film Transistor (AREA)

Abstract

PURPOSE:To form porous silicon free from organic contamination, by introducing gas that contains a high purity fluorine element into a reaction vessel in which a silicon substrate is arranged. CONSTITUTION:A silicon substrate 12 in a reaction vessel 11 made of quartz is arranged on a carbon susceptor 13 covered with silicon carbide. The silicon substrate 12 is rotated together with the carbon susceptor 13 by a motor 14, and heated at 500 deg.C or more by an infrared radiation heater 15. NF3 (nitrogen trifluoride) gas 16 and hydrogen gas 17 are used, and the flow rates are individually controlled by flow rate controlling apparatuses 18, 19. The gas is introduced into the reaction vessel 11 made of quartz through a gas feeding pipe 20, and discharged by a rotary pump 21. In stead of nitrogen trifluoride gas, the following may be used; xenon fluoride (XeF2) gas, chlorine trifluoride (ClF3) gas, and fluorine (F2) gas.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はLSI製造工程において素子分離等に応用され
るボーラス状シリコンの形成方法及び装置に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method and apparatus for forming a bolus of silicon, which is applied to element isolation and the like in an LSI manufacturing process.

〔従来の技術〕[Conventional technology]

従来、ポーラス状シリコンの形成方法及び装置について
は、ジャパニーズ・ジャーナル・オブ・アプライド・フ
ィジクス15 (1976年)第1655頁から166
4頁(Jpn.J.Appl.Phys.,Is (1
976)PP1655−1664)において論じられて
いる。ここで述べられているようにボーラス状シリコン
はフッ化水素(HF)水溶液中での陽極反応によって形
威される.また、ポーラス状シリコンは容易に酸化され
るので、例えばLSI製造プロセスにおける素子分離技
術やS O I (Silicon on Insul
ator)構造の形成に適用される。
Conventionally, methods and apparatus for forming porous silicon are described in Japanese Journal of Applied Physics 15 (1976), pp. 1655 to 166.
4 pages (Jpn. J. Appl. Phys., Is (1
976) PP 1655-1664). As described here, bolus silicon is formed by an anodic reaction in an aqueous hydrogen fluoride (HF) solution. In addition, since porous silicon is easily oxidized, it is difficult to use, for example, element isolation technology in the LSI manufacturing process or SOI (Silicon on Insulator).
ator) structure.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上記従来技術はフッ化水素水溶液中での陽極反応を用い
る為,水溶液中に存在する有機物について配慮がされて
おらず,ポーラス状シリコンの汚染の問題があった。フ
ッ化水素水溶液中でのシリコン基板の汚染については例
えばA.Licciardelloらがアプライド・フ
イジクス・レター4 8 (1986年)第41頁から
第43頁(Appl.Phys.Lett. ,48(
1986)PP41−43)で述べている。彼らはフン
化水素水溶液中の汚染物はフッ化水素水溶液を入れる容
器からの有機物と予想している。
Since the above-mentioned conventional technology uses an anodic reaction in an aqueous hydrogen fluoride solution, no consideration is given to organic substances present in the aqueous solution, resulting in the problem of contamination of porous silicon. Regarding contamination of silicon substrates in a hydrogen fluoride aqueous solution, see, for example, A. Licciardello et al. Applied Physics Letters 48 (1986) pp. 41-43 (Appl. Phys. Lett., 48 (
1986) PP41-43). They predicted that the contaminants in the hydrogen fluoride solution were organic matter from the container containing the hydrogen fluoride solution.

実際、陽極酸化法でポーラス状シリコンを形成する場合
、反応容器(化或槽)は四フッ化エチレンーバーフロロ
アルキルビニルエーテル共重合樹脂(PFA)製である
ため濃フッ酸に対して劣化する。具体的には23℃の6
0%濃フッ酸に168時間、PFAを浸すと引張り強度
と伸びの残留特性は99%になる。すなわち、PFAは
濃フッ酸と反応し、その結果、フッ化水素水溶液中に有
機物が混入することになる。
In fact, when porous silicon is formed by anodizing, the reaction vessel (chemical tank) is made of tetrafluoroethylene-barfluoroalkyl vinyl ether copolymer resin (PFA) and is degraded by concentrated hydrofluoric acid. Specifically, 6 at 23℃
When PFA is immersed in 0% concentrated hydrofluoric acid for 168 hours, the residual properties of tensile strength and elongation become 99%. That is, PFA reacts with concentrated hydrofluoric acid, and as a result, organic matter is mixed into the hydrogen fluoride aqueous solution.

本研究の目的は有機物による汚染のないポーラス状シリ
コンを形成することにある. 〔課題を解決するための手段〕 上記目的を達成するために、シリコン基板を設置した反
応容器内に高純度のフッ素元素あるいは他のハロゲン元
素を含むガスを導入した。
The purpose of this research is to form porous silicon that is free from organic contamination. [Means for Solving the Problems] In order to achieve the above object, a gas containing highly purified fluorine element or other halogen element was introduced into a reaction vessel in which a silicon substrate was installed.

〔作用〕[Effect]

フッ素元素あるいは他のハロゲン元素を含むガスは精製
器で容易に高純度化できる。それらの高純度ガスを反応
容器内へ導入し、反応容器内に設置したシリコン基板と
反応させることにより、有機物の汚染なしにボーラス状
シリコンを形成できる。
Gases containing elemental fluorine or other halogen elements can be easily purified to a high degree using a purifier. By introducing these high-purity gases into a reaction container and causing them to react with a silicon substrate placed in the reaction container, a bolus of silicon can be formed without contamination with organic matter.

〔実施例〕〔Example〕

以下、本発明の一実施例を第工図により説明する。石英
製反応容器11中のシリコン基仮l2(6インチ径,ボ
ロン(B) ドープ,比抵抗20Ω・0,面方位(10
0),オフアングル4゜)は炭化シリコン(sic)被
覆された炭素サセプタ13上に設置した。シリコン基仮
12は炭素サセプタ13と伴にモーターl4によって回
転する。
An embodiment of the present invention will be described below with reference to the drawings. Silicon base 12 (6 inch diameter, boron (B) doped, resistivity 20Ω・0, surface orientation (10
0), off-angle 4°) was placed on a silicon carbide (SIC) coated carbon susceptor 13. The silicon base material 12 is rotated together with the carbon susceptor 13 by a motor 14.

またシリコン基板12は赤外線加熱Wl5によって80
0℃に加熱される.使用したガスはNFsガス(三フッ
化窒素ガス)16(純度99.9999%,流量47c
c/分)と水素ガス17(純度99.9999%,流量
1cc/分)である。流量は流量制御器18.19によ
り各々制御される。ガスはガス供給管20を通じて石英
製反応容器11へ導入される。
Further, the silicon substrate 12 is heated to 80° by infrared heating Wl5.
It is heated to 0℃. The gas used was NFs gas (nitrogen trifluoride gas) 16 (purity 99.9999%, flow rate 47c).
c/min) and hydrogen gas 17 (purity 99.9999%, flow rate 1 cc/min). The flow rates are each controlled by flow controllers 18,19. Gas is introduced into the quartz reaction vessel 11 through the gas supply pipe 20.

反応容器内のガスはロータリボンプ21で排気される。The gas in the reaction vessel is exhausted by the rotary pump 21.

反応容器内の圧力は1 . I Torrである。The pressure inside the reaction vessel is 1. I Torr.

第2図は処理時間(ガスを流した時間)と形成したボー
ラス状シリコン膜の膜厚との関係である。
FIG. 2 shows the relationship between the processing time (time during which gas was flowed) and the thickness of the formed bolus-shaped silicon film.

これから処理時間とともにボーラス状シリコン膜の膜厚
は増加することがわかる。なお、ボーラス状シリコン膜
の膜厚はシリコン基板12を切断面を走査型電子顕微鏡
でM察して求めた。また、三フッ化窒素ガスの代りにフ
ッ化キセノン(XeFz)t三フッ化塩素(CffFa
),フッ素(F2)ガスを用いても同様にボーラス状シ
リコン膜を形成できた。
It can be seen from this that the thickness of the bolus silicon film increases with processing time. The thickness of the bolus silicon film was determined by observing the cut surface of the silicon substrate 12 using a scanning electron microscope. Also, instead of nitrogen trifluoride gas, xenon fluoride (XeFz), chlorine trifluoride (CffFa
), a bolus-shaped silicon film could be similarly formed using fluorine (F2) gas.

次に本発明の素子分離技術への一実施例を述べる。第3
図は素子分離工程を示す。用いたシリコン基板111は
p型シリコン基板表面にアンチモンを10μm拡散させ
た,次に表面を熱酸化し,厚さ50nmの酸化膜112
を形成した。パターニング後、本発明によるポーラス状
シリコン113を形成した。形成条件は先の実施例と同
じで処理時間は30分である。次に基板温度800℃,
30分のドライ酸化によって酸化ボーラス状シリコン(
O P O S : Oxidized Porous
 Silicon) 114を形成した。表面の酸化層
を除去して素子形成領域115を得た。この素子分離技
術では従来のL O G O S (Local Ox
jdation of Silicon)に比人,バー
ズビークがないため、素子集積度を上げられる。また素
子形成領域と酸化領域の高さを同じにできるので、リソ
グラフイ工程において焦点ボケがない効果がある。
Next, an embodiment of the element isolation technology of the present invention will be described. Third
The figure shows the element isolation process. The silicon substrate 111 used was made by diffusing antimony to 10 μm on the surface of the p-type silicon substrate, and then thermally oxidizing the surface to form an oxide film 112 with a thickness of 50 nm.
was formed. After patterning, porous silicon 113 according to the present invention was formed. The forming conditions were the same as in the previous example, and the processing time was 30 minutes. Next, the substrate temperature is 800℃,
Oxidized bolus silicon (
O P O S: Oxidized Porous
Silicon) 114 was formed. The oxide layer on the surface was removed to obtain an element formation region 115. This element isolation technology uses conventional LOGOS (Local Ox
Since there is no bird's beak in the semiconductor device (dation of silicon), the degree of device integration can be increased. Furthermore, since the height of the element formation region and the oxidation region can be made the same, there is an effect that there is no out of focus in the lithography process.

次に本発明のS O I (Silicon on I
nsulator)への一実施例を述べる。第4図はS
OI形成工程を示す。用いた基板は表面に5μmの熱酸
化膜211を有するシリコン単結晶基板212(P型,
面方位(100),比抵抗20Ω・am)とシリコン単
結晶基板2↓3 (p型,面方位(100),比抵抗2
0Ω・国)である。シリコン単結晶基板212と213
を貼り合せ後、常圧酸素雰囲気中で1150℃、2時間
熱処理した。次に機械研摩及び化学研摩によってシリコ
ン単結晶基板212の背面を残厚2μmまで削った。次
にマスク用酸化膜2王4を形成後、本発明によるポーラ
ス状シリコン215を形成した。形成条件は先の素子分
離工程と同じである。次に基板温度800℃、30分の
ドライ酸化によって酸化ポーラス状シリコン216を形
威した。最終にマスク用酸化膜214を除去し、素子形
成領域217を得た。このSOI形成法は従来法に比べ
低コストかつ結晶状態の極めて優れた素子形戊領域を形
成できる効果がある。
Next, the SOI (Silicon on I) of the present invention
An example of this will be described below. Figure 4 shows S
The OI formation process is shown. The substrate used was a silicon single crystal substrate 212 (P type,
Plane orientation (100), resistivity 20Ω・am) and silicon single crystal substrate 2↓3 (p-type, plane orientation (100), resistivity 2
0Ω・Country). Silicon single crystal substrates 212 and 213
After bonding, heat treatment was performed at 1150° C. for 2 hours in a normal pressure oxygen atmosphere. Next, the back surface of the silicon single crystal substrate 212 was ground down to a remaining thickness of 2 μm by mechanical polishing and chemical polishing. Next, after forming the mask oxide film 2 and 4, porous silicon 215 according to the present invention was formed. The formation conditions are the same as in the previous element isolation step. Next, oxidized porous silicon 216 was formed by dry oxidation at a substrate temperature of 800° C. for 30 minutes. Finally, the mask oxide film 214 was removed to obtain an element formation region 217. This SOI formation method has the effect of forming an element-shaped region at a lower cost and having an extremely excellent crystalline state than conventional methods.

次に本発明による完全分離技術(FullIsolat
ion by Porous Oxidized Si
licon, FIPOS)への一実施例を述べる。第
5図はFIPOS形成工程である。p型シリコン基板3
01(面方位(100),比抵抗20Ω・o,ボロンド
ープ)上に窒化シリコン302及びレジスト303を形
成しボロンイオン注入によってp十層304を形成する
。次にレジスト303を除去後,水素イオン注入によっ
てn層305を形成する。次に第6図に示すポーラス状
シリコン形成装置によってFI POS構造を形戊する
。装置の構戒は第1図に示した装置に電極401,直流
電源402と金線403を設け、基板404にバイアス
電圧を印加できるようになっていた。基板温度850℃
,N F s流量47の/分,Hz流R l cc /
分、圧力1.1丁orr ,バイアス電圧50Vで3時
間、基板404を処理することによってボーラス状シリ
コン306を形成した。次に水蒸気雰囲気中で熱酸化す
ることでポーラス状シリコン酸化物307を形成する。
Next, the complete separation technology according to the present invention (FullIsolat)
ion by Porous Oxidized Si
An example of this will be described below. FIG. 5 shows the FIPOS formation process. p-type silicon substrate 3
Silicon nitride 302 and resist 303 are formed on 01 (plane orientation (100), specific resistance 20 Ω·o, boron doped), and a p-type layer 304 is formed by boron ion implantation. Next, after removing the resist 303, an n layer 305 is formed by hydrogen ion implantation. Next, an FI POS structure is formed using a porous silicon forming apparatus shown in FIG. The configuration of the device was as shown in FIG. 1, with an electrode 401, a DC power source 402, and a gold wire 403 so that a bias voltage could be applied to a substrate 404. Substrate temperature 850℃
, N F s flow rate 47/min, Hz flow R l cc /
A bolus of silicon 306 was formed by treating the substrate 404 for 3 hours at a pressure of 1.1 orr and a bias voltage of 50V. Next, porous silicon oxide 307 is formed by thermal oxidation in a steam atmosphere.

このときの熱処理温度が700℃以上の場合、水素イオ
ン注入で発生したドナーは消滅し、P形シリコン層30
8を得る。また700℃以下で熱酸化すればn型シリコ
ンJl309を得る.〔発明の効果〕 本発明によれば、高純度ガスを用いるドライプロセスに
よってポーラス状シリコンを形成できるので従来の陽極
反応によるウエットプロセスに比ベフッ化水素水溶液の
容器や金属電極からの不純物汚染がないので高純度なボ
ーラス状シリコンを形成できる。またポーラス状シリコ
ンを酸化することにより素子分離領域を形戒できる。ま
た、基板に誘電体分離基板を用いることでSOI構造デ
バイスの製造もできる。さらにボーラス状シリコンの形
成時に基板に電界をかけることによってボーラス状シリ
コンの形成領域を制御でき、FIPOS構造も形成でき
る。
If the heat treatment temperature at this time is 700°C or higher, the donors generated by the hydrogen ion implantation disappear, and the P-type silicon layer 30
Get 8. In addition, if thermal oxidation is performed at a temperature below 700°C, n-type silicon Jl309 can be obtained. [Effects of the Invention] According to the present invention, porous silicon can be formed by a dry process using high-purity gas, so there is no impurity contamination from the hydrogen fluoride aqueous solution container or metal electrode compared to the conventional wet process using an anode reaction. Therefore, it is possible to form a bolus of highly pure silicon. Furthermore, element isolation regions can be formed by oxidizing porous silicon. Further, by using a dielectric isolation substrate as a substrate, an SOI structure device can also be manufactured. Furthermore, by applying an electric field to the substrate during the formation of bolus-shaped silicon, the formation region of bolus-shaped silicon can be controlled, and a FIPOS structure can also be formed.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例の概略図、第2図は処理時間
とボーラス状シリコン膜の膜厚との関係図で、第3図は
素子分離工程の流れ図、第4図はSOI形成工程の流れ
図、第5図はFIPOS形成工程の流れ図、第6図はF
IPOS形成用のボーラス状シリコン形成装置を示す図
である611・・・石英製反応容器、12・・・シリコ
ン基板、13・・・炭素サセプタ, 14・・・モーター l5・・・赤 外線加熱器、 1 6・・・NF3 ガス、 17・・・水素ガス、 20・・・ガス供給管、 21・・・ロータリポンプ。 第 3 図 第 1 図 1S 第 2 図 忽I!畔P:IC分) 第 4 図 第 5 図 第6図 HzNFz 4−t)Z
Fig. 1 is a schematic diagram of an embodiment of the present invention, Fig. 2 is a diagram showing the relationship between processing time and bolus silicon film thickness, Fig. 3 is a flowchart of the element isolation process, and Fig. 4 is a SOI formation Process flowchart, Figure 5 is a flowchart of the FIPOS formation process, Figure 6 is F
611... Quartz reaction vessel, 12... Silicon substrate, 13... Carbon susceptor, 14... Motor 15... Infrared heater, 1 6...NF3 gas, 17...Hydrogen gas, 20...Gas supply pipe, 21...Rotary pump. Figure 3 Figure 1 Figure 1S Figure 2 I! P: IC minute) Fig. 4 Fig. 5 Fig. 6 HzNFz 4-t)Z

Claims (1)

【特許請求の範囲】 1、反応容器と、反応容器内の処理すべきシリコン基板
を加熱する手段と、反応容器へ反応ガスを供給する手段
と、反応後のガスを排出する手段より成る装置において
、シリコン基板を500℃以上に加熱し、反応容器内へ
フッ素元素を含むガスを流す工程を含むことを特徴とす
る半導体装置の製造方法。 2、特許請求の範囲第1項において、フッ素元素を含む
ガスが三フッ化窒素(NF_3)、フッ化キセノン(X
eF_2)、三フッ化塩素(ClF_3)、フッ素(F
_2)ガスであることを特徴とする半導体装置の製造方
法。 3、特許請求の範囲第1項記載の工程の後、酸化工程を
含むことを特徴とする半導体装置の製造方法。 4、特許請求の範囲第3項記載の酸化工程によつて素子
分離領域を形成することを特徴とする半導体装置の製造
方法。 5、特許請求の範囲第1項記載の工程においてシリコン
基板が表面に酸化膜を有するシリコン基板と別のシリコ
ン基板とを接合した誘電体分離基板であることを特徴と
する半導体装置の製造方法。 6、特許請求の範囲第5項記載の工程の後、酸化工程を
含むことを特徴とする半導体装置の製造方法。 7、特許請求の範囲第6項記載の酸化工程によつて素子
分離領域を形成し、SOI(SilicononIns
ulator)構造を形成することを特徴とする半導体
装置の製造方法。 8、特許請求の範囲第1項記載の半導体装置の製造装置
においてシリコン基板に電界をかけるための電極を含む
ことを特徴とする半導体装置の製造装置。 9、特許請求の範囲第8項記載の製造装置によつてFI
POS(FullIsolationbyPorous
OxidizedSilicon)構造を形成する工程
を含むことを特徴とする半導体装置の製造方法。
[Claims] 1. An apparatus comprising a reaction vessel, a means for heating a silicon substrate to be processed in the reaction vessel, a means for supplying a reaction gas to the reaction vessel, and a means for discharging the gas after the reaction. A method for manufacturing a semiconductor device, comprising the steps of heating a silicon substrate to 500° C. or higher and flowing a gas containing elemental fluorine into a reaction container. 2. In claim 1, the gas containing elemental fluorine is nitrogen trifluoride (NF_3), xenon fluoride (X
eF_2), chlorine trifluoride (ClF_3), fluorine (F
_2) A method for manufacturing a semiconductor device characterized by using gas. 3. A method for manufacturing a semiconductor device, which comprises an oxidation step after the step recited in claim 1. 4. A method for manufacturing a semiconductor device, characterized in that an element isolation region is formed by the oxidation step according to claim 3. 5. A method of manufacturing a semiconductor device in the step described in claim 1, wherein the silicon substrate is a dielectrically isolated substrate in which a silicon substrate having an oxide film on the surface and another silicon substrate are bonded together. 6. A method for manufacturing a semiconductor device, comprising an oxidation step after the step according to claim 5. 7. An element isolation region is formed by the oxidation process described in claim 6, and SOI (Silicon Ins.
1. A method for manufacturing a semiconductor device, the method comprising forming a ulator structure. 8. A semiconductor device manufacturing apparatus according to claim 1, further comprising an electrode for applying an electric field to a silicon substrate. 9. FI by the manufacturing apparatus according to claim 8
POS (Full Isolation by Porous
1. A method of manufacturing a semiconductor device, the method comprising the step of forming an Oxidized Silicon structure.
JP23281789A 1989-09-11 1989-09-11 Manufacture of semiconductor device Pending JPH0397228A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23281789A JPH0397228A (en) 1989-09-11 1989-09-11 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23281789A JPH0397228A (en) 1989-09-11 1989-09-11 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH0397228A true JPH0397228A (en) 1991-04-23

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JP23281789A Pending JPH0397228A (en) 1989-09-11 1989-09-11 Manufacture of semiconductor device

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000051938A1 (en) * 1999-03-04 2000-09-08 Surface Technology Systems Limited Chlorotrifluorine gas generator system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000051938A1 (en) * 1999-03-04 2000-09-08 Surface Technology Systems Limited Chlorotrifluorine gas generator system
JP2002538068A (en) * 1999-03-04 2002-11-12 サーフィス テクノロジー システムズ ピーエルシー Chlorine trifluoride gas generator
JP4689841B2 (en) * 1999-03-04 2011-05-25 サーフィス テクノロジー システムズ ピーエルシー Chlorine trifluoride gas generator

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