JPH0397197A - Memory cell - Google Patents

Abstract

PURPOSE:To eliminate the need for rewriting a memory cell data at reapplication of power by writing a latched data to a static RAM at application of power to the memory cell so as to store the data even when the power is interrupted. CONSTITUTION:The cell is provided with write transistors (TRs) 20A, 20B and bus TRs 24A, 24B storing a data stored in a memory section 10 at interruption of power of the memory section 10. Moreover, a control gate line 26 for applying an operating voltage to store the data to be stored into the write transistors (TRs) 20A, 20B and a word line 28 delivering a signal to activate the bus TRs 24A, 24B when the data stored in the memory section 10 is read to the bit lines 16A, 16B are provided. Thus, even when power is interrupted, since the data stored in an SRAM is backed up, it is not required to rewrite the data into the memory cell at reapplication of the power.

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention is applicable to static RAM <SRAM> as a memory for storing configuration data, for example.
).

[Prior art] Static R that stores configuration data
AM memory cells include those shown in FIG. This SRAM, unlike a dynamic RAM (DRAM), continues to hold stored data as long as the power supply Vdd is applied. In addition, in the figure, the reference numeral 10 indicates, for example, a complementary metal oxide semiconductor <CMOS).
12 is a pass transistor selected for each row to connect the memory section 10 to bit lines 168 and 16B; 14 is a bus transistor 1;
2 and a word line for transmitting a row selection signal, 16A, 1
6B is a bit line for transmitting data (O/1) when writing the data to the memory section 10. In the memory cell as described above, the voltage i1! After the ta person, data is written in the memory unit 10, and the written data ("O/1") is used to write the n shown in FIG. 2, for example.
A switch 18 consisting of a channel MOS transistor is turned on/off to determine the conduction state between points A and B. However, in the memory cell made of the conventional SRAM, when the power is turned off, the data stored therein disappears, and when the power is turned on again, the data stored in the memory cell is lost.
There is a problem in that it is necessary to rewrite the data, which is complicated. The present invention was made in order to solve the above-mentioned conventional problems, and it is possible to retain data even if the power to the memory cell is cut off, and it is possible to rewrite data to the memory cell when the power is turned on again. The objective is to provide a memory cell that does not require (Means for Achieving the Object) The present invention provides a static RAM and data stored in the static RAM in a memory cell.
A data holding means for holding data when the power to the memory cell is disconnected, and a means for writing the held data to the static RAM when the power is turned on to the memory cell. By doing so, the above-mentioned problem has been achieved.

[Effect]

In general, in a memory cell consisting of a static RAM (SRAM), if the power supplied to the memory is cut off, the stored data will be erased. Therefore, in addition to the static RAM, the inventor decided to use a data holding means, such as a non-volatile memory (EPROM) element, which can store data even when the power supply M is turned off, in addition to the static RAM, and when the power supply is turned on, the data can be stored. The idea was to write the data held by the holding means into the SRAM. Therefore, even when the power is cut off, in order to back up and hold the data stored in the SRAM, the power There is no need to rewrite data to the memory cell when the data is turned on again.Therefore, there is no need to worry about rewriting, and a memory cell having an SRAM can be used as a ROM.

【Example】

Embodiments of the present invention will be described below with reference to the drawings. In this embodiment, data to be stored in the memory section 10 as shown in FIG.
1. :Writing transistors 2OA, 20 for writing, consisting of floating gut type transistors, for example.
B, the writing transistors 2OA and 20B, and the floating gates 22A and 22B are common to the memory section 10.
pass transistors 24A, 24B for holding data to be stored in the memory section 10 when power is cut off; and transistors 20A, 20 for writing the data to be stored.
To B&! When storing, the transistors 20A and 20B
control gate line 26 for applying operating voltage to
, the data stored in the memory section 10 is transferred to the bit line 16A.
, 16B, the pass transistors 24A, 24
This is a memory cell having a word line 28 for transmitting a signal for activating B. The interference transistors 2OA, 20B and the bus transistors 24A, 24B are equipped with EPROMs (
writable ROM> can be used. The rest of the structure is the same as that of the memory cell shown in FIG. 2, so the same parts are given the same numbers and the explanation thereof will be omitted. Next, in the memory cell of the example, as shown in FIG.
The case of storing O) will be explained. First, data is written to bus transistors 24A and 24B. At this time, for example, 8V is applied to the pit line 16A, Ov is applied to the other bit line 16B, and the control gate I! Apply 12V to 26. This results in
Floating gate 2 of write transistor 2OA
2Al. :Bus transistor 24A due to charge accumulation
, 24B, data is stored and held. Note that during the above writing, the word line 28 is at the potential (O<@) (
(ground potential). Further, the pass transistor 24A has a floating gate 22AI,:. Because of the charge accumulation, its operable gate voltage becomes, for example, 5.2V or more, and since the other bus transistor 24B has no charge on its floating gate 22B, its operable gate voltage becomes, for example, 2.5V or more. In a state where the power supply Vdd is applied to the memory section 10,
Each bit line 16A, 16B is set to O'R position, word line 2
For example, a voltage of 5V is applied to 8. As a result, in the memory unit 10, as shown in FIG. 1, 1 is stored in the left CMOS and O is stored in the right CMOS. This memory section 10 has electricity, l! As long as Vdd is applied, the stored data will continue to be stored no matter how many times it is read. Here, it is assumed that the power supply Vdd to the memory section 10 is cut off. In this case, the memory section 10 will erase the stored data. When the power is turned on again in the α state, no data exists in the memory 10 as it is. Therefore, an O potential is applied to each bit line 16A and 16B, and a voltage of 5V, for example, is applied to the word line 28.
The data held in the pass transistors 24A and 24B is written into the memory section 10. That is, each pass transistor 24A, 24B has a different operating gate voltage, for example, 5.2V or more and 2.5V or more, so if 5V is applied, for example, the bit
The bus transistor 24A on the bit side does not operate, the pass transistor 24B on the bit side operates, and the memory section 10
Data with 1 on the t side and O on the bit side will be stored. If the potential is applied to the pit lines 16A, 16B as described above, the original data (for example, 1/0) is reproduced in the memory section 10, but when a predetermined memory operating voltage (1/0) is applied to each bit line 16A, 16B, ), the original data and the inverted data (for example, ○/1) are stored in the memory section 10l. :Remembered. In addition, in the above embodiment, as an example of SRA~1, C
Although the memory section made of MOS is illustrated, the memory cell to which the present invention is applied is not limited to those having such a memory, and the present invention is also applicable to memory cells using other types of memory elements in SRAM. can do.

【Effect of the invention】

As explained above, according to the present invention, even if the power to the memory cell is cut off, the stored data is retained and there is no need to rewrite the data when the power is turned on again. The excellent effect of easy handling can be obtained.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the structure of a memory cell according to an embodiment of the present invention, and FIG. 2 is a circuit diagram showing an example of the structure of a conventional memory cell. 10...Memory part, 16A, 16B...Bit line, 2OA, 20B...Write transistor, 22A,
22B...Floating gate, 24A, 24B.
...pass transistor, 26...control gate line, 28...word line.

Claims (1)

[Claims] (1) A static RAM, a data holding means for holding the data stored in the static RAM when power to the memory cell is cut off, and a data holding means for holding the data stored in the static RAM when the power to the memory cell is turned off; and means for writing into the static RAM when the memory cell is in use.