JPH0397118A - Optical disk device - Google Patents

Abstract

PURPOSE:To stably detect a peak position even when the level of a difference signal is changed by the fluctuation of a reflectance, etc., by providing changeover switches to select a slice level fixer in the unlocked state of a PLL circuit, and to select a slice level varying device in the locked state. CONSTITUTION:When the PLL circuit is set in the unlocked state, a slice level fixer 16 is selected by changeover switches AS 3 and AS 4 and the pull-in operation of the PLL circuit to a clock signal is executed. When the PLL circuit once enters the locked state, a slice level varying device 17 is selected by the changeover switches AS 3 and AS 4. When the slice level varying device 17 is selected, the slice level of a zero point detector 11 with histeresis characteris tic is made variable corresponding to the detecting difference signal between a mirror area 2a and a clock flag sample area 2b. Thus, even when the level of the difference signal is changed by the fluctuation of the reflectance, etc., the peak position can be stably detected.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an optical disc device that reproduces, records, or erases information by irradiating a laser beam onto an optical information recording medium having a sample servo area on a track. .

2. Description of the Related Art In general, various write modulation methods have been considered for this type of optical disk device in order to increase the storage capacity. Also,
The read signal in this type of optical disk device includes information at the peak points or peak point intervals of the read signal waveform.

When identifying the above-mentioned peak point using various modulation methods, a low frequency component is generally superimposed on the read signal, and the peak amplitude varies depending on the low frequency component.

Therefore, it is difficult to detect the peak point based on the amplitude. be. For this reason, the readout signal is generally differentiated, the zero crossing point of the differentiated signal is detected, and this is used as a demodulation signal for peak position detection.

At this time, according to Japanese Patent Application Laid-Open No. 50-39118, in order to prevent unnecessary switching of the zero point detector due to noise etc., the zero point detector is provided with a hysteresis characteristic as shown in Fig. 9(a). Alternatively, countermeasures have been taken, such as slicing the read signal at certain positive and negative levels to create a gate signal and ANDing it with the output signal of the zero point detector.

However, the problem that the invention aims to solve is that even the method described in the publication causes errors in clock detection.

Consider this point. First, the target sample servo system will be explained with reference to Fig. 6. A sample servo type disk has a sample servo area 2 and a data area 3 on track l, and within the sample servo area 2, a mirror area 2a of a certain reference level and a clock flag sample area for detecting a clock signal. 2b are provided at specified positions. Now, as shown in the same figure (b)? Depending on the presence or absence of Ribit 4, mirror area 2a
Assuming that the clock flag sample area 2b and the clock flag sample area 2b are areas with different reflectances, the RF
The clock can be detected as a change in the sum signal. Furthermore, if the mirror area 2a and the clock flag sample area 2b are magnetized regions different in S and N as shown in FIG. The clock can be detected as an RF difference signal (magneto-optical signal) as shown in FIG.

The peak position detector 5 which receives such an RF signal as input is configured as shown in FIG. 7, for example. That is, it consists of a differentiator 6 using an OP amplifier and a zero point detector 7 with hysteresis characteristics using a converter. The output logic of the zero point detector 7 with hysteresis characteristics is such that the input voltage is at the slice level V.
When R E exceeds p+, roJ (5V
to OV), and the input voltage reaches the slice level V R
When the voltage drops below E■, rOJ becomes rlJ (OV to 5V). Here, VOH= VD+= 5 V
%Vo+. = O V , comparator input resistance,
If the feedback resistance is <R,,R, as shown in the figure, then VREF-=Vat. ．． −1=OR, 10R, .

Now, the mirror region 2a is a region having a certain reflectance, the clock flag sample region 2b is a region having a reflectance different from that of the mirror region 2a, and the input signal of the differentiator 6 is a signal detected by at least one pair of light receiving elements. If it is a sum signal, the amplitude level of this sum signal changes depending on the reflectance of the optical information recording medium or the quality of the pre-bit 4, so it can be detected by the signal detected when the laser beam passes through the clock flag sample area 2b or by the mirror area 2a. Is the difference signal amplitude between the optical information recording media or the same media? However, it is conceivable that variations may occur between the inner circumferential side and the outer circumferential side, although within a certain level.

Therefore, the output amplitude of the differentiator 6 also changes, and the slice level Vll. If , detected by PLL
The circuit may operate abnormally.

By the way, considering the noise resistance, the slice level VRE
When F+ is set high, the output amplitude of differentiator 6 becomes VRo■
The clock will not be detected in locations where the slice level does not exceed V.
If ■ is set low, the clock will be detected twice in some places due to the influence of noise. FIG. 8 shows the RF signal, the differential waveform of the RF signal, and the V R I according to FIG. 7.
! The signal whose zero point was detected is shown with p+ as the hysteresis slice level. The first half (left half) shows an example of the waveform when the clock position is detected normally, and the second half (right half) shows the waveform example when the signal amplitude has decreased and cannot be detected. show.

Further, as shown in FIG. 6(d), the mirror area 2a and the clock flag sample area 2b are made to have the same reflectance configuration, but are made to have different magnetization areas like the magneto-optical recording signal, and are applied to the differentiator 6. A difference signal (optical magnetic signal...Fig. 6 (e
)), the amplitude level of this difference signal will also vary between optical information recording media, or even within the same medium between the inner and outer circumferential sides.
Due to changes in reflectance, recording conditions, changes in modulation degree, etc.
Since variations occur, there is a problem similar to that of clock detection using the sum signal described above.

Means for Solving the Problems A laser beam is irradiated onto an optical information recording medium having a sample servo area including at least a clock flag sample area and a mirror area on a track, and based on the reflected light from the optical information recording medium, at least A differentiator that differentiates the sum signal or difference signal of the signals detected by a pair of light receiving elements, and a zero point with hysteresis characteristics that detects the alternating current zero point of the output from this differentiator using a slice level and converts it into a rectangular wave signal. The invention according to claim 1 provides an optical disc device comprising a peak position detector consisting of a detector, and a PLL circuit that synchronizes using an output from the zero point detector in the clock flag sample area as a basic timing signal. , a difference signal detector is provided to detect a difference signal between the detection signal in the mirror region and the detection signal in the clock flag sample region, and a zero point detector with hysteresis characteristic is sliced in proportion to the difference signal by the difference signal detector. A slice level variable device that varies the level and a slice level fixing device that fixes the slice level of the zero point detector with hysteresis characteristics to a predetermined value are provided, and the slice level fixing device is selected when the PLL circuit is in an unlocked state and is selected when the PLL circuit is in a locked state. A changeover switch is provided to select the slice level variable device.

Further, in the invention according to claim 2, a difference signal detector is provided to detect a difference signal between the detection signal in the mirror area and the detection signal in the clock flag sample area, and the level of the difference signal by the difference signal detector is adjusted. A gain variable device that varies the gain of the signal detection amplifier to maintain it at a constant value and a gain fixer that fixes the gain of the signal detection amplifier to a predetermined value are provided, and the gain fixer is selected when the PLL circuit is in an unlocked state. A changeover switch is provided to select the variable gain when in the locked state.

When the working PLL circuit is in the unlocked state, the slice level fixer or gain fixer is selected by the changeover switch, and the slice level of the zero point detector with hysteresis characteristic is fixed at a predetermined value or the gain of the signal detection amplifier is fixed. With the clock signal fixed at a predetermined value, the PLL circuit performs a synchronization pull-in operation with respect to the clock signal. However, P
Once the LL circuit enters the locked state, the slice level variable device or the gain variable device is selected by the changeover switch. When the slice level variable device is selected, the slice level of the zero point detector with hysteresis characteristic is varied according to the detected difference signal between the mirror area and the clock flag sample area, so that it is Even if the difference signal level changes, the peak position can be detected stably. The same is true when a variable gain amplifier is selected; the gain of the signal detection amplifier is automatically varied so that the detected difference signal between the mirror area and the clock flag sample area is always maintained at a constant value, so The peak position can always be detected stably even at high levels.

Embodiment An embodiment of the invention set forth in claim 1 will be described based on FIGS. 1 and 2. FIG. First, FIG. 7 consists of a differentiator 10 having an OP amplifier configuration and receiving an RF signal (a sum signal or a difference signal of signals detected by a pair of light receiving elements), and a zero point detector 11 with a hysteresis characteristic having a comparator configuration. A peak position detector 12 similar to the above is provided.

Further, there is provided a difference signal detector 13 having an OP amplifier configuration, which receives the RF signal as input and detects a difference signal between a detection signal from the mirror area in the sample servo area and a detection signal from the clock flag sample area. Here, a sample hold circuit 1 is provided at the input and output of the difference signal detector l3, respectively.
4.15 is connected. Sample hold circuit 14
is an analog switch ASI connected to one input side of the OP amplifier and operated by the H level of a predetermined mirror sample pulse T1, and a capacitor C. It becomes more. The sample and hold circuit l5 is also an analog switch AS which is activated by the H level of a predetermined clock flag sample pulse T2.
2 and a capacitor C1. Also, resistors R, , connected to the input side of the OP amplifier forming the difference signal detector 13
R4 is R, = R4, input and feedback resistance R,, R, is R
, = R.

Furthermore, a slice level fixer l6 and a slice level variable device l7 are connected in parallel to the reference voltage side of the zero point detector 11 with hysteresis characteristics. The slice level fixer l6 consists of a resistor R, and the slice level variable device l7 consists of a voltage/resistance conversion circuit made up of an FETI8 and resistors R, , R, and a low-pass filter ( The voltage value is varied via the LPF (LPF) 19. Moreover, analog switches AS3 and AS4 as changeover switches are interposed between the slice level fixer l6, the slice level variable device 17, and the zero point detector l1 with hysteresis characteristics, respectively. These analog switches AS3 and AS4 are switched and controlled by the same signal, specifically, the H level of PLL READY depending on the locked/unlocked state of the PLL circuit, but an inverter 20 is interposed in one of them so that the reverse operation occurs. is set to.

Here, the pulses TI and T2 are P as shown in FIG.
This is a timing pulse that can be output after the LL circuit is in the locked state, but is not output when the LL circuit is in the non-locked state. However, after locking the PLL circuit and before outputting PLL READY, pulses TI and T2 are output at least l times to make the difference signal hold output value unstable (in the initial state, the hold voltage of capacitor C1 is OV (or undefined) is canceled in advance, and the slice level is set to be normal immediately when the analog switch AS4 is turned on.

In such a configuration, when the PLL circuit is in an unlocked state as an initial state, the analog switch AS3 is on and the analog switch AS4 is off.

Therefore, the zero point detector 1l with hysteresis characteristic performs a peak position detection operation at a fixed slice level determined by , and synchronizes the PLL circuit with respect to the clock signal.

Therefore, once the PLL circuit enters the locked state, the second
As shown in the figure, timing pulses TI and T2 in the mirror area and clock flag sample area are output, and furthermore, the PLL READY signal becomes H level. When the pulse Tl is input, the analog switch ASI is turned on and the mirror region level is sampled by the capacitor C1 and held at the timing of the L level of the pulse TI.

Next, at the timing of the H level of pulse T2 (analog switch AS2 is turned on), the level obtained by multiplying the difference between the mirror area level and the clock flag sample area level by R, /R, is sampled into capacitor C3, and the L When the level is reached, it will be held.

Further, the analog switch AS4 is turned on and the analog switch AS3 is turned off.

The difference signal held by the difference signal detector 13 is not sliced very sensitively even if a few samples of abnormal RF signals are obtained, such as reflectance fluctuations due to scratches or dust on the optical information recording medium. In order to prevent the level from fluctuating, it is applied as the gate-source voltage of FET1g through LPFI9 with an appropriate time constant, and is applied to the drain-source voltage of FET18.
The source resistance RD8 is controlled (there is a part where the drain-source resistance R.S changes linearly when the gate-source voltage is changed), and the hysteresis slice level VR
εl-ya is varied as follows.

That is, as the level of the difference signal increases, the gate-source voltage increases and the drain-source resistance RDs increases, so that the slice level V R E F + also increases. Conversely, when the level of the difference signal decreases, the slice level VIIEF+ decreases. Therefore, even if the level of the RF signal changes, the slice level of the zero point detector I1 with hysteresis characteristics is varied accordingly, so that stable peak position detection is always possible.

Next, an embodiment of the invention according to claim 2 will be described with reference to FIGS. 3 to 5. The same parts as those shown in the previous embodiment are indicated using the same reference numerals.

This embodiment relates to the input stage of the peak position detector l2, in which a signal detection amplifier 21 having a non-inverting amplifier configuration that receives an input of an RF signal is connected to a differentiating circuit 10 and an analog switch AS.
It is provided in the front stage of I.

This signal detection amplifier 21 has a feedback resistor R + a, and a gain fixer 22 and a gain variable device 23 are connected in parallel to the inverting input side. Gain fixer 22
is made up of a resistor R + +, and the gain variable device 23 is an FET.
24 and resistors R Ill R, , (signal detection amplifier 2l and FET 24 form a voltage control amplifier
= AGC circuit is configured).

Further, analog switches AS5 and AS6 as changeover switches are interposed between the gain fixer 22, the gain variable device 23, and the signal detection amplifier 21, respectively. These analog switches AS3 and AS4 have the same signal, specifically the lock type of the PLL circuit! ll! Switching is controlled by the H level of PLL READY corresponding to the I/unlocked state, but an inverter 25 is interposed on one side and set to operate in the opposite direction. Further, an integrator 26 having an OP amplifier configuration is connected to the output side of the sample and hold circuit l5 to stabilize the system, and its output is connected to the FE.
It is fed back to T24.

In such a configuration, when the PLL circuit is in an unlocked state, the analog switch AS5 is turned on as an initial state.
AS6 is turned off, and the gain fixer 22 is connected to the signal detection amplifier 21, resulting in an amplifier with a fixed gain (gain G = 1 + (R, ./R
．． ,) ). A signal obtained by multiplying the input RF signal by this fixed gain is sent to the differentiating circuit IO, where the peak position is detected as described above, and the PLL circuit is pulled into synchronization.

Once the PLL circuit enters the locked state, sampling timing pulses TI and T2 are output in the mirror area and the clock flag sample area, and furthermore, the PLL circuit
The L READY signal becomes H level, the analog switch AS6 is turned on, and the analog switch AS5 is turned off. In this state, by the same operation as in the previous embodiment, the level difference between the mirror area and the clock flag sample area is R,
The level multiplied by /R is the capacitor C. sampled/held.

For example, suppose that the drain-source resistance of the FET 24 is controlled by a negative gate-source voltage, and when the gain characteristic of the signal detection amplifier 21 has at least a monotonically decreasing characteristic as shown in FIG. so that the held voltage matches the target voltage set to an appropriate value (when the target voltage is VREF, the sum of the hold voltage VC of capacitor C and -VREF becomes OV). ), the gain of the signal detection amplifier 2l is variably controlled.

Here, the operation of the system will be briefly explained with reference to FIG.

Suppose now that a gain GRI matching the target voltage is obtained, for example, with V a s =V C SR1. Therefore,
V when the input difference signal level becomes small. ．． becomes smaller,
VC- VREF (O), so the output voltage of the integrator 26 moves to the positive side. That is, the gain increases in the direction of the arrow ■ in FIG. 5, and V matches V R E F. s=V.s1, G=CI1, On the other hand, when the input difference signal level increases, VC,
Since VREF > O, the integrator 26's ? The force voltage moves to the negative side. That is, the gain decreases in the direction of the arrow (■) in FIG. 5, and V.I. ．．
=-V. S■, G=GR, . Therefore, P
Once the LL circuit is locked, an RFAcc signal is obtained in which the level difference between the mirror area and the clock flag sample area is always a constant value. Therefore, the peak position detector 12 is configured as shown in FIG. , stable peak position detection = binary signal can be obtained.

Effects of the Invention As described above, the present invention provides a difference signal detector for detecting a difference signal between a detection signal in a mirror region and a detection signal in a clock flag sample region; a slice level variable device that varies the slice level of the zero point detector with hysteresis characteristic in proportion to the difference signal from the device; a slice level fixing device that fixes the slice level of the zero point detector with hysteresis characteristic to a predetermined value; and a PLL circuit. In the invention according to claim 2, there is provided a changeover switch for selecting the slice level fixing device in the unlocked state and selecting the slice level variable device in the locked state,
A difference signal detector that detects the difference signal between the detection signal in the mirror area and the detection signal in the clock flag sample area, and the gain of the signal detection amplifier to maintain the level of the difference signal from the difference signal detector at a constant value. a gain variable device that varies the gain of the signal detection amplifier, a gain fixing device that fixes the gain of the signal detection amplifier to a predetermined value, and a changeover switch that selects the gain fixing device when the PLL circuit is in an unlocked state and selects the gain variable device when it is in a locked state. Therefore, when the PLL circuit is in the locked state, the slice level variable device or the gain variable device is selected, and the slice of the zero point detector with hysteresis characteristic is selected according to the detected difference signal between the mirror area and the clock flag sample area. The level is varied, or the gain of the signal detection amplifier is automatically varied so that the detection difference signal between the mirror area and the clock flag sample area is always maintained at a constant value, and the reflection of the optical information recording medium Even if the difference signal level changes due to rate fluctuations, etc., the peak position of the RF signal can be stably detected.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the invention as claimed in claim 1,
Fig. 2 is a timing chart showing its operation, Fig. 3 is a circuit diagram showing an embodiment of the invention as claimed in claim 2, Fig. 4 is a timing chart showing its operation, and Fig. 5 is a gain characteristic diagram of the VCA. , Fig. 6 is an explanatory diagram showing the principle of the sample servo system, Fig. 7 is a circuit diagram showing a conventional peak position detector, Fig. 8 is a timing chart showing its operation, and Fig. 9 is an explanatory diagram showing the principle of the sample servo method.
The figure is a waveform diagram showing characteristics depending on whether or not there is a hysteresis characteristic. 2...Sample servo area, 2a...Mirror area,
2b... Clock flag sample area, lO... Differentiator, 11... Zero point detector with hysteresis characteristic, 1
2...Peak position detector, 13...Difference signal detector,
16... Slice level fixed level controller, 17... Slice level variable device, 21... Signal detection amplifier, 22...
Gain fixed device, 23...gain variable device

Claims (1)

[Claims] 1. A laser beam is irradiated onto an optical information recording medium having a sample servo area including at least a clock flag sample area and a mirror area on a track, and based on the reflected light from the optical information recording medium, A differentiator that differentiates the sum signal or difference signal of signals detected by at least a pair of light receiving elements, and a hysteresis characteristic that detects the alternating current zero point of the output from this differentiator using a slice level and converts it into a rectangular wave signal. Equipped with a peak position detector consisting of a zero point detector,
A PLL that synchronizes using the output from the zero point detector in the clock flag sample area as a basic timing signal.
In an optical disk device equipped with a circuit, a difference signal detector for detecting a difference signal between a detection signal in the mirror area and a detection signal in the clock flag sample area is provided, and a difference signal detected by the difference signal detector is proportional to the difference signal. a slice level variable device for varying the slice level of the zero point detector with hysteresis characteristic; and a slice level fixing device for fixing the slice level of the zero point detector with hysteresis characteristic at a predetermined value; An optical disc device characterized in that a changeover switch is provided that selects the slice level fixing device when in a locked state and selects the slice level variable device when in a locked state. 2. A laser beam is irradiated onto an optical information recording medium having a sample servo area on a track including at least a clock flag sample area and a mirror area, and at least one pair of light receiving elements detects the reflected light from the optical information recording medium. It consists of a differentiator that differentiates the sum signal or difference signal of the detected signals, and a zero point detector with hysteresis characteristics that detects the alternating current zero point of the output from the differentiator using a slice level and converts it into a rectangular wave signal. Equipped with a peak position detector,
A PLL that synchronizes using the output from the zero point detector in the clock flag sample area as a basic timing signal.
In an optical disk device equipped with a circuit, a difference signal detector for detecting a difference signal between a detection signal in the mirror area and a detection signal in the clock flag sample area is provided, and the level of the difference signal by the difference signal detector is determined. A gain variable device that varies the gain of the signal detection amplifier to maintain it at a constant value, and a gain fixer that fixes the gain of the signal detection amplifier to a predetermined value are provided, and the gain is fixed when the PLL circuit is in an unlocked state. 1. An optical disc device comprising: a changeover switch for selecting a variable gain device and selecting the variable gain device when in a locked state.