JPH0396922A - Matrix type display device - Google Patents

Matrix type display device

Info

Publication number
JPH0396922A
JPH0396922A JP1233461A JP23346189A JPH0396922A JP H0396922 A JPH0396922 A JP H0396922A JP 1233461 A JP1233461 A JP 1233461A JP 23346189 A JP23346189 A JP 23346189A JP H0396922 A JPH0396922 A JP H0396922A
Authority
JP
Japan
Prior art keywords
electrode
storage capacitor
gate electrode
line
stage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1233461A
Other languages
Japanese (ja)
Inventor
Hirokazu Sakamoto
阪本 弘和
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP1233461A priority Critical patent/JPH0396922A/en
Publication of JPH0396922A publication Critical patent/JPH0396922A/en
Pending legal-status Critical Current

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  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

PURPOSE:To obtain necessary capacity without decreasing the aperture rate of a picture element by forming one electrode of a storage capacitor by using a transparent conductive film, connecting this electrode to the gate electrode line of the precedent stage, and using a picture element electrode as the other electrode, and forming an insulating film between both the electrodes. CONSTITUTION:On a transparent insulating substrate 10 of glass, etc., the transparent conductive film of an ITO, etc., is deposited by an EB vapor-depositing method, etc. Then this film is patterned by normal etching, etc., to form an island-shaped storage capacitor electrode 1. This is patterned by photoetching, etc., to form a gate electrode line 3. At such a time, the gate electrode line of the precedent stage and the electrode 1 of the storage capacitor are connected electrically. Therefore, the picture element of the 1st stage has no precedent stage, so a gate electrode line corresponding to a (0)th stage is formed and this and the electrode 1 of the storage capacitor of the 1st stage are connected. Then the transparent electrode of an ITO, etc., is patterned in an island shape to form the picture element electrode 8 and then the insulating film is formed between the electrodes 1 and 8.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、マトリクス型素示装置に関するものである
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a matrix type display device.

〔従来の技術〕[Conventional technology]

マトリクス型表示装置は、通常2枚の対向する基板の間
に液晶等の表示材料が挾持され、この表示材料に選択的
に電圧を印加するように構成されている。上記基板の少
なくとも一方には、マトリクス状に配列した画素電極を
設け、これらの画素電極に選択的に電圧を印加するため
に、各画素電極毎にトランジスタ等の能動素子を設けて
いる。
A matrix type display device is usually configured such that a display material such as a liquid crystal is sandwiched between two opposing substrates, and a voltage is selectively applied to the display material. Pixel electrodes arranged in a matrix are provided on at least one of the substrates, and an active element such as a transistor is provided for each pixel electrode in order to selectively apply a voltage to these pixel electrodes.

さらに、画質を向上するために、各画素毎にストレージ
キャパシタを設けている。
Furthermore, in order to improve image quality, a storage capacitor is provided for each pixel.

従来、この種の装置として、第4図から第6図に示すも
のがあった。第4図は、従来の液晶表示装置に用いられ
る薄膜トランジスタ(以下「TFTJ価回路図である。
Conventionally, there have been devices of this type as shown in FIGS. 4 to 6. FIG. 4 is a circuit diagram of a thin film transistor (hereinafter referred to as "TFTJ") used in a conventional liquid crystal display device.

第4図乃至第5図において、α0は透明の絶縁性基板、
(1)はこの絶縁性基板(11上に形成されたインジウ
ム・すず酸化物(以下r ITOJという。)等の透明
導電膜からなるストレージキャパシタの一方のN.極、
(2)は絶縁膜、(3)はゲート電極線、(4)はゲー
ト絶縁膜、(5)は半導体膜、(6)はソース電極線、
(7)はドレイン電極、(8)はこのドレイン電極tこ
接続された画素電極、(9)は保護膜である。ストレー
ジキャパシタの一方の電極(1)は、液晶表示装置が動
作中は、常に一定の電位(通常チはアース電位)に保持
されるように、他の画素のストレージキャパシタの電極
と接続して専用の外部端子に接続されている。このため
、上記のストレージキャパシタの電極(1)をゲート電
極線(3)やソース電極線(6)と絶縁する必要があり
、電IBM (1)形成後に絶縁膜(2)が形成される
。なお、画素WL極(8)は、ストレージキャパシタの
他方の電極となっている。
In FIGS. 4 and 5, α0 is a transparent insulating substrate;
(1) is one N. pole of a storage capacitor made of a transparent conductive film such as indium tin oxide (hereinafter referred to as ITOJ) formed on this insulating substrate (11);
(2) is an insulating film, (3) is a gate electrode line, (4) is a gate insulating film, (5) is a semiconductor film, (6) is a source electrode line,
(7) is a drain electrode, (8) is a pixel electrode connected to this drain electrode, and (9) is a protective film. One electrode (1) of the storage capacitor is connected to the electrode of the storage capacitor of the other pixel so that it is always kept at a constant potential (usually ground potential) while the liquid crystal display device is in operation. connected to the external terminal of the Therefore, it is necessary to insulate the electrode (1) of the storage capacitor from the gate electrode line (3) and the source electrode line (6), and an insulating film (2) is formed after the electrode (1) is formed. Note that the pixel WL pole (8) serves as the other electrode of the storage capacitor.

また、他の従来例として第7図から第9図に示すものが
ある。第7図は他の従来例の要部を示す平面図、第8図
は第7図の■一■線断面図、第9図はその等価回路であ
る。第7図の構成のものは、まず透明の絶縁性基板(1
0J−にゲート電極線(3)を形成する。このとき、ス
トレージキャパシタの一方の電極(1)も同時に形威し
、前段のゲート電極線(3)と接続する。ストレージキ
ャパシタの一方の電極〈1)とゲート電極線(3)とを
このように接続してもよいのは、動作時に信号を走査す
る際、前段の走査ラインすなわち前段のゲート電極線は
、前段が走査されているとき以外は、アース電位になる
からである。
Further, as other conventional examples, there are those shown in FIGS. 7 to 9. FIG. 7 is a plan view showing the main parts of another conventional example, FIG. 8 is a cross-sectional view taken along line 1-2 in FIG. 7, and FIG. 9 is an equivalent circuit thereof. The structure shown in Fig. 7 first consists of a transparent insulating substrate (1
A gate electrode line (3) is formed at 0J-. At this time, one electrode (1) of the storage capacitor is also formed at the same time and connected to the previous gate electrode line (3). The reason why one electrode (1) of the storage capacitor and the gate electrode line (3) may be connected in this way is that when scanning signals during operation, the previous scanning line, that is, the previous gate electrode line, is connected to the previous scanning line. This is because it is at ground potential except when it is being scanned.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来のマトリクス型液晶表示装置は、以上のように構成
されているので、第4図に示したものでは、ストレージ
キャパシタ電極(1)の形成工程と絶縁膜(2)の形成
工程の二つの工程が必要であること、並びにストレージ
キャパシタ電極(1)とゲート電極線(3)及びソース
電極線(6)とが短絡することによる歩留低下を招くこ
と等の問題がある。
Since the conventional matrix type liquid crystal display device is constructed as described above, the one shown in FIG. There are problems such as a short circuit between the storage capacitor electrode (1), the gate electrode line (3), and the source electrode line (6), resulting in a decrease in yield.

また、第7図に示したものは、ストレージキャパシタ電
極を形成するための工程数は増加しないが、前段のゲー
ト電極線(3)をストレージキャパシタの電極(1)と
しており、このゲート電極線(3)は通常不透明な金属
で形成されるので、大きくしすぎると画素の開口率を下
げ、小さくすぎるとス1〜レージキャパシタとして必要
な容量が得られないというジレンマがあった。
In addition, in the case shown in FIG. 7, although the number of steps for forming the storage capacitor electrode is not increased, the gate electrode line (3) in the previous stage is used as the electrode (1) of the storage capacitor, and this gate electrode line ( 3) is usually made of opaque metal, so there was a dilemma that if it was made too large, the aperture ratio of the pixel would be lowered, and if it was too small, it would not be possible to obtain the necessary capacity as a storage capacitor.

この発明は、上記のような従来の問題点を解決するため
になされたもので、工程をあまり増やさず、画素の開口
率を低下させず、かつ上記の如き短絡による歩留低下を
招来しないマトリクス型表示装置を得ることを目的とし
ている。
This invention was made in order to solve the conventional problems as described above, and it is possible to create a matrix that does not significantly increase the number of steps, does not reduce the aperture ratio of pixels, and does not cause a decrease in yield due to short circuits as described above. The purpose is to obtain a type display device.

〔課題をM決するための手段〕[Means for deciding issues]

この発明に係るマトリクス型表示装置においては、スト
レージキャパシタの一方の電極を透明導電膜で形戚する
と共に前段のゲート電極線に接続し、他方の電極を画素
電極で兼用し、上記両電極間に絶縁膜を設けることによ
り、ストレージキャパシターを構威している。
In the matrix type display device according to the present invention, one electrode of the storage capacitor is formed with a transparent conductive film and connected to the gate electrode line of the previous stage, the other electrode is also used as the pixel electrode, and the space between the two electrodes is By providing an insulating film, a storage capacitor is constructed.

〔作 用〕[For production]

上記のように構威されたストレージキャパシタは、一方
の電極を透明導電膜で形威しているので、画素の開口率
が低下しない。また、この電極は、ゲート電極線やソー
ス電極線と交差しないので、短絡のおそれもない。
Since the storage capacitor constructed as described above has one electrode formed of a transparent conductive film, the aperture ratio of the pixel does not decrease. Further, since this electrode does not intersect with the gate electrode line or the source electrode line, there is no risk of short circuit.

〔実施例〕〔Example〕

第1図乃至第3図を参照してこの発明の一実施例を説明
する。第1図は、この発明の一実施例にT よる−fFTアレイ基板の要部を示す平面図、第2図は
第1図のト」線断面図、第3図はその等価回路図である
。第1図ないし第3図において、第4図乃至第9図と同
一符号は、それぞれ同一又は相当部分を示している。
An embodiment of the present invention will be described with reference to FIGS. 1 to 3. FIG. 1 is a plan view showing the main parts of a T-fFT array substrate according to an embodiment of the present invention, FIG. 2 is a sectional view taken along the line T in FIG. 1, and FIG. 3 is an equivalent circuit diagram thereof. . In FIGS. 1 to 3, the same reference numerals as in FIGS. 4 to 9 indicate the same or corresponding parts, respectively.

まず、ガラス等の透明の絶縁性基板0*上にITO等の
透明導電膜をEB蒸着法等で堆積する。その後、この膜
を通常のエッチング等でパターンニングし、アイランド
状のストレージキャパシタ電極(1)を形威する。次に
、スパッタ法等でCr又はMo等の金属を堆積し、これ
をホトエッチング等によりパターンニングして、ゲート
電極線(3)を形成する。このとき、前段のゲート電極
線(3)とストレージキャパシタの電極(】)が電気的
に接続されるようにする。従って、第1段目の画素には
前段がないので、第O段に相当するゲート電極線を形成
し、これと第1段のストレージキャパシタの電極(1)
とを接続する。
First, a transparent conductive film such as ITO is deposited on a transparent insulating substrate 0* such as glass by EB evaporation or the like. Thereafter, this film is patterned by ordinary etching or the like to form an island-shaped storage capacitor electrode (1). Next, a metal such as Cr or Mo is deposited by sputtering or the like, and patterned by photoetching or the like to form a gate electrode line (3). At this time, the gate electrode line (3) at the previous stage and the electrode (]) of the storage capacitor are electrically connected. Therefore, since the first stage pixel has no previous stage, a gate electrode line corresponding to the Oth stage is formed, and this and the first stage storage capacitor electrode (1) are formed.
Connect with.

次に、絶縁膜(4)となるシリコン窒化膜( S l 
3N4 )又はシリコン酸化膜(5102)等、及び半
導体膜(5)となる水素化アモルファスシリコノ(a−
Si:H)等をCVD法等により連続して堆積する。次
いで、半導体膜をアイランド状にパターン加工し、さら
に絶縁膜(4)をパターン加丁する。絶縁膜(4)はゲ
ート絶縁膜およびストレージキャパシタの電極間の絶縁
膜となる。
Next, a silicon nitride film (S l
3N4) or silicon oxide film (5102), and hydrogenated amorphous silicone (a-
Si:H) etc. are continuously deposited by CVD method or the like. Next, the semiconductor film is patterned into an island shape, and the insulating film (4) is further patterned. The insulating film (4) serves as a gate insulating film and an insulating film between the electrodes of the storage capacitor.

次に、Ae又はMo等の金属をスパッタ法等で堆積し、
パターン加工してソース電極線(6)とドレイン電極(
7)を形成する。次に、ITO等の透明導電膜をEB法
等で堆積し、さらにこれをアイランド状にパターン加工
して画素電極(8)を形成する。その後、Si3N4又
はS i 02等をCVD法で堆積し、パターン加工し
て保護膜(9)を形成する。
Next, a metal such as Ae or Mo is deposited by sputtering or the like,
After patterning, the source electrode line (6) and drain electrode (
7). Next, a transparent conductive film such as ITO is deposited by EB method or the like, and this is further patterned into an island shape to form a pixel electrode (8). Thereafter, Si3N4 or Si02 or the like is deposited by CVD and patterned to form a protective film (9).

この実施例においては、透明導電膜からなる電極(1)
,画素電極(8)及びこれらの電極間の絶縁膜(4)で
ストレージキャパシタを構成している。
In this example, an electrode (1) made of a transparent conductive film
, a pixel electrode (8), and an insulating film (4) between these electrodes constitute a storage capacitor.

このようにして形成したTFT アレイ基板と、透明導
電電極及びカラーフィルタ等を有する対向電極基板との
間に液晶等の表示材料を挾持して、マトリクス型表示装
置が構成される。
A matrix type display device is constructed by sandwiching a display material such as a liquid crystal between the thus formed TFT array substrate and a counter electrode substrate having transparent conductive electrodes, color filters, etc.

なお、上記の実施例では、まずストレージキャパシタの
一方のN tFM (].)を形成した後で、ゲート電
極線(3)を形成する方法を説明したが、工程順序を入
れかえて、先にゲート電極線(3)を形威し、次にスト
レージキャパシタの一方の電極(1)を形成しても、上
記実施例と同様のストレージキャパシタを構戊でき、同
様の作用効果を奏する。
In the above embodiment, a method was explained in which the gate electrode line (3) was formed after forming one N tFM (].) of the storage capacitor, but the process order was changed and the gate electrode line (3) was formed first. Even if the electrode wire (3) is formed and then one electrode (1) of the storage capacitor is formed, a storage capacitor similar to that of the above embodiment can be constructed and the same effects can be obtained.

〔発明の効果〕〔Effect of the invention〕

本発明は、以上説明したように構威されているので、以
下の如き効果を奏する。
Since the present invention is structured as described above, it produces the following effects.

ストレージキャパシタの電極は、透明導電膜で構成され
ているので、画素の開口率を低下させることなく、必要
な容量が得られる。
Since the electrode of the storage capacitor is made of a transparent conductive film, the necessary capacitance can be obtained without reducing the aperture ratio of the pixel.

また、ストレージキャパシタ電極は、ゲート電極線やソ
ース電極線と交差しないので、短絡による歩留の低下が
ない。
Furthermore, since the storage capacitor electrode does not intersect with the gate electrode line or the source electrode line, there is no reduction in yield due to short circuits.

【図面の簡単な説明】[Brief explanation of drawings]

第]図は、この発明の一実施例によるTFTアレイ基板
の要部を示す平面図、第2図は第1図のIt−1線断面
図、第3図はその等価回路図、第4図は従来のTFT 
 アレイ基板の要部を示す平面図、第5図は第4図のV
−V線断面図、第6図はその等価回路図、第7図は他の
従来のTFT アレイ基板の要部を示す平面図、第8図
は第7図の■1−■線断面図、第9図はその等価回路図
である。 図中、(1)はストレージキャパシタの一方の電極、(
3)はゲート電極線、(4)は絶縁膜、(5)は半導体
膜、(6)はソース電極線、(7)はドレイン電極、(
8)は画素電極、OQは絶縁性基板である。 なお、図中同一符号は、同一又は相当部分を示す。
1 is a plan view showing the main parts of a TFT array substrate according to an embodiment of the present invention, FIG. 2 is a sectional view taken along line It-1 in FIG. 1, FIG. 3 is an equivalent circuit diagram thereof, and FIG. is a conventional TFT
A plan view showing the main parts of the array substrate, Figure 5 is V in Figure 4.
-V sectional view, FIG. 6 is its equivalent circuit diagram, FIG. 7 is a plan view showing the main parts of another conventional TFT array substrate, FIG. 8 is a sectional view taken along the line ■1-■ in FIG. FIG. 9 is an equivalent circuit diagram thereof. In the figure, (1) is one electrode of the storage capacitor, (
3) is a gate electrode line, (4) is an insulating film, (5) is a semiconductor film, (6) is a source electrode line, (7) is a drain electrode, (
8) is a pixel electrode, and OQ is an insulating substrate. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

【特許請求の範囲】[Claims] 透明の絶縁性基板上に並設された複数のゲート電極線、
このゲート電極線に交差する複数のソース電極線、上記
二つの電極線の交差部に設けられゲートが上記ゲート線
にソースが上記ソース線にそれぞれ接続された薄膜トラ
ンジスタ、及びこの薄膜トランジスタのドレインに接続
された画素電極を有するマトリクス型表示装置において
、上記絶縁性基板上に形成され前段のゲート電極線に接
続された透明導電膜からなる一方の電極、上記画素電極
からなる他方の電極、及び上記一方の電極と他方の電極
との間に形成された絶縁膜からなるストレージキャパシ
タを備えたマトリクス型表示装置。
Multiple gate electrode lines arranged in parallel on a transparent insulating substrate,
A plurality of source electrode lines intersect with the gate electrode line, a thin film transistor provided at the intersection of the two electrode lines and having a gate connected to the gate line and a source connected to the source line, and a thin film transistor connected to the drain of the thin film transistor. In a matrix type display device having pixel electrodes, one electrode is formed on the insulating substrate and is made of a transparent conductive film and connected to the previous gate electrode line; the other electrode is made of the pixel electrode; A matrix display device including a storage capacitor made of an insulating film formed between one electrode and another electrode.
JP1233461A 1989-09-09 1989-09-09 Matrix type display device Pending JPH0396922A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1233461A JPH0396922A (en) 1989-09-09 1989-09-09 Matrix type display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1233461A JPH0396922A (en) 1989-09-09 1989-09-09 Matrix type display device

Publications (1)

Publication Number Publication Date
JPH0396922A true JPH0396922A (en) 1991-04-22

Family

ID=16955396

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1233461A Pending JPH0396922A (en) 1989-09-09 1989-09-09 Matrix type display device

Country Status (1)

Country Link
JP (1) JPH0396922A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5835168A (en) * 1992-04-10 1998-11-10 Matsushita Electric Industrial, Co., Ltd. Active matrix liquid crystal having capacitance electrodes connected to pixel electrodes

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5835168A (en) * 1992-04-10 1998-11-10 Matsushita Electric Industrial, Co., Ltd. Active matrix liquid crystal having capacitance electrodes connected to pixel electrodes

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