JPH0396281A - Manufacture of conductivity-modulation mosfet - Google Patents

Abstract

PURPOSE:To reduce an irregularity in a characteristic caused by a crystal defect density and to eliminate instability of an electric characteristic after a lifetime has been controlled by a method wherein impurities are introduced into a semiconductor substrate of a first conductivity type and a first region of the first conductivity type and a second region of a second conductivity type are formed. CONSTITUTION:An n-type silicon substrate which has been cut from a single crystal manufactured by a floating zone method is used, boron is diffused from the rear to form a P<+> layer to be used as a collector region 1. A remaining part of the substrate is used as an n<-> drift region 2. When a heavy metal is diffused and an electron beam is then irradiated, an expected lifetime is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a conductivity modulated MOSFET used as a power switching element. (Prior art) In recent years, conductivity modulated MO has been used as a power switching element.
SFETs have been proposed and are beginning to appear on the market. Since the conductivity modulation type MOSFET is also called an insulated gate type bipolar transistor, it will be abbreviated as rGBT below. Second
The figure shows the structure of rGBT, and p'' which is the collector region.
A high-resistance n-drift region 2 is layered on top of a Go board 1. A plurality of p-type channel diffusion regions (base regions) 3 are formed in the surface layer of the drift region 2, and a low-resistance p3 well 4 is provided in the center thereof. base area 3
A pair of N9 emifter regions 5 are formed with an interval between them on the surface layer. Drift region 2 of channel diffusion region 3
In order to form an n-channel in the surface layer 31 sandwiched between the ivy region 5 and the ivy region 5, gate oxidation is performed! A gate electrode 7 is provided which is connected to the gate terminal G via I6. An emitter electrode 9 is provided which contacts the p0 well 4 and the emitter region 5 via the gate electrode 7 and the insulating layer 8.
A conductive wire 1l for connection to the emitter terminal E is fixed to the vine electrode 9 by, for example, M wire bonding. Further, a collector electrode 10 connected to a collector terminal C is in contact with the collector region l. This structure is a power MOSFET called normal vertical DMOS.
It can be said that the n''' region as the collector contact layer of ET is replaced with the p0 layer l. The operation of this device is as follows. Apply positive voltage to 8i10, M
Using the same principle as an OSFET, the surface of the p-layer 3 under the electrode is inverted to create an electron channel. Therefore, the n'' base region is connected to the ground potential, and a hole current is injected from the drain electrode 10. This hole current increases the electron concentration in the n- drift region 2 and increases the resistance of this region. Due to the so-called conductivity modulation effect, the on-resistance has a sufficiently low value.As shown in Fig. 3, the ivy current IE flows through the channel!Trout@3 and the n- drain region 2. The hole current flowing into p base region 3 is the sum of p base region 3 + n- PNP formed by drift region 2 and p0 collector region 1
What is the current amplification factor of bipolar transistor αFIIP and 1-αPIIIP? Ra, ■, one! workman. It becomes 3. Therefore, Ib (hole current) changes depending on the value of αP1, that is, the current of IGET changes. Figure 4 shows a typical switching waveform at turn-off, and the first It can be seen that there is a phase 41 and a second phase 42. In the first period 41, the channel disappears and the electron current becomes 0, so the current instantly decreases by that amount. In period 42, the carriers remaining in the n layer 2 cause PN
The current that flows due to the action of the P bipolar transistor decreases with the lifetime τ of the carriers. Therefore, it can be seen that this switching characteristic is also greatly influenced by the injection level of the 1-hole current, that is, by the current amplification factor αp. [Problem to be solved by the invention] In manufacturing conventional IGETs, a first conductivity type is formed by an epitaxial method on a substrate of a second conductivity type obtained from a silicon crystal produced by the Chickralski method (CZ method). A high-resistance layer of the first conductivity type, which becomes the drift l-IN region, is laminated via a low-resistance layer of the first conductivity type. However, according to the Dislocations were observed, indicating the presence of a high density of crystal defects. Such defects greatly affect the injection efficiency of bipolar transistors in IGBTs. Therefore, the current amplification factor of the bipolar transistor, which influences the characteristics of the IGBT, is greatly influenced by the crystal defect density. This crystal defect density does not decrease in subsequent processes, and in particular, the switching speed and forward voltage drop of IGBTs vary greatly, resulting in performance deterioration. This results in a decrease in yield. Crystal defects that occur at the joint surface of an ebitaxial long layer are caused by oxygen precipitates present in the substrate. Therefore, the characteristics of the IGBT change depending on the oxygen concentration in the substrate. Figure 5 is p
“This shows the relationship between the oxygen concentration in the substrate and the turn-off time of IGBT.On the other hand, in order to speed up IGBT, lifetime control is performed by electron beam irradiation or heavy metal diffusion.However, these There is the following problem. In a crystal subjected to electron beam irradiation, the crystal anneal effect progresses at a relatively low temperature of 200 to 300 degrees Celsius, and its electrical properties fluctuate. This instability is caused by excessive Significant problems arise when the power loss within the chip occurs unevenly during electrical stress, i.e., there is a possibility of local variations in electrical characteristics during long-term use. Lifetime control by irradiation is possible because immediately after electron beam irradiation, the threshold voltage decreases due to the capture of hole and electron carriers generated in the oxide film. One ring is required.
The anneal ring, which restores the oxidation center and interface to normal conditions, naturally also restores defects caused by electron beam irradiation in the s+ crystal. In addition, when the irradiation dose is increased to speed up the switching speed, it is observed that the resistance of the high-resistance layer decreases. In other words, there is a limit to increasing the switching speed of IGBTs. In the case of lifetime control using heavy metal diffusion, there is a problem in that the heavy metals are gen- terisolated to the above-mentioned crystal defects, making it impossible to obtain the originally required uniform distribution in the high-resistance layer. In addition, although there is no instability at low temperatures in the heavy metal lifetime control method, when a large amount of impurities is introduced, for example, in an n-high resistance layer, the free electron carrier density is reduced due to the capture of donors in deep levels, resulting in a high resistance phenomenon occurs. This increases the forward voltage drop of the IGBT. An object of the present invention is to provide an IGBT in which variations in characteristics caused by crystal defect density are reduced. Another object of the present invention is to provide an IGBT with no instability in electrical characteristics after lifetime control. (Means for solving !II!I) In order to achieve the above object, the present invention provides a first conductivity type.
A second region of the second conductivity type is adjacent to one surface of the first region, a third region of the second conductivity type is adjacent to the surface of the other surface of the first region, and a third region of the second conductivity type is adjacent to the surface of the third N region. A conductivity-variable beak type having a gate via an insulating film on a region sandwiched between the first region and the fourth region of the third region of a semiconductor body in which a fourth region of one conductivity type is formed. In the method for manufacturing a MOSFET, both the first and second regions are formed by diffusing impurities into a semiconductor substrate of a first conductivity type. In addition, in the above manufacturing method, a polymeric element is first introduced into the semiconductor element,
Next, the desired lifetime of the semiconductor element is obtained by irradiating it with an electron beam. [Operation] When forming the first region of the first conductivity type and the second region of the second conductivity type by introducing impurities into the semiconductor substrate of the first conductivity type, crystal defects existing in the substrate are Since the density is significantly reduced, <I
No variations in GBT characteristics occur. On the other hand, heavy metals are introduced so that the intended lifetime of the semiconductor element remains at the impurity density before the resistance value of the high-resistance layer increases significantly, and the shortfall in lifetime reduction is further compensated for by electron beam irradiation. By doing so, the amount of electron beam irradiation can be reduced, and the amount of variation in electrical characteristics due to low-temperature annealing can be significantly reduced. [Embodiment] Figure 1 shows an intermediate stage of the process of an embodiment of the present invention, and the right side is a cross-sectional view of a semiconductor element. The left side is an impurity concentration distribution map. Such semiconductor bodies can be manufactured using the floating zone method (
Using an n-type silicon substrate with an impurity concentration of IXIO''/1 or less cut out from a single crystal produced by FZ method), boron is diffused from the back surface to form the collector M region 1 shown in Fig. 2.
・Form a layer. The remaining board part becomes the drift SJ area 2. The subsequent steps are the same as the conventional ones, and the p base region 3. shown in FIG. 2 is formed by impurity diffusion. A p well 4 and an n'' emitter region 5 are formed. In the embodiment shown in FIG. 6, which is similar to FIG. A low-resistance n-layer 11 is formed as a seven-head buffer region interposed between the layers.In these structures, the crystal defect density is significantly lower than that of a semiconductor element formed by epitaxial growth on a conventional p9 substrate. The low crystal defect density is not limited to the case where a crystal produced by the FZ method is used, but also when a crystal produced by the neutron irradiation FZ method, a crystal produced by the magnetic field pulling method (MCZ method), or a crystal produced by the cz method is used. can also be obtained.In addition,
Needless to say, ion implantation can also be applied to introduce impurities. In the lifetime control method according to the present invention, a two-stage lifetime IIIm is performed. Figure 7 shows the lifetime and collector-emitter saturation voltage (V Cl
tgal1). In the first heavy metal diffusion, V C! 1111%), that is, to lower the diffusion temperature so that the forward voltage drop remains before it increases rapidly, to suppress the amount of introduced impurity density, and then to obtain a fast switching speed, the lifetime reduction is insufficient. Perform the necessary electron beam irradiation. For example, after heavy metal diffusion at 860°C, 2 MaV. 5 Mrad electron beam irradiation reduces the forward voltage drop by 0.5 μ without increasing the forward voltage drop.
With a relatively small electron beam irradiation dose of less than *5 Mrad, which achieved a turn-off time of 1.2 sec, the amount of variation in electrical characteristics due to low-temperature annealing can be significantly reduced. Figure 8 shows an element subjected to heavy metal lifetime control (line 81) and an element subjected to two-stage lifetime control based on the present invention (line 82).
The relationship between forward voltage drop and turn-off time is shown, and it can be seen that the two-stage lifetime control method improves the trade-off between switching speed and forward voltage drop. This is thought to be due to the suppression of the high resistance phenomenon during heavy metal lifetime control by combining heavy metal and electron beam lifetime control. Furthermore, faster switching speeds can be achieved than with electron beam irradiation alone. Figure 9 shows the conventional IGBT (Figure a) and the F
The variation in turn-off time with the GBT (Figure b) manufactured by forming the p″ head area, n buffer area, and n″81 area by Z method diffusion into the silicon substrate and implementing the two-step lifetime control method was investigated. This is shown in the histogram. It can be seen that the present invention reduces the variation in characteristics. It was also demonstrated that variations in electrical characteristics such as forward voltage drop can be reduced as well. Furthermore, by modifying the shape of the collector region using the diffusion method, the diffusion profile of the collector region can be easily changed, so the turn-off time can be significantly reduced as shown in FIG. Figure 10+al is IGB by conventional method
T, and FIGS.
It is GBT. [Effects of the Invention] According to the present invention, the collector region and drift region of an IGBT are shaped by impurity diffusion into a semiconductor substrate. This eliminates the occurrence of crystal defects at the junctions between regions, which is the case with conventional epitaxial long-teeth formation, and prevents variations in properties due to the effects of crystal defects. In addition, by performing lifetime control in two stages: heavy metal introduction and electron beam irradiation, it is possible to improve the trade-off between switching speed and forward voltage drop during heavy metal lifetime control, increasing the speed of IGBT. became easy.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view and impurity concentration distribution diagram of a semiconductor element at an intermediate stage of the process according to an embodiment of the present invention, and FIG. 2 is an I
A cross-sectional view showing the basic structure of a GBT, Figure 3 is an IGBT.
Figure 4 is a cross-sectional view showing a certain amount of current in IG and an equivalent circuit.
Collector current waveform diagram at turn-off of BT, Figure 5 is p
FIG. 6 is a diagram showing the relationship between the oxygen concentration in the silicon substrate and the turn-off time of the IGBT. FIG. is a relationship diagram between heavy metal diffusion temperature, turn-off time and forward voltage drop for lifetime control,
FIG. 8 is a diagram showing the relationship between forward voltage drop and turn-off time in the IGBT according to the conventional method and the IGBT according to the embodiment of the present invention, and FIG. A histogram showing the distribution of turn-off times of IGBTs, FIG.
．． (I according to the conventional method and the embodiment of the present invention according to bl.
FIG. 3 is a waveform diagram showing the turn-off of GBT. 1! p0 collector region, 2: n- drift region, 3!
p base region, 5: n0 engineering ξ sota region, 6: C Fig. 3 Fig. 4 p1 Regular scale in the substrate (OLd ASTM Scale) Fig. 7 Fig. 8 (a) Fig. 9 (b)

Claims (1)

[Claims] 1) A second region of the second conductivity type is adjacent to one surface side of the first region of the first conductivity type, and a third region of the second conductivity type is adjacent to the surface portion of the other surface side of the first region. An insulating film is formed on a region sandwiched between the first region and the fourth region of the semiconductor body, in which the region further includes a fourth region of the first conductivity type formed on the surface of the third region. A method for manufacturing a conductivity modulated MOSFET having a gate via a conductivity modulated MOSFET, characterized in that both the first and second regions are formed by introducing impurities into a semiconductor substrate of a first conductivity type. Method of manufacturing MOSFET. 2) A second region of the second conductivity type is adjacent to one side of the first region of the first conductivity type, a third region of the second conductivity type is adjacent to the surface portion of the other side of the first region, and a third region of the second conductivity type is adjacent to one side of the first region of the first conductivity type. A gate is provided on a region sandwiched between the first region and the fourth region of the third region of the semiconductor body in which the fourth region of the first conductivity type is formed on the surface of the region, with an insulating film interposed therebetween. In the method for manufacturing a conductivity modulated MOSFET, the semiconductor element is first introduced with a heavy metal and then irradiated with an electron beam to obtain the desired lifetime of the semiconductor element.
Method for manufacturing T.