JPH0395797A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce the number of MOS transistors and to constitute a word decoder with a small area by obtaining specified connection constitution for the p-channel and n-channel MOS transistors of a word decoder circuit to select a word line. CONSTITUTION:A semiconductor integrated circuit device is composed of two p-channel MOS transistors Q1, Q2...Q7 and Q8, to which word decoder circuits D1-D4 are serially connected, and one n-channel MOS transistors Q9-Q12 and first and second address signal lines are inputted to the gates of the two p- channel MOS transistors Q1, Q2...Q7 and Q8. The gates of the n-channel MOS transistors Q9-Q12 pull out the electric charge of the word line by the driving of a pulse and the electric charge is connected with word lines W1-W4 by reference electricity, for example, connected with the set electricity by the resistors of 10K-10GOMEGA in the interval to a GND. Thus, without damaging the normal operation of a static RAM, the word decoders D1-D4 to widely occupy the area of a chip can be designed in the small area and accordingly, the chip area can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for designing a small-area decoder circuit in a semiconductor memory device, particularly a word decoder circuit for selecting a word line.

[Conventional technology]

The conventional word decoder circuit is the 1988 Symposi
um of VLSI Circuits pp. 4
．． A single stage NOR gate as described in 5-46. Alternatively, it was constructed with an AND gate as described in Japanese Patent Application Laid-Open No. 59-72699.

[Problem to be solved by the invention]

As semiconductor memory devices become more highly integrated and larger in capacity, the memory array is divided into multiple subarrays, which increases the number of word decoders used to select word lines, making it increasingly necessary to reduce the word decoder area. Channel and n-channel Most ~ transistors require 4 to 6 elements,
The word decoder area cannot be sufficiently reduced.

An object of the present invention is to provide a MoS that constitutes a word decoder circuit.
The purpose is to reduce the number of transistors and construct a word decoder with a small area.

[Means to solve the problem]

In order to achieve the above object, the word decoder circuit is constructed of two p-channel MOS transistors and an n-channel MOS transistor connected in series, and the gates of the two p-channel MOS transistors are connected to the first and second p-channel MOS transistors. 2 address signal line is input, n-channel MOS
The gate of the h transistor draws out the word line charge by pulse driving, and connects the word line and base +1! A resistive element of 10 KΩ to 10 GΩ to IOGΩ is connected to a potential (for example, ground potential GND).

[Effect]

When the first and second address signal lines input to the gates of two cascade-connected p-channel MOSh transistors are both set to GND potential, the word line is charged to Vcc potential, and the {th and After at least one address signal line among the two address signal lines has finished reading memory cell information due to pulse drive, V C CfX
After that, the power supply to all word lines is stopped, and then the input voltage to the gates of the n-channel Mos+ transistors is set to the ■cc potential, and the n-channel MOS transistors are made conductive, so that the power supply to all word lines is at the VccYd level.
1 The charge of one line is drawn and the word line that is not separated by 1 is aND=
After the input signal of the n-channel MOS transistor is set to the GND potential, the word line is again supplied with power when the two p-channel MOS transistors are turned on, and the two p-channel MOS transistors connected in series are Connect a resistance element that is sufficiently higher than the ON resistance of the transistor to the lead wire and GN.
By maintaining the non-selected word line %GND potential by connecting it to D, normal memory cell selection operation in static RAM becomes possible, and the word decoder can be designed with a small area.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 and 2. In FIG. 1, MW is a main word line and is selected by the output of a mouth decoder (not shown). D
i, D2, D3, and D4 are word decoders for selecting word lines W1 to W4, and each includes two p-channel MOS transistors Ql, QZ and one n-channel MOS transistor Q9, Q3 . Q4 and Qto.
It is composed of Q5rQ6 and Q11, and (h, Qa and Q12. Wl, W2, W3, W4 are word lines selected by word decoders D'l, D2, D3, D4, respectively. Bit line, MCI, MC2, MC3
, MC4 represent static type memory cells. φ is n-channel MOS transistor Q9-0 of each word decoder
The signals a1, a1a3, and a4 controlling the word decoders 12 and 12 are predecode signals of address signals, and one p-channel MOS transistor Q2, Q4, and
Input to the gates of Qs and Qδ.

FIG. 2 is an example of operational waveforms for explaining the operation of the embodiment shown in FIG. When the address input signal changes, the address signal transition detection circuit (ATD circuit) generates an ATD pulse with a predetermined pulse width, and by controlling the X decoder with this pulse, the GN selected by the X decoder is
One main word line that is at the D potential is set at the Vcc potential after memory cell information read from a predetermined memory cell is stored in the latch circuit 12 shown in FIG. Buri decode signals at, a2, a3 . For a4, after the address input signal changes, the potentials of at and a2 are switched, and a3 and a4 maintain the Vcc potential. The signal φ is generated from the ATD pulse, and the main word line potential is G N in the previous cycle.
After reaching the 771st position, the potential is set to Vcc and the n-channel MOS}-transistor Q s * Q r a +
Q tr , Q12 are made conductive, word lines Wl, W2
, W3. Set W4 to GND potential. Next, before the main word line is selected and becomes the GNDTi level, the signal φ goes to GND.
potential, and Qet Qto and Qllll Q12 are all rendered non-conductive. After that, a1 becomes GND potential, a
2 is set to the Vcal level, and subsequently or simultaneously, the main word line MW is set to the GND potential, so that Qt and Qz become conductive in the word decoder D1, and the word line W1
is charged to about Vccfa. At this time, the resistor R is connected to the p-channel MOS transistor Ql. By setting a value sufficiently large compared to the ON resistance of Q2, W1 is approximately equal to Vc.
Cl position can be maintained.

Since the On resistance of Ql and Q2 is usually less than 10KΩ,
The value of R is more preferably about IMΩ to IOMΩ than 10KΩ to 10GΩ to IOMΩ. Regarding D2, D3, and D4, since a2+ a3, a↓ becomes the Vcc potential, Q4, Qes Qa becomes non-conductive, and the word lines W2,
W3 and W4 are fixed to GND potential by a resistor R. The resistance R is. By forming polycrystalline polysilicon on the MOS transistor, the layout area does not need to be increased.

next. Information of the memory cell MCI selected by the word line W1, which has reached the Vcc potential, is read out to the bit lines b, b, and reaches the sense amplifier l1 via the Y decoder 10. The sense amplifier 11 is activated by the activation signal SA and amplifies the memory cell information, and this amplification a reaches the output buffer 13 via the data path, and the information is stored in the latch circuit 12. After the information is stored in the latch circuit 12, the sense amplifier activation signal SA is set to the GND potential to inactivate the sense amplifier 11, and the main word line potential is set to the Vcc potential, and the p-channel MOS transistors Qt, Q3 . Ql1I Q7 is made non-conductive. That is, word line W1 is no longer powered to Vcc'R. Subsequently, φ is set to the vcc potential, and the m-channel MOS transistor Q 9 1Qto+ Q1t
+ Q12 is made conductive and the potential of word vAll is GN
It becomes D potential. After the word line becomes GND potential at terminal 8 and the sense amplifier l1 becomes inactive, the latch circuit l2
The output buffer 13 is activated based on the information stored in the output buffer 13, and the output is maintained.

Thus, according to the embodiment of FIG.
It can be constructed from a channel MOSH transistor and one n-channel MOS transistor, and a word decoder can be constructed with an extremely small area.

3 and 4 are examples of conventional word decoder circuits. In the conventional circuit shown in Fig. 3, the word decoder consists of two p
Channel MOS transistor and two n-channel MOS
The conventional circuit shown in FIG. 4 consists of three p-channel MOS transistors and three n-channel MOS transistors.
In either case, the word decoder area cannot be sufficiently reduced.

FIG. 5 shows another embodiment of the present invention, in which a p-channel MOS transistor and an n-channel MOS transistor are used in the embodiment of FIG.
The structure is such that the roles of the OS transistors are swapped and one stage of inverter is added, and the inverter input terminal and Vc
A resistive element is connected between C and C to maintain the potential of the unselected word line. This embodiment also allows normal operation of the status RAM in the same manner as the embodiment shown in FIG. 1, and the area of the word decoder can be made smaller than that in the embodiment shown in FIG.

〔Effect of the invention〕

According to the present invention, the word decoder, which occupies a large proportion of the chip area, can be designed in a small area without impairing the normal operation of the static RAM, which has the effect of reducing the chip area and lowering the chip cost. .

[Brief explanation of drawings]

Fig. 2 is an operation waveform diagram explaining the operation of the embodiment of Fig. 1, Fig. 3 and Fig. 4 are conventional circuit examples, and Fig. 5 is an example of the present invention. This is another example. D1-D4...word decoder, MCI-MC4...
・Memory cell, MW ・Main word line, W1 to W4・
・Word line, R...resistance element, a1 to a4...bridecode signal, φ...pulse signal for extracting word line charge, b, 5...bit line, SA...sense amplifier Laughing 2nd map 3 To country 04α3α2, whisper 4 Q<'(Axrα

Claims (1)

[Claims] In a semiconductor memory device in which memory cells storing one or two-value information are arranged two-dimensionally, a memory cell is selected by a word line and a bit line, and information in the memory cell is read out. , the word decoder circuit for selecting the word line is comprised of: (1) a first field effect transistor of the first conductivity type whose source is connected to a first power supply voltage and whose gate is connected to a first address signal line; (2) a second field effect transistor of the first conductivity type, the source of which is connected to the drain of the first field effect transistor of the first conductivity type, and the gate of which is connected to the second address signal line; (3) the source of the field effect transistor of the first conductivity type; a third second conductivity type field effect transistor having a gate connected to a second power supply voltage, a gate connected to a third signal line, and a drain connected to the second first conductivity type field effect transistor. , connecting the drain of the second field effect transistor of the first conductivity type and the drain of the third field effect transistor of the second conductivity type to the word line; (4) the first and second addresses; By driving at least one address signal line among the signal lines, information is read from the memory cell, and after the read memory cell information is stored in the latch circuit, the first and second first conductivity types are (5) changing the at least one address signal line to a potential such that at least one of the field effect transistors becomes non-conductive;
(6) changing the potential of the word line by the first and second address signal lines to make the third field effect transistor of the second conductivity type conductive; Before the potential changes to a potential that selects a memory cell, the potential of the third signal line is changed to a potential that makes the third field effect transistor of the second conductivity type non-conductive; (7) A first terminal is connected between the word line and the second power supply terminal.
(8) The resistance value of the first resistance element is 10KΩ to 10G.
A semiconductor integrated circuit device characterized by being in the range of Ω. 2. In the semiconductor integrated circuit device according to claim 1,
An inverter including a fourth field effect transistor of the first conductivity type and a fifth field effect transistor of the second conductivity type is provided between the word line and the drain of the third field effect transistor of the second conductivity type. and connecting the word line and the first power supply voltage terminal with a second resistance element,
A semiconductor integrated circuit device, wherein the second resistance element has a resistance value in a range of 10KΩ to 10GΩ.