JPH039528A - Hetero junction bipolar transistor - Google Patents

Abstract

PURPOSE:To eliminate emitter resistance component due to the low concentration dope limit, by setting the thickness of a III-V compound layer having forbidden bandwidth larger than semiconductor constituting a base and opposite conductivity type at a specified value, arranging said layer between a base and an emitter, and making the III-V compound semiconductor completely turn to a depletion state. CONSTITUTION:On a semiconductor substrate 1 constituted of group IV single element, the following are formed; a conductivity type collector region constituted of group IV single element, an opposite conductivity type base region 6 formed in the collector region, a conductivity type emitter region formed on the surface of the base region 6, and a group IV single element semiconductor layer which is formed on the emitter region and has impurity concentration larger than that of the emitter region. Said emitter region is constituted of III-V compound whose forbidden bandwidth is larger than that of the group IV single element semiconductor and the thickness is smaller than the width of a depletion layer stretching from the base region 6. By this constitution, the resistance of the emitter part is reduced and characteristics are improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a heterojunction bipolar transistor.

[Conventional technology]

FIG. 2 is a cross-sectional view of an example of a conventional heterojunction bipolar transistor.

A field oxide film 5 is formed using a local oxidation method (LOCO3 method) in which a 01 type layer 4 is formed on a p-type silicon substrate 1 by ion implantation to define an element region. A p-type base region 6 is formed in layer 4. An oxide film 7 is formed on the surface, a phosphorus film 8 is deposited thereon, and a window is formed. And it has a wider forbidden band width than silicon■
For example, an InP layer 9 is deposited as a -V group compound semiconductor. Open the window again and place the aluminum electrode 11 on the silicon layer.
, the InP layer 9 has a Ni/AuGe electrode 1
form 2.

[Problem to be solved by the invention]

In the conventional heterojunction bipolar transistor described above, when a large amount of donor type impurity is added to the 111-V group compound semiconductor crystal used as the emitter material,
The impurity that should occupy the substituted lattice position of the donor type does not necessarily occupy the desired lattice position, but instead occupies the opposite lattice position, and the impurity is approximately two orders of magnitude smaller than that of a homojunction bipolar transistor using silicon as the emitter material. The degree doping limit concentration decreases, the standard doping limit is 1018 cm-3
The concentration is low. As a result, there is a problem in that the resistance of the emitter portion becomes significantly high, leading to deterioration of characteristics and becoming an obstacle to progressing with miniaturization.

[Means to solve the problem]

The heterojunction bipolar transistor of the present invention has an island-shaped collector (or emitter) of one conductivity type made of the parent element, which is formed by rubbing an insulating separation layer on a semiconductor substrate made of the parent element. a base region of opposite conductivity type formed in the collector (or emitter) region, and a base region of an opposite conductivity type formed in the collector (or emitter) region; an emitter (or collector) region of one conductivity type made of a group V compound and having a thickness smaller than the width of a depletion layer extending from the base region; a group IV single-element semiconductor layer having an impurity concentration of 10 times or more and 500 times or less of the impurity concentration of the collector) region.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIGS. 1(a) to 1(e) are cross-sectional views showing the order of steps for explaining a manufacturing method according to an embodiment of the present invention.

First, as shown in FIG. 1(a), a p-type silicon substrate 1
After the entire surface is oxidized, a part of the oxide film is removed and a window is opened, arsenic is diffused using the remaining oxide film as a mask to form an n+ type buried layer 2, and the oxide film used as a mask is removed. do. Impurity concentration on the silicon substrate surface: 1.0 x 101
An n-type layer 3 of 6Cffl-s is epitaxially grown to a thickness of about 1.3 μm. An oxide film 13 and a nitride film 814 are sequentially formed on the n-type layer 3, and the nitride film and oxide film between the device regions and in the region that will become the emitter and collector are etched using photolithography technology. Remove by etching up to the middle.

Next, as shown in FIG. 1(b), a p+ type layer 4 for preventing a channel is formed using an ion implantation method, and annealing is performed to remove crystal defects generated by the ion implantation. After forming the field oxide film 5 by thermal oxidation using the uppermost nitride film 14 as a mask, the nitride wA1 used as a mask is
4. Remove the oxide film 13 and apply a new oxide film. After opening a window by selective etching and diffusing phosphorus into the collector extraction region, an oxide film 7 is provided again. Photoresist 15
Using this as a mask, boron ions are implanted to form p-type base region 6.

Next, as shown in FIG. 1(c), after depositing a phosphorus glass film 8 for passivation, the phosphorus glass film 8 and oxide film 7 in the region where the emitter will be formed are selectively removed using photolithography technology. . This opening has an impurity concentration of about 1,
About 8 nm of n-type InP19 of OX 1018 cm-'
Deposited to a thickness of . On top of this, impurity concentration is about 2.0XIO
A single-crystal n+ type silicon layer 10 is selectively grown using 2.degree. Cl1l. In particular, in the case of an epitaxial growth system that does not have excellent selectivity, a polycrystalline InP layer and a polycrystalline silicon layer grow on the insulating crotch. In this case, the emitter region is covered with photoresist and the polycrystalline layer is removed by etching.

Next, as shown in FIG. 1(d), a window is formed by selectively removing the insulating film in the collector and base regions using photolithography.

Next, as shown in FIG. 1(e), after aluminum is deposited on the entire surface, aluminum electrodes 11 are formed on the emitter, base, and collector regions using photolithography. Unnecessary Aβ is removed by etching to form the @ pole part.

In this way, the heterojunction bibolar transistor of the present invention is manufactured. Estimating the width of the depletion layer formed at the emitter and base of a transistor with this structure, the relative permittivity of the base is p-type silicon is 11.9. Impurity concentration 3×
1018 cm-3, and this base region 6 and p-n
InP forming the junction has a dielectric constant of 12.4 and an n-type impurity concentration I x 1018 cm-'. Silicon and In
It has almost the same dielectric constant as P, and when the depletion layer between the emitter and paste is shortened by applying a forward bias, the width of the depletion layer extending toward the InP side is approximately 9 when the built-in potential + applied voltage = O, IV.
．． 5 nm, and the InP layer 9 is completely depleted.

In the above embodiment, n-type InP was used as the ■-■ group compound, but it is clear that n-type GaAs may also be used. When using GaAs, the impurity concentration is 2 x 1
018 cm-' and the thickness is 5 nm.

The difference in electron affinity between GaAs and silicon is 20 mV and I
The difference in electron affinity between nP and silicon is less than 350 mV, and the base voltage value for the same collector current differs little from that of a silicon homojunction bipolar transformer, which has the advantage of being easy to apply to current circuit configurations.

〔Effect of the invention〕

As explained above, the present invention provides an IV group compound layer having a forbidden band width wider than that of the semiconductor constituting the base of a bipolar transistor and having reverse conductivity and having a thickness of 10r++++ or less and disposing it between the base and emitter. ■-By completely depleting the V group compound semiconductor, the upper limit of doping is lower than that of silicon crystal, and the limit value is 1018 cm-'
There is an effect that the emitter resistance component generated due to the low concentration of the base can be eliminated.

[Brief explanation of the drawing]

FIGS. 1(a) to (e) are cross-sectional views showing the manufacturing method of an embodiment of the present invention in the order of steps, and FIG. 2 is a cross-sectional view of an example of a conventional heterojunction bipolar transistor. be. 1...p-type silicon substrate, 2...n+ type buried layer, 3
... n-type layer, 4 ... p + type layer, 5 ... field oxide film, 6 ... p-type base region, 7 ... oxide film, 8
...phosphorus glass film, 9... n-type InP layer, 10...
・n+ type silicon layer, 11...aluminum electrode, 1
2...Ni/AuGe electrode, 13...Oxide film, 14
...Nitride film, 15...Photoresist.

Claims (1)

[Claims] An island-shaped collector (or emitter) region of one conductivity type made of a group IV single element formed on a semiconductor substrate made of a group IV single element surrounded by an insulating separation layer, and a collector (or emitter) region of one conductivity type formed within the collector (or emitter) region. a base region of opposite conductivity type, and a group III-V compound formed on a part of the surface of the base region and having a wider forbidden band width than the group IV single-element semiconductor,
and an emitter (or collector) of one conductivity type having a thickness smaller than the width of a depletion layer extending from the base region.
and a group IV single-element semiconductor layer formed on the emitter (or collector) region and having an impurity concentration of 10 times or more and 500 times or less than the impurity concentration of the emitter (or collector) region. Heterojunction bipolar transistor.