JPH039502U - - Google Patents

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Publication number
JPH039502U
JPH039502U JP6853189U JP6853189U JPH039502U JP H039502 U JPH039502 U JP H039502U JP 6853189 U JP6853189 U JP 6853189U JP 6853189 U JP6853189 U JP 6853189U JP H039502 U JPH039502 U JP H039502U
Authority
JP
Japan
Prior art keywords
electrodes
electrode
main surface
stage
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6853189U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP6853189U priority Critical patent/JPH039502U/ja
Publication of JPH039502U publication Critical patent/JPH039502U/ja
Pending legal-status Critical Current

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  • Control Of Motors That Do Not Use Commutators (AREA)
  • Waveguides (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図ないし第3図は本願第1項の考案の一実
施例によるトリプレート型ストリツプラインフイ
ルタを説明するための図であり、第1図はその分
解斜視図、第2図はその底面図、第3図は第2図
の−線断面図、第4図は本願第2項の考案の
一実施例を説明するための分解斜視図、第5図a
及び第5図bはそれぞれ従来のトリプレート型ス
トリツプラインフイルタを示す平面図、分解斜視
図である。 図において、1はトリプレート型ストリツプラ
インフイルタ、2は誘電体基板、3はアース電極
、4は共振電極、4a,4bは初段及び最終段の
共振電極、6は入、出力電極、7はスルーホール
電極、10はストリツプラインフイルタ、11は
セラミツクス基板である。
1 to 3 are diagrams for explaining a triplate type stripline filter according to an embodiment of the invention of item 1 of the present application, FIG. 1 is an exploded perspective view thereof, and FIG. 2 is a bottom view thereof. Figure 3 is a cross-sectional view taken along the - line in Figure 2, Figure 4 is an exploded perspective view for explaining an embodiment of the invention of Section 2 of the present application, and Figure 5a.
and FIG. 5b are a plan view and an exploded perspective view, respectively, showing a conventional triplate type stripline filter. In the figure, 1 is a triplate type stripline filter, 2 is a dielectric substrate, 3 is a ground electrode, 4 is a resonant electrode, 4a and 4b are first and final stage resonant electrodes, 6 is an input and output electrode, and 7 is a Through-hole electrodes, 10 are stripline filters, and 11 are ceramic substrates.

Claims (1)

【実用新案登録請求の範囲】 (1) 誘電体基板の一主面にアース電極を形成し
、他主面に所定間隔をあけて複数の共振電極を形
成するとともに、初段及び最終段の上記共振電極
に入、出力部を形成してなるストリツプラインフ
イルタにおいて、上記誘電体基板の上記初段及び
最終段の共振電極部分にスルーホール電極を形成
し、該誘電体基板の一主面の上記スルーホール電
極の周縁に上記アース電極との間にギヤツプを設
けて入、出力電極を形成し、該入、出力電極と上
記初段及び最終段の共振電極とを上記スルーホー
ル電極により接続し、上記誘電体基板の入、出力
電極をプリント基板上の回路配線に接続したこと
を特徴とするストリツプラインフイルタ。 (2) 誘電体基板の一主面にアース電極を形成し
、他主面に所定間隔をあけて複数の共振電極を形
成するとともに、初段及び最終段の上記共振電極
に入、出力部を形成してなるストリツプラインフ
イルタにおいて、上記誘電体基板の他主面側に低
誘電率からなるセラミツクス基板の一主面を対向
当接させ、該セラミツクス基板の上記初段及び最
終段の共振電極を臨む部分にスルーホール電極を
形成し、上記セラミツクス基板の他主面のスルー
ホール電極の周縁に入、出力電極を形成するとと
もに、該入、出力電極と上記初段及び最終段の共
振電極とを上記スルーホール電極により接続し、
上記セラミツクス基板の入、出力電極をプリント
基板上の回路配線に接続したことを特徴とするス
トリツプラインフイルタ。
[Claims for Utility Model Registration] (1) A ground electrode is formed on one main surface of a dielectric substrate, a plurality of resonant electrodes are formed at predetermined intervals on the other main surface, and In a stripline filter in which an electrode enters and an output part is formed, through-hole electrodes are formed in the first-stage and final-stage resonant electrode portions of the dielectric substrate, and the through-hole electrodes are formed in the first-stage and final-stage resonant electrode portions of the dielectric substrate, and A gap is provided between the hole electrode and the ground electrode to form input and output electrodes, and the input and output electrodes are connected to the first and final stage resonance electrodes by the through-hole electrode, and the dielectric A stripline filter characterized in that input and output electrodes of a body board are connected to circuit wiring on a printed circuit board. (2) A ground electrode is formed on one main surface of the dielectric substrate, and a plurality of resonant electrodes are formed at predetermined intervals on the other main surface, and the resonant electrodes enter the first and final stages to form an output section. In the stripline filter, one main surface of a ceramic substrate made of a low dielectric constant is brought into opposing contact with the other main surface side of the dielectric substrate, and the resonant electrodes of the first and final stages of the ceramic substrate are faced. A through-hole electrode is formed in the ceramic substrate, and an output electrode is formed by entering the periphery of the through-hole electrode on the other main surface of the ceramic substrate, and the input and output electrodes and the first-stage and final-stage resonance electrodes are connected through the through-hole electrode. Connected by hole electrode,
A stripline filter characterized in that the input and output electrodes of the ceramic substrate are connected to circuit wiring on a printed circuit board.
JP6853189U 1989-06-12 1989-06-12 Pending JPH039502U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6853189U JPH039502U (en) 1989-06-12 1989-06-12

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6853189U JPH039502U (en) 1989-06-12 1989-06-12

Publications (1)

Publication Number Publication Date
JPH039502U true JPH039502U (en) 1991-01-29

Family

ID=31603047

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6853189U Pending JPH039502U (en) 1989-06-12 1989-06-12

Country Status (1)

Country Link
JP (1) JPH039502U (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008311688A (en) * 2006-02-28 2008-12-25 Tdk Corp Chip antenna
JP4513082B2 (en) * 2000-03-15 2010-07-28 パナソニック株式会社 Laminated electronic parts, laminated duplexers, communication equipment, and high frequency radio equipment
WO2014002764A1 (en) * 2012-06-29 2014-01-03 株式会社村田製作所 Laminated flat cable and manufacturing method therefor

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5951606A (en) * 1982-09-17 1984-03-26 Murata Mfg Co Ltd Distributed constant filter
JPH01106464A (en) * 1987-09-24 1989-04-24 Mitel Corp Latchup and electrostatic discharge protection structure

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5951606A (en) * 1982-09-17 1984-03-26 Murata Mfg Co Ltd Distributed constant filter
JPH01106464A (en) * 1987-09-24 1989-04-24 Mitel Corp Latchup and electrostatic discharge protection structure

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4513082B2 (en) * 2000-03-15 2010-07-28 パナソニック株式会社 Laminated electronic parts, laminated duplexers, communication equipment, and high frequency radio equipment
JP2008311688A (en) * 2006-02-28 2008-12-25 Tdk Corp Chip antenna
WO2014002764A1 (en) * 2012-06-29 2014-01-03 株式会社村田製作所 Laminated flat cable and manufacturing method therefor
JPWO2014002764A1 (en) * 2012-06-29 2016-05-30 株式会社村田製作所 Manufacturing method of high-frequency signal line
US9673501B2 (en) 2012-06-29 2017-06-06 Murata Manufacturing Co., Ltd. Laminated flat cable and method for producing same

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