JPH0394666U - - Google Patents
Info
- Publication number
- JPH0394666U JPH0394666U JP15171689U JP15171689U JPH0394666U JP H0394666 U JPH0394666 U JP H0394666U JP 15171689 U JP15171689 U JP 15171689U JP 15171689 U JP15171689 U JP 15171689U JP H0394666 U JPH0394666 U JP H0394666U
- Authority
- JP
- Japan
- Prior art keywords
- slice level
- input signal
- comparator
- setting circuit
- level setting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 6
Landscapes
- Signal Processing For Digital Recording And Reproducing (AREA)
Description
第１図は本考案の一実施例のブロツク図、第２
図は第１図で用いるスライスレベル演算回路の具
体例を示すブロツク図、第３図は第１図の動作を
説明する波形図、第４図は第１図で用いるスライ
スレベル設定回路の他の具体例を示す回路図、第
５図は波形再生動作を説明する波形図、第６図は
従来の装置の一例を示すブロツク図、第７図は従
来の装置の動作波形例図である。
７……入力端子、８……比較器、９……スライ
スレベル設定回路、１０……増幅器。
Figure 1 is a block diagram of one embodiment of the present invention;
The figure is a block diagram showing a specific example of the slice level calculation circuit used in Figure 1, Figure 3 is a waveform diagram explaining the operation of Figure 1, and Figure 4 is another example of the slice level setting circuit used in Figure 1. 5 is a waveform diagram illustrating a waveform reproducing operation, FIG. 6 is a block diagram illustrating an example of a conventional device, and FIG. 7 is a diagram illustrating an example of operating waveforms of the conventional device. 7...Input terminal, 8...Comparator, 9...Slice level setting circuit, 10...Amplifier.
Claims (1)
定するスライスレベル設定回路と、 前記入力信号と該スライスレベル設定回路で設
定されたスライスレベルを比較する比較器と、 該比較器の出力信号を増幅する増幅器とで構成
され、 入力信号のピーク部分を選択的に増幅してパル
ス幅を細くすることを特徴とする波形等化器。[Claims for Utility Model Registration] A slice level setting circuit that detects the amplitude of an input signal and sets a slice level; a comparator that compares the input signal with the slice level set by the slice level setting circuit; A waveform equalizer is comprised of an amplifier that amplifies the output signal of the comparator, and is characterized by selectively amplifying the peak portion of the input signal to narrow the pulse width.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15171689U JPH0394666U (en) | 1989-12-29 | 1989-12-29 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15171689U JPH0394666U (en) | 1989-12-29 | 1989-12-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0394666U true JPH0394666U (en) | 1991-09-26 |
Family
ID=31698004
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15171689U Pending JPH0394666U (en) | 1989-12-29 | 1989-12-29 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0394666U (en) |
-
1989
- 1989-12-29 JP JP15171689U patent/JPH0394666U/ja active Pending
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