JPH0394521A - Multiplex a/d conversion circuit - Google Patents

Multiplex a/d conversion circuit

Info

Publication number
JPH0394521A
JPH0394521A JP23194189A JP23194189A JPH0394521A JP H0394521 A JPH0394521 A JP H0394521A JP 23194189 A JP23194189 A JP 23194189A JP 23194189 A JP23194189 A JP 23194189A JP H0394521 A JPH0394521 A JP H0394521A
Authority
JP
Japan
Prior art keywords
output
converter
sample
logarithmic amplifiers
hold circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23194189A
Other languages
Japanese (ja)
Inventor
Naoko Matsuda
直子 松田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP23194189A priority Critical patent/JPH0394521A/en
Publication of JPH0394521A publication Critical patent/JPH0394521A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To improve the effect of saving of the number of analog circuits proportional to multiplex rate by providing an A/D converter to a data signal, and a gain control signal being gain information of a logarithmic amplifier, respectively. CONSTITUTION:A dynamic range of a signal is corrected by variable gain logarithmic amplifiers 1-1, 1-2-1-n and corrected into a conversion range of an D/A converter of the post-stage. n-Set of output signals of the logarithmic amplifiers 1-1, 1-2-1-n are multiplexed by an analog multiplexer(MUX) 2, and a high frequency component is eliminated by a low pass filter(LPF) 3 for loopback distortion prevention, its output is sampled and held by a sample-and- hold circuit (S/H) 4 and converted and outputted into a digital data through an A/D converter. Then the gain of the logarithmic amplifiers 1-1, 1-2-1-n is required for reproducing the data signal, then the gain control signal for the logarithmic amplifiers 1-1, 1-2-1-n is A/D-converted similarly.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は多重化A−D変換回路に関し、特に複数の入力
信号を多重化する多重化A−D変換回路に関する. 〔従来の技術〕 従来、複数の物理データをA−D変換する場合、それぞ
れの信号が異なるダイナミックレンジやビット精度を持
つために、第2図のような楕戒をとっていた.すなわち
、n個の入力信号を増幅するn個のアンプ11−1〜1
1−nと、その出力に−nと、そのサンプルホールド出
力をデジタル値に変換するA−Dコンバータ14−1〜
14−nの組み合わせと、n個の出力信号を多重化する
マルチプレクサ15からなる。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multiplexed A-D converter circuit, and more particularly to a multiplexed A-D converter circuit that multiplexes a plurality of input signals. [Prior Art] Conventionally, when converting multiple pieces of physical data from analog to digital, an ellipse as shown in Figure 2 has been used because each signal has a different dynamic range and bit precision. That is, n amplifiers 11-1 to 1 that amplify n input signals
1-n, -n for its output, and A-D converters 14-1 to 14-1 for converting the sample and hold output into digital values.
14-n and a multiplexer 15 for multiplexing n output signals.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の多重化A−D変換回路では、個個の入力
信号が異なるダイナミックレンジやビット精度を持つた
め、それぞれ専用のA−D変換器を必要とし回路構戒が
繁雑とな.る欠点がある。また、このようなA−D変換
回路はアナログ部分が回路の大部分を占め、集積技術が
向上し半導体プロセスが微細化してもアナログ部分が縮
小せずコスト低下の妨げとなっていたという欠点がある
In the above-mentioned conventional multiplexed A-D converter circuit, since individual input signals have different dynamic ranges and bit precisions, dedicated A-D converters are required for each, resulting in a complicated circuit structure. There are some drawbacks. Another disadvantage of such A-D converter circuits is that the analog part occupies most of the circuit, and even as integration technology improves and semiconductor processes become smaller, the analog part does not shrink, which hinders cost reduction. be.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の多重化A−D変換回路は、n個の入力アナログ
信号のダイナミックレンジを圧縮補正するn個の対数増
幅器と、前記対数増幅器の出力を多重化する第1のアナ
ログマルチプレクサと、前記第1のアナログマルチプレ
クサの出力の高周波戒分を除く第1のロウパスフィルタ
と、前記ロウパスフィルタの出力データをサンプルホー
ルドする第1のサンプルホールド回路と、前記第1のサ
ンプルホールド回路の出力をデジタル信号に変換する第
1のA−Dコンバータと、前記n個の対数増幅器のゲイ
ン値を表現するn個のゲインコントロール信号を多重化
する第2のアナログマルチプレクサと、前記第2のアナ
ログマルチプレクサの出力から高周波成分を除く第2の
ロウパスフィルタと、この第2のロウパスフィルタの出
力データをサンプルホールドする第2のサンプルホール
ド回路と、前記第2のサンプルホールド回路の出力をデ
ジタル信号に変換する第2のA−Dコンバータとを備え
て構成される。
The multiplexing A-D conversion circuit of the present invention includes: n logarithmic amplifiers that compress and correct the dynamic range of n input analog signals; a first analog multiplexer that multiplexes the outputs of the logarithmic amplifiers; a first low-pass filter that removes high-frequency signals from the output of the analog multiplexer No. 1; a first sample-and-hold circuit that samples and holds the output data of the low-pass filter; and a first sample-and-hold circuit that samples and holds the output data of the first analog multiplexer; a first analog-to-digital converter for converting into a signal; a second analog multiplexer for multiplexing n gain control signals representing gain values of the n logarithmic amplifiers; and an output of the second analog multiplexer. a second low-pass filter that removes high-frequency components from the second low-pass filter; a second sample-and-hold circuit that samples and holds the output data of the second low-pass filter; and a second sample-and-hold circuit that converts the output of the second sample-and-hold circuit into a digital signal. and a second AD converter.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する. 第1図は本発明の一実施例の楕戒図である。n個の入力
信号である入力1,入力2・・・入力nは、ゲイン可変
の対数増幅器1−1.1−2〜1−nによりダイナミッ
クレンジを補正され、後段のA一Dコンバータの変換範
囲内の信号に修正される.対数増幅器1−1〜1−nの
n個の出力信号はアナログマルチブレクサ(MtJX>
2で多重化され、さらに、折り返しひずみ防止のためロ
ウパスフィルタ(LPF)3により高周波成分を取り除
かれ、その出力はサンプルホールド回路(S/H)4に
よりサンプルホールドされ、A−Dコンバータを通って
デジタルデータに変換され出力される.ここで、対数増
幅器1−1〜1−nのゲイン値はデータ信号の再現のた
め必要となるので、対数増幅器1−1〜1−nのゲイン
コントロール信号も同様にA−D変換する。
Next, the present invention will be explained with reference to the drawings. FIG. 1 is an elliptical diagram of an embodiment of the present invention. Input 1, input 2, etc., which are n input signals, have their dynamic ranges corrected by variable gain logarithmic amplifiers 1-1, 1-2 to 1-n, and are converted by the A-D converter in the subsequent stage. The signal is corrected to within the range. The n output signals of the logarithmic amplifiers 1-1 to 1-n are connected to an analog multiplexer (MtJX>
2, high frequency components are removed by a low pass filter (LPF) 3 to prevent aliasing distortion, and the output is sampled and held by a sample hold circuit (S/H) 4, and passed through an A-D converter. The data is converted into digital data and output. Here, since the gain values of the logarithmic amplifiers 1-1 to 1-n are necessary for reproducing the data signal, the gain control signals of the logarithmic amplifiers 1-1 to 1-n are also analog-to-digital converted.

即ち、対数増幅器1−1〜1−nのゲインコントロール
信号をアナログマルチブレクサ6で多重化し、LPF7
でその出力の高周波成分を除き、S/H8でデータを保
持し、A−Dコンバータ9でデジタルデータに変換し出
力する.よって、出力は、多重化されたデータ信号と、
データ信号再現のためのゲインコントロール信号を多重
化したものの2系列で出力される。
That is, the gain control signals of the logarithmic amplifiers 1-1 to 1-n are multiplexed by the analog multiplexer 6, and the LPF 7
The high-frequency components of the output are removed, the data is held by the S/H 8, and the data is converted to digital data by the A-D converter 9 and output. Therefore, the output is the multiplexed data signal and
A gain control signal for data signal reproduction is multiplexed and output in two series.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、データ信号と対数増幅器
のゲイン情報たるゲインコントロール信号の両者に1個
づつのA−Dコンバータを持つのみで、多重化率に比例
してアナログ回路節約の効果をあげることができるとい
う効果がある。
As explained above, the present invention has only one A-D converter for both the data signal and the gain control signal which is the gain information of the logarithmic amplifier, and the effect of saving analog circuits is achieved in proportion to the multiplexing ratio. It has the effect of being able to give.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の多重化A−D変換回路の一実施例の楕
戒図、第2図は従来の多重化A−D変換回路の楕戒図で
ある. 1−1〜.1−n・・・対数増幅器、2,6・・・アナ
ログマルチプレクサ、3.7.12・・・ロウパスフィ
ルタ、4,8.13・・・サンプルホールド回路、5,
9.14・・・A−Dコンバータ、1 1−1−11−
n・・・アンプ、15・・・マルチプレクサ。
FIG. 1 is an elliptical diagram of an embodiment of the multiplexed A-D converter circuit of the present invention, and FIG. 2 is an elliptic diagram of a conventional multiplexed A-D converter circuit. 1-1~. 1-n... Logarithmic amplifier, 2, 6... Analog multiplexer, 3.7.12... Low pass filter, 4, 8.13... Sample hold circuit, 5,
9.14...A-D converter, 1 1-1-11-
n...Amplifier, 15...Multiplexer.

Claims (1)

【特許請求の範囲】[Claims]  n個の入力アナログ信号のダイナミックレンジを圧縮
補正するn個の対数増幅器と、前記対数増幅器の出力を
多重化する第1のアナログマルチプレクサと、前記第1
のアナログマルチプレクサの出力の高周波成分を除く第
1のロウパスフィルタと、前記ロウパスフィルタの出力
データをサンプルホールドする第1のサンプルホールド
回路と、前記第1のサンプルホールド回路の出力をデジ
タル信号に変換する第1のA−Dコンバータと、前記n
個の対数増幅器のゲイン値を表現するn個のゲインコン
トロール信号を多重化する第2のアナログマルチプレク
サと、前記第2のアナログマルチプレクサの出力から高
周波成分を除く第2のロウパスフィルタと、この第2の
ロウパスフィルタの出力データをサンプルホールドする
第2のサンプルホールド回路と、前記第2のサンプルホ
ールド回路の出力をデジタル信号に変換する第2のA−
Dコンバータとを備えて成ることを特徴とする多重化A
−D変換回路。
n logarithmic amplifiers for compressing and correcting the dynamic range of n input analog signals; a first analog multiplexer for multiplexing the outputs of the logarithmic amplifiers;
a first low-pass filter that removes high-frequency components from the output of the analog multiplexer; a first sample-and-hold circuit that samples and holds output data of the low-pass filter; and converting the output of the first sample-and-hold circuit into a digital signal. a first A-D converter for converting, and the n
a second analog multiplexer for multiplexing n gain control signals representing the gain values of the logarithmic amplifiers; a second low-pass filter for removing high frequency components from the output of the second analog multiplexer; a second sample-and-hold circuit that samples and holds the output data of the second low-pass filter; and a second sample-and-hold circuit that converts the output of the second sample-and-hold circuit into a digital signal.
Multiplexing A characterized by comprising a D converter.
-D conversion circuit.
JP23194189A 1989-09-06 1989-09-06 Multiplex a/d conversion circuit Pending JPH0394521A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23194189A JPH0394521A (en) 1989-09-06 1989-09-06 Multiplex a/d conversion circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23194189A JPH0394521A (en) 1989-09-06 1989-09-06 Multiplex a/d conversion circuit

Publications (1)

Publication Number Publication Date
JPH0394521A true JPH0394521A (en) 1991-04-19

Family

ID=16931463

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23194189A Pending JPH0394521A (en) 1989-09-06 1989-09-06 Multiplex a/d conversion circuit

Country Status (1)

Country Link
JP (1) JPH0394521A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05227025A (en) * 1991-12-10 1993-09-03 Nec Corp A/d conversion device
ES2153730A1 (en) * 1998-03-27 2001-03-01 Univ Cadiz Data acquisition system for quick sweep spectrophotometry

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05227025A (en) * 1991-12-10 1993-09-03 Nec Corp A/d conversion device
ES2153730A1 (en) * 1998-03-27 2001-03-01 Univ Cadiz Data acquisition system for quick sweep spectrophotometry

Similar Documents

Publication Publication Date Title
EP0383689A2 (en) Digital-to-analog converter
EP1253805A3 (en) Automatic sound field correcting device
US20080012743A1 (en) Method for mixing signals with an analog-to-digital converter
JPH0394521A (en) Multiplex a/d conversion circuit
CN1854741A (en) Multi-band amplifier for test and measurement instruments
JPS62287717A (en) Digital/analog conversion circuit
JP2006165912A (en) Signal processor and image pickup device using the same
US7496417B2 (en) Audio processing system for use in multi-channel audio chip
US20090262620A1 (en) Methods and devices for detecting wobbles on an optical disc
JPH0515087B2 (en)
JPH0632023B2 (en) Voice analyzer
JP3005231B2 (en) Oversampling A / D converter
CN215222021U (en) Synchronous sampling circuit, system and device of multi-channel condenser microphone
JPH0481279B2 (en)
JPS63300699A (en) Network for multi-way speaker equipment
JPH03237821A (en) Signal converter
JPH03238923A (en) A/d converter
JPH04268822A (en) Analog-digital converter
JP2592818B2 (en) Image reading device
JPH05227025A (en) A/d conversion device
JPH0528832Y2 (en)
JPH02303217A (en) Aliasing noise eliminating circuit
JPS63318812A (en) Filter circuit
JPS58221510A (en) Digital audio signal processor
JPS62239198A (en) Voice reproduction circuit