JPH0393946U - - Google Patents
Info
- Publication number
- JPH0393946U JPH0393946U JP113590U JP113590U JPH0393946U JP H0393946 U JPH0393946 U JP H0393946U JP 113590 U JP113590 U JP 113590U JP 113590 U JP113590 U JP 113590U JP H0393946 U JPH0393946 U JP H0393946U
- Authority
- JP
- Japan
- Prior art keywords
- instruction
- instructions
- jump
- storage means
- distributing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 3
- 238000000034 method Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 1
Landscapes
- Advance Control (AREA)
Description
第１図は本考案の基本的構成を示す図、第２図
は本考案を適用したプリンタコントローラのシス
テム回路図、第３図は加算器のアドレス変換処理
内容を示す図、第４図はＣＰＵのパイプライン構
造によるインストラクシヨン処理を示す図、第５
図は基本クロツクに対応する各バンク出力とラツ
チ出力の関係を示すタイミングチヤートである。
１−１〜ｎ……インストラクシヨン記憶手段、
２……分配手段、３……ジヤンプ命令検出手段、
４……インストラクシヨン出力手段、５……ラツ
チ手段、１０……ＣＰＵ。
Fig. 1 is a diagram showing the basic configuration of the present invention, Fig. 2 is a system circuit diagram of a printer controller to which the invention is applied, Fig. 3 is a diagram showing address conversion processing contents of an adder, and Fig. 4 is a CPU Figure 5 shows instruction processing using the pipeline structure of
The figure is a timing chart showing the relationship between each bank output and latch output corresponding to the basic clock. 1-1 to n...instruction storage means,
2...distributing means, 3...jump command detection means,
4... Instruction output means, 5... Latch means, 10... CPU.
Claims (1)
を独立処理する中央演算装置へのインストラクシ
ヨン入力装置において、 それぞれがインストラクシヨンをワード単位で
記憶する複数のインストラクシヨン記憶手段と、 入力された各アドレスに基づいて各インストラ
クシヨンを前記の各記憶手段に分配する分配手段
と、 各記憶手段が記憶しているインストラクシヨン
にジヤンプ命令があるか否か検索し、同命令を検
出するジヤンプ命令検出手段と、 通常は入力されたアドレスと同アドレスに対応
するインストラクシヨンを順次分配手段へ出力し
、ジヤンプ命令検出手段がジヤンプ命令を検出し
た場合には、そのジヤンプ命令に係るアドレスと
インストラクシヨンを優先的に分配手段へ出力す
るインストラクシヨン出力手段と、 各インストラクシヨン記憶手段のインストラク
シヨンをラツチして中央演算装置へ供給させるラ
ツチ手段 とを具備したことを特徴とするインストラクシヨ
ン入力制御装置。[Claims for Utility Model Registration] In an instruction input device to a central processing unit that independently processes addresses, instructions, and data words, a plurality of instruction storage means each storing instructions in units of words. a distributing means for distributing each instruction to each of the above-mentioned storage means based on each input address; and a distributing means for searching for a jump instruction among the instructions stored in each storage means, A jump instruction detection means detects an instruction, and normally outputs instructions corresponding to the same address as the input address to the distribution means in sequence, and when the jump instruction detection means detects a jump instruction, the jump instruction is outputted to the distribution means. an instruction output means for preferentially outputting addresses and instructions related to the instruction to the distribution means; and a latch means for latching the instructions in each instruction storage means and supplying them to the central processing unit. An instruction input control device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP113590U JPH0393946U (en) | 1990-01-10 | 1990-01-10 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP113590U JPH0393946U (en) | 1990-01-10 | 1990-01-10 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0393946U true JPH0393946U (en) | 1991-09-25 |
Family
ID=31505059
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP113590U Pending JPH0393946U (en) | 1990-01-10 | 1990-01-10 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0393946U (en) |
-
1990
- 1990-01-10 JP JP113590U patent/JPH0393946U/ja active Pending
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