JPH0393124A - Timer system for quality control - Google Patents

Abstract

PURPOSE:To make it easy to control quality by enabling a plurality of timers to work successively and sequentially with extraction function and automatically switching to display the passing time on one display. CONSTITUTION:A first timer I starts at the time of receiving a selling signal by operation of an extraction switch, passing time after the extraction time is counted and at the same time the counted time of the timer I is displayed on a display 9. A second timer II starts when a selling signal is sent again at the time of the second extraction and the passing time is counted in the same way, but the passing time is not displayed. Like this, timers start successively at every time of receiving a selling signal and passing times after each extraction time are individually counted. The passing time of the timer I which starts prior is displayed on a display 9 and when the passing time becomes a predetermined time, an alarm means such as a buzzer is worked so as to urge an operator to throw coffee, not sold and left over, away. In this way, quality is controlled easily.

Description

[Detailed Description of the Invention] (a) Industrial Application Field The present invention is applied to coffee brewers that extract coffee and dispensers that dispense various beverages, and is useful for controlling the quality of extracted beverages. Regarding a management timer system.

(B) Conventional Technology Coffee, which is generally in high demand as a beverage, is said to taste best immediately after extraction, and in order to provide delicious coffee, it is necessary to extract it each time. However, when actually serving coffee at a restaurant, etc., generally,
The method used is to extract a large amount of coffee into a decanter at one time.

At this time, if all the extracted coffee cannot be served immediately after extraction, the taste will deteriorate (oxidize) over time.
The common practice was to discard items after a certain period of time (usually around 30 minutes), as this would reduce the value of the product. This time management related to quality was carried out by the operator while checking the clock, and if there were any unsold items after the above-mentioned certain period of time (30 minutes), they were to be thrown away.

(c) Problems to be Solved by the Invention However, with the above-mentioned conventional method, the operator had to constantly watch a clock to judge the elapsed time after extraction, and time management was not easy. In particular, when there are an unspecified number of operators, the reality is that the extracted force cannot be adequately managed at any time. Also, a timer can be used to achieve more accurate time management and ease of use, but in this case as well, it is necessary to press the coffee extraction switch and the timer start switch at the same time, which is still insufficient for operation. I couldn't say it.

The present invention has been made in view of the above points, and allows multiple timers to be operated sequentially in conjunction with the extraction function, and
The purpose of the present invention is to provide a timer system for quality control in which the elapsed time is automatically switched and displayed on a single display, thereby making it easier for an operator to manage coffee. (2) Means for Solving the Problems The quality control timer system according to the present invention starts operation sequentially every time there is a sales signal generated in connection with the extraction operation, and the elapsed time after extraction reaches a predetermined set time. at least two or more timers that count until the timer starts counting, a single display that displays the elapsed time, and a display that displays the elapsed time of only the timer that started first; A conversion circuit that performs connection conversion with the timer, and when a sales signal is input while all timers are operating, resets the first timer to start, and uses the same timer to count the elapsed time related to the last extraction. a display switching circuit that acts on the conversion circuit section to switch and display the elapsed time related to the next start timer on the display; and an alarm that operates when the set time is reached. It consists of means. (e) Effect The first timer starts upon receiving the sales signal from the operation of the extraction switch, and counts the elapsed time from the time of extraction. At the same time, the count time of this timer is displayed on the display. When there is a sales signal again due to the second extraction, the second timer starts and counts the elapsed time in the same way. At this time, the elapsed time is not displayed.

In this way, the timer starts sequentially every time there is a sales signal, and independently counts the elapsed time from each extraction point. Then, the elapsed time of the previously started timer is displayed on the display, and when this elapsed time reaches a preset time, an alarm means such as a buzzer is activated to notify the operator and discard the unsold coffee. Encourage them to do so. In addition, extraction is performed continuously and all timers are activated, and when more extraction is made, the sales signal causes the first start, that is, the timer displayed on the display is automatically reset, and the timer is set to the last. The switching function is used to count the elapsed time related to extraction. At the same time, the elapsed time counted by the timer started next to the switched timer is displayed on this display instead of the reset timer. In this way, in conjunction with the extraction operation, it is possible to sequentially start the plurality of timers and sequentially switch the timer elapsed time display on the display.

(f) Example The present invention will be explained below based on the drawings.

As shown in FIG. 1, the coffee blower 1 consists of a main body IA with a built-in hot water tank, a coffee extractor 100, a decanter 101, and upper and lower insulation heater plates 102 and 103 on which the decanter 101 is placed. , upper heat retention heater plate 1
02 is used to replace the previous decanter 101 when extracting to the second decanter. 104 is a power switch, and 105 and 106 are the heat-retaining heater plates 102, respectively.
, 103 are ON/OFF switches. An operation panel 110 is provided on the front of the upper main body IA, and there are extraction switches 11 for different extraction amounts as shown in FIG.
1, each operation table lamp 107, hot water temperature status display lamp 108, timer display section 9 that displays the elapsed time after extraction, and reset button 1 that clears the timer operation.
4, and a display switching button 1 that allows the set time of the back timer to be called up temporarily on the timer display section 9 as described later.
5 is provided. The present invention makes it possible to accurately control the quality of coffee by making it possible to know how long the coffee is kept warm after brewing. In other words, use at least two timers, start the timers one after another with the extraction switch, and display the timer time of the timer made first until the time limit for coffee deterioration (usually 30 minutes) is reached. When this happens, the timer display is controlled to flash, a buzzer is used, and a time-up indicator light is turned on to display an alarm. A basic block diagram for implementing the above control operation is shown in FIG. 3, and a specific control circuit diagram is shown in FIG.

First, in Fig. 3, timer AI and timer B are both used to count minutes based on the reference frequency from second oscillator 5, and their internal configuration consists of a 60x minute oscillator and a minute/hour counter. . Here, for convenience of explanation, timer AI will be abbreviated as timer A, and timer-all will be abbreviated as timer B, and the subsequent explanation will be continued.

The timer A and the timer B are arbitrarily set for set time by the timer set circuit 6. That is, this set time is the limit time during which coffee after extraction does not deteriorate in quality, and is usually about 30 minutes. And this setting time and timer A
, B are compared, and when the time is up, the count is stopped. On the other hand, a timer switching circuit 8 is provided so that two timers A and B are sequentially started in a sales signal circuit 7 that generates an extraction signal, that is, a sales signal ^, which is generated in conjunction with the extraction switch. ．． The count content of the timer (time elapsed after extraction) is displayed on the display 9,
In this case, the display s9 displays only the one that started first.

In other words, the timer that is displayed on the display 9 is the front timer, and the timer that is performing the counting operation (the timer elapsed time of the later extracted timer) but is not displayed on the display 9 is the back timer. , a conversion circuit 10 is provided for converting the timer A and the timer 8 so that only the front timer is always connected to the display 9. When the count time in the front timer reaches the set time, the front timer generates an alarm that causes the buzzer generation circuit 11 to sound, and the time displayed on the display 9, that is, the set time, flashes. However, the time is over and the operator is prompted to discard the coffee in the decanter. By the way, to explain in detail the manner in which timer switching is performed by sales signal A and timer A and timer B are sequentially started in relation to the sequential operation of the extraction switch, first, timer A is switched on when the power is turned on.
and timer B are both automatically reset and return to their initial states. Then, "00" is displayed on the display 9 for either timer A. Input from B. In this case, for example, if timer B corresponds to display 9 and the first sales signal A is obtained by the extraction switch, the timer is switched so that the start operation starts from timer A. It will be done. Timer A starts counting the elapsed time after extraction. At the same time, the conversion circuit 10 converts the display so that the elapsed time is displayed on the display 9. In other words, timer A becomes a table timer. And if the initial brewed coffee runs out,
Transfer the decanter 101 to the thermal insulation heater plate 102,
A new decanter 101 is set on the lower heater plate 103 and the push switch 111 is pressed to brew coffee for the second time. In this way, when the next second sales signal is received, the timer is switched and timer B is started. At this time, timer B starts as a back timer that independently counts the elapsed time after the second extraction switch operation, but its contents are not displayed on display 9. Of course, the front timer (timer A) continues counting. In this way, both timers A and B operate, and when the front timer (timer A) reaches the set time, the buzzer circuit outputs a W signal and the display 9 flashes.

However, within the set time, the first brewed coffee ran out, and in order to make a third brew, a new carafe of 10
1 on the lower heater plate 103 again, press the extraction switch 111, and when the third sales signal A is generated, a control signal (dotted arrow A') is output, and the reset circuit 12 operates to reset, and at the same time, a control signal (dotted arrow A'') is input to the timer display switching circuit 13, and the display from the timer display switching circuit 13 is generated after a certain time delay. The conversion circuit 10 is controlled by the switching signal so that the back timer (timer) becomes the front timer, and after the switching, timer A, which has become the back timer from the front timer, counts the elapsed time since the third extraction. At the same time, the display 9 displays the elapsed time since the second extraction from timer B. In this way, timer 8 continues to operate as the front timer and timer A as the rear timer, and the fourth extraction is started. From then on, the reset operation is automatically performed.

In addition, the front timer can be reset using the manual reset switch 14.
It is also carried out at In other words, the set time has elapsed and the display N9 is displayed.
The manual reset switch 14 is pressed when the icon flashes and the buzzer sounds, and when the timer count is canceled within the set time. In the former case, only the back timer receives the reset signal and immediately returns to the initial state ("oo" can be displayed and sales signals can be accepted). At the same time, the display is switched after a certain period of time, the true timer becomes the front timer, and the elapsed time extracted later is displayed on the display 9. If no subsequent extraction has been performed, Kl
0 0 II will be displayed. In the latter case, when the manual reset switch 14 is pressed, if there is only one decanter 101, the table timer will be reset and the display will read II O O.
Become II. If there are two decanters 101, after the front timer is reset, the back timer becomes the front timer and the elapsed time extracted later is displayed. 6 Manual display changeover switch 1
5 is pressed to check the elapsed time on the back timer, and while it is held down, the display switching circuit is activated.
The timer elapsed time of a back timer can be displayed on a display 9.

FIG. 4 shows a specific control circuit diagram of the block diagram of FIG. 3 mentioned above. In the figure, constituent parts equivalent to those in FIG. 3 are shown surrounded by dotted lines.

Timer A and timer B both connect the oscillation output from the second oscillator 5 to the analog switch 20. 21, and operates the frequency dividers 2A, 2B and the minute/hour counting units 3A, 3B. Reference numeral 22 is a time setting device for the timer ^, B, which arbitrarily sets the maximum time (usually 30 minutes) after which the coffee is judged to be unsuitable for drinking after brewing. 23. 24 is a comparator, and this time setting device 22
The set time T6 is compared with the elapsed time T counted by each timer A, H, and when T=T, an H level time-up output P. Output each P. H level time-up output P. P is a light emitting diode 25. connected through a resistor. 26 to indicate time up, and inverter 27. 28 and becomes the L level, and each of the analog switches 20. 2
1 is turned OFF, and the counting operation of timer A and timer B is stopped. Also, time-up output P. P is an AND circuit 90. As well as being one input of 91,
This signal is input to the OR circuit 30 of the buzzer generation circuit 11, so that when either timer A or 8 reaches the set time, the buzzer BZ will sound. The buzzer BZ is intermittently sounded by the switching operation of the transistor Tr via the buzzer continuous sound oscillation part 31 and the driver part 32, and notifies that the time is up. r is a volume adjustment resistor for the buzzer BZ. By the way, the elapsed time (minutes) T counted by each of the timers A and B is displayed on the display 9. In this case, the elapsed time T displayed on the display 9 is as follows.
It is necessary to input the count output of the timer started earlier, that is, the front timer, to the decoder 33.

Since timer A and timer B become front timers or back timers B, the output relationship to the decoder 33 must be changed according to the change. Analog switches 34 and 35 perform this conversion. and analog switch 34. 35 turns on the one corresponding to the front timer and turns off the one corresponding to the back timer. Therefore, both analog switches 34. By inputting reverse positive and negative signals to 35, in other words, H is input to one side.
Apply a level signal to the other to make it conductive, and give an L level signal to the other to make it non-conductive. In order to achieve the above control, the analog switch 34 on the timer A side and the analog switch 35 on the timer B side are provided with an output before inversion and an output after inversion via the inverter 36 of the timer display switching circuit l3, respectively. giving. That is, if the A timer is a table timer, the analog switch 34
The H level output after inversion is input to the analog switch 34, while the L level output before inversion is input to the analog switch 34.
The elapsed time T counted by only the A timer is displayed on the display 9 via the decoder 33. Conversely, when the 8 timer becomes a table timer, the same operation occurs in reverse,
This means that only the B timer will display the elapsed time it counts. The inverted output from the inverter 36 is input to the AND circuit 90, while the output before inversion is input to the AND circuit 9l. Therefore, the count output of the timer is input to the decoder 33 and displayed on the display 9.
In the table timer that displays the timer elapsed time T, the elapsed time T is the set time T. Then, each comparator 23. 24, the time-up output P. Since P is output, at that point, AND circuit 90. The AND output of 91 is obtained, and an H level signal is input to the analog switch 38 via the OR circuit 37, turning the switch 38 ON. Then, the oscillation output from the second oscillator 5 is input to the blacking terminal BI of the decoder 33, and the elapsed time being displayed on the display 9, that is, the set time T. is displayed blinking. In this way, the blinking display also indicates that the time is up. Note that 40 is a light emitting diode for displaying seconds, and displays the oscillation output from the seconds oscillator 5 in a blinking manner via an inverter 41.

Reference numeral 42 denotes a power-on reset circuit, which outputs one H-level pulse through an inverter 43 when the power is turned on.

This pulse is a part of the timer switching circuit 8.
Through circuits 44 and 45, it is input to the reset terminal R of the frequency dividers 2A and 2B of timer A and timer B, and each frequency divider 2
At the same time as resetting A and 2B, the minute/hour counter part 3
It is also input to the preset terminals PE of A and 3B to set each minute/time counter part 3A and 3B to an initial state of count O. On the other hand, is it the electric GON reset circuit 42? The above-mentioned one pulse is generated by the flip-flop FF, 4 which inputs the sales signal C from the sales signal generation circuit 7 to the clock terminal CL.
6 (hereinafter, figure number 46 is omitted) to set the output terminal Q of this flip-flop FF■ to the initial state of L level and output terminal 0 to H level, and also reset the output terminal of flip-flop FF247 (hereinafter referred to as 46 is omitted). OR circuit 49. 50
to set each output terminal Q to the L level and each output terminal 6 to the H level in an initial state. One input to the clock terminal CL of the flip-flop FF is set to the output terminal 0 of the flip-flop FF, and
The other input is connected to the output terminal Q of the flip-flop FF.
The AND circuit 51 is directly connected. Similarly, one input to the clock terminal CL of the flip-flop FF is this flip-flop FF, its own output terminal Q, and the other input is the clock terminal CL of the flip-flop FF.
The AND circuit 52 with the output terminal 6 of 1 is connected not directly but with a delay using a CR delay circuit 53. In this delay circuit 53, the AND circuit 52 is activated when the power is turned on, and
This is to prevent the flip-flop FF from malfunctioning. In addition, each flip-flop FF2. Each output terminal Q of the FF is connected to an inverter 54. 55, therefore, when each output terminal Q becomes L-+H level, an inverted output of L level is obtained, and each of the OR circuits 44. 45, each frequency dividing circuit 2A of timer A and timer B,
2B and minute/hour counter 3A, reset terminal R of 3B,
and to the preset terminal PE, respectively, to make it possible to start counting from the initial state. In this way, each timer A and timer B are connected to the OR circuit 44. H output from 45
The timer is preset with a level signal and enters a counting operation state with an L level signal. Furthermore, an OR circuit 44.
45 is an AND circuit 56. There is also an input from 57, but this AND circuit 56. The functions of 57 will be described later.

Next, in the sales signal generation circuit 7, the extraction switch txt
When pressed, the signal is transmitted via the photocoupler 58 and input to the OR circuit 59, and the OR circuit 59 also receives the test signal generated by the test switch TS, which is pressed instead of the extraction switch 111 during the sales test. It is input via an inverter 60.

During the extraction time (for example, 3 minutes), the sales signal A output from the OR circuit 59 in the H level state is input to the inverter 62 via the delay circuit 61 consisting of a resistor R^ and a capacitor CA, and the inverted L level signal The sales signal 8 is further inverted by an inverter 63 to become the original H level sales signal C, which is applied to the clock terminal CL of the flip-flop FF.
Enter. Flip-flop FF1 is operated by the rising edge of the pulse input to this clock terminal CL,
Output terminal Q is set to H level and output terminal Q is set to L level.

Thereafter, each time the next sales signal C is input, the output states of the output terminal Q and the output terminal 2 change sequentially.

Therefore, due to the l-th sale signal C, the flip-flop F
F1 operates, then flip-flop FF2 operates, and the ttH'' level output of its output terminal Q is output to inverter 5.
4. The "L" level output is output via the OR circuit 44, and the A timer becomes a front timer and performs a counting operation. When the next sales signal C is received, flip-flop FF5 operates again, then FF3 operates, its output terminal Q becomes "H" level, and inverter 55. Similarly, an "L" level output is generated via the OR circuit 45, and the B timer starts counting, becoming a back timer. At this time, the AND circuit 64 is operated by the Q output operation of the flip-flop FF and the flip-flop FF at the ``I1'' level, and the AND output is inputted to the OP terminal of the decoder 33 to display the 7-segment structure. A dot is displayed on the lower right of the device 9 to indicate that the back timer has operated.In this way, under the condition that both the front timer and the back timer are operating, when the sales signal (third signal) C is further input, Sales signal A, sales signal B, and the AND output from the AND circuit 64 are input to an AND circuit 65 together with a signal D delayed by a delay circuit 59 made up of a resistor Rc and a capacitor Re, and a reset signal E is generated. As will be detailed later, the reset signal E is such that after the first extraction, there is a second extraction within the set time T0, both timers A and B operate, and then the third extraction occurs as described above. When this is done within the set time T6, it is automatically output and the previously started timer, that is, the table timer currently being displayed, is reset.

Next, in the reset circuit 12, when the reset signal E is automatically output from the AND circuit 65 at H level, the output is transmitted to the reset signal line RL via the OR circuit 66 and the analog switch 67, and the output is transmitted to the AND circuit 56. 57, respectively. However, since the other input terminal of this AND circuit 56 is inputted with the inverted output via the inverter 36, and the other input terminal of the AND circuit 57 is inputted with the output before inversion, this inverted output Or, when the pre-inversion output is at H level, the AND circuit 56. AND output is obtained from 57,
Each OR circuit 44. 45, the H level reset signal E is sent to the frequency divider 2A. It is applied to the reset terminal R of 2B and the preset terminal PE of the minute/hour counter parts 3A and 3B to reset it. Therefore, in other words, the timer being displayed (table timer)
This means that it only accepts resets. Now, you can reset the displayed timer manually as you like. In the manual reset section 68, the manual reset switch l
When 4 is closed, one pulse of H level is outputted through the inverter 69 and becomes a reset signal, which has the same effect.

Incidentally, this automatic reset signal E and one pulse generated by manual reset also serve as an activation signal for the timer display switching circuit 13. The timer display switching circuit 13, which receives the automatic reset signal E and the manual reset reset pulse as input signals, has the following structure. That is, the reset signal from the power ON reset circuit 42 is received at the reset terminal R, the output terminal Q is set to L level, and the output terminal 0 is set to H level.
Flip-flop FF470 initialized to level
(Figure number 70 is omitted hereafter), and the clock terminal CL of this flip-flop FF4 has an automatic reset signal E (
The reset pulse generated by manual reset is also the same) as the time constant Rc. of the delay circuit 71. The signal F delayed according to Cc and further inverted by the inverter 72 is used as one input, and the other input is connected to the flip-flops FF2 and FF,
An AND circuit 74 is connected which outputs a signal G from an OR circuit 73 when any one of them is operating.6Then, the output from the output terminal Q of the flip-flop FF4 is inverted by an inverter 75 and connected to a resistor and an analog switch. 76, one is input to the inverter 36, and the other is directly input as an ON/OFF control signal to the analog switch 35 on the timer B side.
It is input to one side of the ND circuit 91.

Further, the inverted output via the inverter 36 is input as an ON/OFF control signal to the analog switch 34 on the timer A side, and also serves as one input of the AND circuit 90.

Therefore, the flip-flop FF is activated by the first sales signal A.
When the signal G is output from the OR circuit 73 through the operation of the FF, the signal a is ANDed with the signal F, which is normally input to one side of the AND circuit 74 at the "Hlj level", and the AND The flip-flop FF. is activated by the rising signal ■ from the @ path 74, and an "H" level signal is output from the timer display switching circuit 13 via the inverter 75 and the inverter 36. This display switching circuit 13
The output from the inverter 36, that is, the "H" level output, turns the analog switch 34 ON, and the "L" level output before the inverter 36 turns the analog switch 35 OFF.
F, and timer A becomes the front timer and timer B becomes the back timer. Subsequently, when the second sales signal A is received, the counting operation of the back timer (timer B) starts, but
In the display switching circuit 13, since there is no rising signal I via the AND circuit 74, the flip-flop FF. does not operate, and the front and rear outputs of the inverter 36 do not change. Therefore, timer A continues to be the front timer and timer 8 continues to be the back timer. In this way, both timers A
, B operate, and when the third sales signal A is generated, an automatic reset signal E is output and the timer A is reset.

The automatic reset signal E is generated after a certain time delay (according to the time constant RcCc) by setting the AND condition of the AND circuit 74 and generating a rising signal. As a result, the front and rear outputs of the inverter 36 are reversed. That is, the output via the inverter 36 changes to H4L, and the output immediately before inputting to the inverter 36 changes to L4H.

Therefore, the analog switch 34 is turned OFF, the analog switch 35 is turned ON, and the timer B becomes a front timer in which the elapsed time T is displayed on the display 9 via the decoder 33. On the other hand, the reset timer A becomes the back timer and 3
Start counting the elapsed time T required for the first extraction operation. In this way, since two timers are used in this case, the timer display switching signal output from the timer display switching circuit 13 is generated at the third extraction operation, and the timer display is switched. Therefore, if there are N timers in general use, the timer that started first is reset by the first sale signal of Ni, and is made to count the elapsed time related to the last extraction, while the timer that started next first is The front timer and back timer will be sequentially switched to display the elapsed time on the display as the front timer. In this way, the outputs before and after the inverter 36 convert the A timer to the front timer (
At this time, the timer display switching signal is used to select whether the B timer is a back timer) or the B timer is a front timer (at this time, the A timer is a back timer).

By the way, suppose that the analog switch 34 on the front timer side receives an H level signal, and the analog switch 35 on the 1&timer side
When the L level signal is input, the front timer is displayed as a count on the display 9, and when the back timer is counting, the output relationship is forcibly reversed, and the analog switch on the back timer side is temporarily turned on. It is designed to check the elapsed time of the back timer by turning it on. That is, the manual display changeover switch 15 is operated to confirm this, and when the switch 15 is pressed, the two impurators 78. 79, the analog switch 7
An L level signal is input to 6, and the analog switch 76 is turned OFF. On the other hand, another analog switch 80 is turned on by the 11-level inverted output from the third inverter 8l.
becomes. By turning on the analog switch 80, the output from the output terminal Q of the flip-flop FF4 becomes an output via the inverter 75 and the inverter 82, so that the output relationship before and after the inverter 36 is reversed.

Therefore, the back timer temporarily becomes the front timer and the elapsed count time is displayed on the display 9. The display is performed while the manual display changeover switch 15 is held down. When this manual display changeover switch 15 is pressed, the L from the inverter 79 is set so that manual reset is prohibited.
The level output is input to the analog switch 67 to turn it off. Note that when the manual display changeover switch I5 is OFF, the output of the inverter 78 is L, and the output from the inverter 79 is H, so the analog switch 76 is ON. Further, the output from the inverter 81 is L and the analog switch 80 is OFF.

Next, the operation of the above structure will be explained for each functional operation item and with reference to the time chart of FIG.

(a) Automatic reset operation when the power is turned on When the power is turned on, the inverter 4 of the power-on reset circuit 42
3, one pulse is generated, flip-flops FF, FF, FF, FF4 and timer A, timer
Each frequency divider of 8, 2B and minute hour counter part 3A, 3
Set B to the initial state.

? b) Priority operation of timers Since two timers A and B are displayed on one display 9, the first timer operation requires starting the displayed timer, that is, the front timer. Therefore, in the above initial state, when the sales signal A is output from the sales signal generation circuit 7, the rising edge of the sales signal C after a slight delay causes the output terminal Q (hereinafter Q ) becomes uH'' output.At this time, the AND of the AND circuit 51 is established and f(H
” output, and the output terminal Q (hereinafter abbreviated as Q) of flip-flop FF2 (hereinafter abbreviated as FF2) becomes L-
}H output. The "ttH" output is inverted by the inverter 54 and becomes an "L" output, which is input to the frequency divider 2A and the minute/time counter 3A via the OR circuit 44, and the timer A starts counting.

Then, the 0 output of activated FF2 becomes H→S, so A
The ND circuit 51 does not accept sales signals while the timer is operating. Also, since the G output of FF2 becomes L->H, it is input to the AND circuit 74 via the OR circuit 73, and A
AN with the “H” input input to the other side of the ND circuit 74.
Since D is established and a rising signal is given to the clock terminal CL of the flip-flop FF4 (hereinafter referred to as FF4), its output terminal Q (hereinafter referred to as Q) changes from L to H. Therefore, it is inverted at the inverter 75, and further inverted at the inverter 36 through the analog switch 76 which is in a conductive state, resulting in an "H" output, and the analog switch 34 becomes conductive and the count contents of the timer A are displayed through the decoder 33. Displayed on device 9.

When the sales signal is input again. FF outputs 6 →H
Therefore, through the AND circuit 52, the flip-flop F
The Q output of F3 (hereinafter abbreviated as FF3) is L-}}1.

The 11L17 output of the "H" Q output is inputted to the frequency divider 2B and minute time counting section 3B of the 8 timer via the inverter 55 and the OR circuit 845, and the timer enters a counting state. However, since the H output remains input to the AND circuit 74 and does not change, the signal I does not rise and the output state of the FF 4 does not change, so no display switching signal is generated. Therefore, the elapsed time counted by the B timer is not displayed on the display 9. In other words, the B timer becomes a back timer.

(C) Display and confirmation operation when the back timer is operating When the back timer is operating, the dot at the bottom right of the display 9 consisting of seven segments is displayed. (When the timer is operating, the Q output of FF and FF becomes j( H It, so both of them are It H I
The AND circuit 64 detects that the value becomes +. )! When checking the elapsed time of the timer, the inverter 36 is reversed while the manual display changeover switch l5 is pressed, so it can be easily checked. When checking the back timer, the analog switch 67 is made non-conductive so that manual reset is not accepted.

(d) Manual reset operation (alarm stop and timer stop) When the manual reset switch l4 is pressed, the inverter 69 generates one pulse. Then the reset signal line R
Therefore, only the front timer receives this reset signal via the ANI) circuit 56 or the AND circuit 57, and immediately enters the initial state ("o o" display and sales signal can be accepted). At the same time, the display switching pulse is input to the FF after a certain time delay (determined by Re. Cc), so the F
F4 performs a reverse operation, and its front and rear outputs via the inverter 36 are reversed, and as a result, the back timer becomes the front timer (automatic display switching). However, when the back timer is not operating, it performs a reset operation, but the AND circuit 74 prevents display switching to ensure consistency of display. Display consistency means that when a sales signal is input, only the front timer must start when the front timer is // O On.

・When the front timer is running, the back timer must start while the front timer remains the same.

・When both are operating, the table timer is reset,
Next, the back timer switches to the front timer and the back timer starts.

・Manual reset is only accepted for front timers.

- The front timer must always be the timer that started first.

means.

(e) Automatic reset operation If the front timer and back timer are operating and a sales signal is further input, this is an operation that resets the front timer, moves the back timer to the front timer, and then starts the true timer. .

The operation will be explained according to the time chart shown in FIG.

(1) Initial operation When the sales signal A (normally "lul+" during coffee brewing time) is input, after a delay time determined by RA.CA, the C signal and the engineering signal operate as a start-up timer.

(■) Second operation The C signal rises, but the engineering signal does not change, so it starts as a back timer. A. B. D is It H at the same time
Since it does not become IT, no reset signal is generated.

(■) When the third operation sales signal A rises, A, B, and D become “H” at the same time.
”, the automatic reset signal E resets the rise table timer. The reset pulse width is determined by RB and CB.

At the same time, Rc. After the time determined by Cc has elapsed, the signal F rises, the display changes, and the back timer becomes the front timer.

During the time when the above operations are completed, RA. The sales signal C delayed by CA rises after the display is switched, so it starts as a true timer.

Since the front timer and back timer operate again, the waveform D also becomes "H I+. Therefore, since the automatic reset circuit operates in the same manner from the fourth time onward, there is no need to return the timer to the initial state by manual reset.

(f) Alarm action setting time (usually said to be 30 minutes after coffee is brewed)
When the signal reaches 23 or 24, an "H" signal is output, which is inverted by the inverters 27 and 28, and the analog switches 20 and 21 stop the clock input. An LED is provided to display the output, making it easier to inspect the board. Front timer only AND circuit 90 (or AND circuit 91)
The analog switch 38 is turned on via the decoder 33, and the second oscillation signal is guided to the BI (planking) terminal of the decoder 33, causing the display to blink to notify that the display time has reached. Further, in order to attract attention with sound, a signal indicating the arrival of a set time is sent to the buzzer oscillation circuit 11 to make the buzzer BZ sound. Although the buzzer has a volume adjustment function using a resistor, it may also be provided with a buzzer stop switch.

The above is as above. In the embodiment, a count-up method is used, but a count-down method can also be easily adopted. Further, in the embodiment, two timers, a front timer and a back timer, are displayed on one display, but it is also applicable to a case where there are two or more timers.

(G) Effects of the Invention As described above, according to the present invention, a plurality of timers that count the elapsed time after coffee extraction etc. are started sequentially in conjunction with the extraction operation, so the timer operation The operations required for this can be omitted, reducing the burden on the operator regarding quality control.

In addition, we decided to use one display and automatically change the display of the elapsed time in the order of the oldest one (extracted first in RL) in conjunction with the extraction operation, so the operator can All you have to do is pay attention to the pre-extracted coffee, etc., and quality control becomes easier. Then, when a certain time has elapsed, an alarm is issued, and even an unspecified number of operators can easily discard the coffee in question. This has many effects.

[Brief explanation of drawings]

Fig. 1 shows a coffee brewer equipped with a timer system for quality control according to the present invention, (a) is a front view thereof, (b) is a side view thereof, and Fig. 2 is a front view of an operation panel related to coffee extraction operation. 3 is a block diagram of a quality control timer system of the present invention, FIG. 4 is an electric circuit diagram embodying FIG. 3, and FIG. 5 is a time chart. 1...Coffee brewer, I...Timer A,■
... Timer B, 5... Second oscillator, 6... Timer set circuit, 7... Sales signal generation circuit, 8... Timer switching circuit, 9... Display, 10... Conversion Circuit, 1l... Buzzer generation circuit, l2... Reset circuit, 13... Timer display switching circuit, l4... Manual reset switch, l5... Manual display switching switch. Figure 1 IUb Figure 2

Claims (1)

[Claims] At least two or more timers that start each time there is a sales signal generated in connection with the extraction operation and count the elapsed time since the extraction until a predetermined set time, and a unit that displays the elapsed time. One display, a conversion circuit that connects and converts the timer that started so that only the timer that started first always displays its elapsed time, and a source that controls the operation of all timers. Furthermore, when a sales signal is input, the timer for the first start is reset, and the timer functions to count the elapsed time related to the last extraction, and also acts on the conversion circuit section to become the timer for the next start. A timer system for quality control, comprising: a timer display switching circuit that operates to display the elapsed time on the display; and an alarm unit that operates when the set time is reached.