JPH0392053U - - Google Patents
Info
- Publication number
- JPH0392053U JPH0392053U JP71990U JP71990U JPH0392053U JP H0392053 U JPH0392053 U JP H0392053U JP 71990 U JP71990 U JP 71990U JP 71990 U JP71990 U JP 71990U JP H0392053 U JPH0392053 U JP H0392053U
- Authority
- JP
- Japan
- Prior art keywords
- metal plate
- chip
- stage
- resin
- package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000002184 metal Substances 0.000 claims description 6
- 239000011347 resin Substances 0.000 claims description 2
- 229920005989 resin Polymers 0.000 claims description 2
- 238000007789 sealing Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Die Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP71990U JPH0392053U (US20100223739A1-20100909-C00005.png) | 1990-01-09 | 1990-01-09 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP71990U JPH0392053U (US20100223739A1-20100909-C00005.png) | 1990-01-09 | 1990-01-09 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0392053U true JPH0392053U (US20100223739A1-20100909-C00005.png) | 1991-09-19 |
Family
ID=31504660
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP71990U Pending JPH0392053U (US20100223739A1-20100909-C00005.png) | 1990-01-09 | 1990-01-09 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0392053U (US20100223739A1-20100909-C00005.png) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007164741A (ja) * | 2005-12-12 | 2007-06-28 | Figla Co Ltd | 建築現場の管理システム |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6482554A (en) * | 1987-09-24 | 1989-03-28 | Mitsubishi Electric Corp | Resin-sealed semiconductor device |
-
1990
- 1990-01-09 JP JP71990U patent/JPH0392053U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6482554A (en) * | 1987-09-24 | 1989-03-28 | Mitsubishi Electric Corp | Resin-sealed semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007164741A (ja) * | 2005-12-12 | 2007-06-28 | Figla Co Ltd | 建築現場の管理システム |
