JPH0391957A - Manufacture of memory device - Google Patents

Abstract

PURPOSE:To easily manufacture a memory device possessed of a capacitive element of large capacity by a method wherein conductive layers which from one of the electrodes of the capacitive element and a laminar piece which separates the conductive layers from each other in a direction that the source/ drain region of an access transistor extends are successively formed two or more times so as to enable their side walls to come into contact with each other. CONSTITUTION:A first conductive layer 21 is formed so as to be connected to a source/drain region 16b, laminar pieces 22 and 24 and second conductive layers 23, 25, 26, and 27 are successively formed two or more times respectively on the first conductive layer 21 in a direction that one of the source/drain regions 16b extends. In succession, after the laminar pieces 22 and 24 are removed, a dielectric layer 32 and a third conductive layer 33 are formed, the first conductive layer 21 and the second conductive layers 23-27 are made to serve as one of the electrodes of a capacitive element, and the third conductive layer 33 is made to serve as the other electrode of the capacitive element. By this setup, a memory device possessed of a capacitive element of large capacity can be easily manufactured.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a memory device called a DRAM, in which a memory cell is composed of a capacitive element and an access transistor.

[Summary of the invention]

The present invention provides a method for manufacturing a memory device as described above.
By sequentially forming a conductive layer that constitutes one electrode of the capacitive element and a layered body that separates this conductive layer in the direction in which the source/drain regions of the access transistor extend so that they are in contact with each other's sidewalls multiple times. , it is possible to easily manufacture a memory device in which the capacitive element has a large capacity.

[Conventional technology]

A star-socket capacitor cell, in which a capacitive element is also formed on the gate electrode of the access transistor, that is, on the word line, is easy to manufacture because the conventional Brenna cell technology can be applied as is, although the capacitance of the capacitive element can be increased. Therefore, it is becoming the mainstream of DRAM (for example,
Nikkei Microdevice Bessatsu Ko 1” Nikkei McGraw-Hill (
1987.5) p. 117-130).

[Problem to be solved by the invention]

However, with the most basic stacked capacitor cell as described in the above-mentioned document, it is becoming difficult to secure a desired capacity as DRAMs become finer.

In order to solve this problem, it is inevitably required that the capacitive element has a three-dimensional structure. However, such a structure could not be easily manufactured in the past because it was easily damaged during the manufacturing process.

[Means to solve the problem]

The method for manufacturing a memory device according to the present invention includes the steps of forming the first conductive layer 2l so as to be connected to one source/drain region 16b of the access transistor, and forming the first conductive layer 2l on the one source/drain region 16b and Layered bodies 22, 24 and a second layered body having side walls in the vicinity thereof and touching each other's side walls
conductive layers 23, 25 to 27, and the first conductive layer 21.
a step of sequentially reshaping the one source/drain region 16b a plurality of times in the direction in which the one source/drain region 16b spreads; a step of removing the layered bodies 22 and 24;
and a step of forming a dielectric film 32 on the surfaces of the second conductive layers 2l, 23, 25 to 27, and a step of forming a third conductive layer 33 covering the dielectric film 32, respectively, The first and second conductive layers 21, 23 to 27 serve as one electrode of the capacitive element, and the third conductive layer 33 serves as the other electrode of the capacitive element.

[Effect]

In the method for manufacturing a memory device according to the present invention, the layered body 22,
By simply repeating the sequential formation of 24 and the second conductive layers 23, 25 to 27, the opposing area between one electrode and the other electrode of the capacitive element increases.

Further, the second conductive layers 23, 25 to 27 are applied to the layered bodies 22, 2.
Since the second conductive layers 23, 25 to 27 are formed so as to be in contact with the side walls of 4, the second conductive layers 23, 25 to 27 are shaped like a fence, and the second conductive layers 23, 25 are formed in the shape of an eave. ~27 is less likely to be damaged during the manufacturing process.

〔Example〕

Hereinafter, first to fifth embodiments of the present invention will be described with reference to FIGS. 1 to 8.

1 and 2 show a first embodiment.

In this first embodiment, as shown in FIG.
Si? ．． Membrane 1
2 is first formed, and then an SiO2 film 13, which becomes the gate insulating film of the word line, that is, the gate electrode of the access transistor, is formed. Ru.

Then, the polycide layer 14 is patterned in the pattern of the gate electrode of the access transistor, and the N- regions 15a, 15b and the N+ regions 16a, 16b, which will become the source/drain regions of the LDD structure of the access transistor, are self-contained with respect to the polycide layer 14, etc. Administer the precepts in a consistent manner. In addition,
A polycrystalline St film or the like may be used instead of the polycide layer l4.

After that, NSC (Non Doped Sili
A glabellar insulating film 17 such as a Cate Glass film or a PSG film is deposited, and a contact window 18 reaching the N+6I region 16b is opened in the glabellar insulating film 11117. And 2
000 to 4000 thick polycrystalline SilIj! 21
is deposited so as to be in contact with the N9 region 16b.

After that, a thick NSC film 22 is deposited, and this NSC film 2
2, a portion where a capacitive element is to be formed is removed by RIE. Note that an SOG film or the like may be used instead of the NSC film 22. Further, a polycrystalline Si film 23 is deposited so as to be in contact with the polycrystalline Si film 21.

Next, the entire surface of the polycrystalline Si film 23 is subjected to RIEL, and as shown in FIG.
leave. Note that even if the polycrystalline Si film 23 is etched,
The polycrystalline St film 21 is made to remain with a sufficient thickness. Then, an NSC film 24 is further deposited.

Next, the entire surface of the NSC film 24 is subjected to RIEL, leaving the NSC film 24 only on the side walls of the polycrystalline St film 23, as shown in FIG. Further, the polycrystalline Si film 25 is
Deposit it so that it is in contact with 1.

Next, as in the case of the polycrystalline Si film 23, the entire surface of the polycrystalline Si film 25 is subjected to RIEL, leaving the polycrystalline Si film 25 only on the side walls of the NSG film 24. Then, by repeating the above-mentioned process several times, the polycrystalline Si film 2 is formed as shown in FIG.
6 and 27 are further shaped into a fence.

Thereafter, the NSC films 22, 24, etc. are removed using hydrofluoric acid or the like, and a resist 28 is patterned in a region where a capacitive element is to be formed.

Then, when the polycrystalline Si film 2l is separated into memory cells using a resist 28 and the resist 28 is removed, coaxial rectangular cylindrical polycrystalline Si films 23, 25 to 2 are formed as shown in FIG.
7 is obtained. Therefore, polycrystalline Si films 21, 23, 25
27 becomes one electrode of the capacitive element connected to the N'' region 16b, that is, a storage node.

Thereafter, a dielectric film is formed on the surfaces of the polycrystalline Si films 21, 23, 25 to 27, etc., and the other electrode of the capacitive element is formed with the polycrystalline Si film covering this dielectric film, and the N' region 16a is A contacting bit line is formed to complete the DRAM memory cell.

3 and 4 show a second embodiment, and correspond to FIGS. 1 and 2, respectively, of the first embodiment described above.

While the first embodiment sequentially forms the polycrystalline Si film 23 and the like on the inner periphery of the opening of the NSC film 22, the second embodiment sequentially forms the polycrystalline St film 23 and the like on the outer periphery of the NSC film 22. are explained in order, but in other respects this second embodiment has substantially the same steps as the first embodiment described above.

5 and 6 show a third embodiment.

In this third embodiment as well, as shown in FIG. 5A, polycrystalline S1
The steps up to the formation of the film 21 are carried out in the same manner as in the first and second embodiments described above.

After that, an NSC film 22 with a thickness of several thousand layers is deposited,
The NSC film 22 is patterned so as to pass over the N'' region 16b and extend between the polycide layers 14 as shown in FIG. An SOG film or the like may be used instead of the film 220.

Next, as shown in FIG. 5B, a polycrystalline St film 23 with a thickness of several hundred to several thousand layers is deposited and the entire surface is subjected to RIE, and an NSC film 24 is deposited with a thickness of several hundred layers and the entire surface is subjected to RIE. The polycrystalline St film 23 is sequentially manipulated to both sides of the NSC film 22.
, 25 to 27, the NSC film 24, etc. are formed into a wall shape.

Next, as shown in FIG. 5C, polycrystalline Si films 21, 23,
A polycrystalline Si film 31 is deposited so as to be in contact with 25 to 27, and a resist 28 is further patterned to cover only the portion of this polycrystalline St film 31 where a capacitive element is to be formed.

Then, using the resist 28 as a mask, the polycrystalline Si film 31 is
RIE is performed, but at this time some overetching is performed. Then, in the region not covered with the resist 28, the NSC film 22 is removed together with the polycrystalline St films 21, 23, 25-27.
, 24 etc. are exposed.

Therefore, the NSC films 22, 24, etc. are removed using hydrofluoric acid or the like, and as a result, the NSC films 22, 24, etc. in the regions covered with the resist 28 are also removed. Therefore, a tunnel-like cavity is formed under the resist 28 in the portion where the NSC films 22, 24, etc. were present.

Next, with the resist 28 remaining, the polycrystalline Si film 2 is
1 to RIEt, and as shown in FIG. 5D, this polycrystalline S
ill21 is separated for each memory cell. As a result, a certain storage node is obtained from the polycrystalline Si films 21, 23, 25-27, and 31.

After that, the resist 28 is removed and the polycrystalline Si films 21, 2
A dielectric film 32 is formed on the surfaces of 3, 25 to 27, 31, etc., and this dielectric film 32 is also formed on the inner surface of the cavity where the NSC films 22, 24, etc. were present.

A polycrystalline Si film 33 covering the dielectric film 32 forms the other electrode of the capacitive element, but this polycrystalline Si film 33 also fills the cavities where the NSC films 22, 24, etc. were present.

Further, a bit line contacting the N9 region 16a is formed to complete the DRAM memory cell.

In the DRAM manufactured in the third embodiment as described above, the tips of the wall-shaped polycrystalline Si films 23, 25 to 27 are connected to each other by polycrystalline St.
Since they are connected by the film 31, the strength of the entire storage node is higher than that of the DRAMs manufactured in the first and second embodiments described above, and the storage node is less likely to be damaged during the manufacturing process.

FIG. 7 shows a fourth embodiment. In this fourth embodiment as well, as shown in FIG. 7A, the steps up to the formation of the interlayer insulating film 17 are carried out in the same manner as in the above-described first to third embodiments. However, this fourth
In the embodiment, an NSC film is used as the interlayer insulating film 17.

Next, as shown in FIG. 7B, the resist 34 is patterned so that only the region where the capacitive element is to be formed is opened, and using this resist 34 as a mask, the P+ ions 35 are
Ions are implanted into the surface of the glabella insulating film 17 by approximately X 10 I6 cm-z.

Next, as shown in FIG. 7C, the resist 34 is removed and the N
A contact window 18 reaching the "fiJl region 16b" is opened in the interlayer insulating film 17, and a polycrystalline Si film 21 is deposited so as to be in contact with the "N" region 16b.

Then, the polycrystalline Si film 2l that is in contact with the part of the glabella insulating film 17 doped with P' ions 35 at a high concentration as described above grows abnormally, and the protrusions of the polycrystalline Si film 21 grow in the order of thousands. It reaches about 1 μm.

Note that a PSG film doped with phosphorus at a high concentration of about 4 to 10% by weight may be used as the glabellar insulating film 17, and in that case, ion implantation of the P+ ions 35 is not necessary. However, in that case, the entire surface of the polycrystalline St film 21 becomes abnormally long,
Processing becomes a little more difficult.

After that, the resist 28 is patterned in the region where the capacitive element is to be formed.

Next, as shown in FIG. 7D, the polycrystalline St film 21 is separated into memory cells using a resist 28 to form storage nodes, and the resist 28 is removed.

Thereafter, a dielectric film 32 is formed on the surface of the polycrystalline Si film 21, etc., and the other electrode of the capacitive element is formed with the polycrystalline Si film 33 covering the dielectric film 32, and the bit contacting the N'' region 16a is formed. A line is formed to complete the DRAM memory cell.

In the DRAM manufactured in the fourth embodiment as described above, the polycrystalline Si film 2l is abnormally lengthened and protrusions are formed.
The effective area of the storage node constituted by this polycrystalline Si film 21 is large.

FIG. 8 shows a fifth embodiment. In this fifth embodiment, instead of implanting P ions 36 into the surface of the glabellar insulating film 17, a polycrystalline St film 36 is deposited on the interlayer insulating film 17 as shown in FIG. 8A. Polycrystalline Si film 3
P9 ions 35 are implanted into the surface of the polycrystalline Si film 21 on the polycrystalline Si film 36 as shown in FIG. 8B.
The process is substantially similar to that of the fourth embodiment described above, except for depositing.

〔Effect of the invention〕

In the method for manufacturing a memory device according to the present invention, a layered body and a second
The opposing area between one electrode and the other electrode of the capacitive element increases by simply repeating the formation of the conductive layer in sequence.
Moreover, since the second conductive layer is less likely to be damaged during the manufacturing process, it is possible to easily manufacture a memory device in which the capacitive element has a large capacity.

[Brief explanation of drawings]

1 is a side sectional view sequentially showing a first embodiment of the present invention, FIG. 2 is a plan view showing intermediate steps in the first embodiment, and FIG. 3 is a side sectional view sequentially showing a second embodiment. 4 is a plan view showing an intermediate step in the second embodiment, FIG. 5 is a side sectional view sequentially showing the third embodiment, and FIG. 6 is a plan view showing an intermediate step in the third embodiment. 7 are side sectional views sequentially showing the fourth embodiment,
FIG. 8 is a side sectional view showing an intermediate step in the fifth embodiment. In addition, in the symbols used in the drawings, 16b-・---1-----...-N1 area 21,
23, 25.26, 27.33 1.--1--..--1 polycrystalline Si film 22.24
・−・・−−−−−1・NSG film 32・・−・
・・−・−・−−−−−−・One dielectric film.

Claims (1)

[Claims] A method for manufacturing a memory device in which a memory cell is configured of a capacitive element and an access transistor, comprising: forming a first conductive layer so as to be connected to one source/drain region of the access transistor. a layered body and a second conductive layer each having a sidewall on and near the one source/drain region and in contact with each other's sidewall; and a second conductive layer on the first conductive layer.・Sequentially forming the drain region multiple times in the direction in which it spreads; removing the layered body; and forming a dielectric film on the surfaces of the first and second conductive layers after the removal. , forming a third conductive layer covering the dielectric film, the first and second conductive layers being one electrode of the capacitive element, and the third conductive layer being the A method for manufacturing a memory device in which the other electrode of a capacitive element is used as the other electrode.