JPH0391957A - Manufacture of memory device - Google Patents

Manufacture of memory device

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Publication number
JPH0391957A
JPH0391957A JP1228618A JP22861889A JPH0391957A JP H0391957 A JPH0391957 A JP H0391957A JP 1228618 A JP1228618 A JP 1228618A JP 22861889 A JP22861889 A JP 22861889A JP H0391957 A JPH0391957 A JP H0391957A
Authority
JP
Japan
Prior art keywords
film
polycrystalline
capacitive element
conductive layer
memory device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1228618A
Other languages
Japanese (ja)
Inventor
Hideaki Kuroda
英明 黒田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP1228618A priority Critical patent/JPH0391957A/en
Publication of JPH0391957A publication Critical patent/JPH0391957A/en
Pending legal-status Critical Current

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  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To easily manufacture a memory device possessed of a capacitive element of large capacity by a method wherein conductive layers which from one of the electrodes of the capacitive element and a laminar piece which separates the conductive layers from each other in a direction that the source/ drain region of an access transistor extends are successively formed two or more times so as to enable their side walls to come into contact with each other. CONSTITUTION:A first conductive layer 21 is formed so as to be connected to a source/drain region 16b, laminar pieces 22 and 24 and second conductive layers 23, 25, 26, and 27 are successively formed two or more times respectively on the first conductive layer 21 in a direction that one of the source/drain regions 16b extends. In succession, after the laminar pieces 22 and 24 are removed, a dielectric layer 32 and a third conductive layer 33 are formed, the first conductive layer 21 and the second conductive layers 23-27 are made to serve as one of the electrodes of a capacitive element, and the third conductive layer 33 is made to serve as the other electrode of the capacitive element. By this setup, a memory device possessed of a capacitive element of large capacity can be easily manufactured.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、容量素子とアクセストランジスタとでメモリ
セルが構成されておりDRAMと称されているメモリ装
置の製造方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a memory device called a DRAM, in which a memory cell is composed of a capacitive element and an access transistor.

〔発明の概要〕[Summary of the invention]

本発明は、上記の様なメモリ装置の製造方法において、
容量素子の一方の電極を構威する導電層とこの導電層を
アクセストランジスタのソース・ドレイン領域の広がる
方向で分離する層状体とを互いの側壁に接する様に順次
に複数回ずつ形成することによって、容量素子の容量が
大きいメモリ装置を容易に製造することができる様にし
たものである。
The present invention provides a method for manufacturing a memory device as described above.
By sequentially forming a conductive layer that constitutes one electrode of the capacitive element and a layered body that separates this conductive layer in the direction in which the source/drain regions of the access transistor extend so that they are in contact with each other's sidewalls multiple times. , it is possible to easily manufacture a memory device in which the capacitive element has a large capacity.

〔従来の技術〕[Conventional technology]

アクセストランジスタのゲート電極つまりワード線上に
も容量素子を形成したスタソクトキャパシタセルは、容
量素子の容量を大きくすることができるにも拘らず、従
来のブレーナセルの技術をそのまま応用でき製造が容易
であるので、DRAMの主流になりつつある(例えば「
日経マイクロデバイス別冊弘1」日経マグロウヒル社(
1987.5)p.117〜130)。
A star-socket capacitor cell, in which a capacitive element is also formed on the gate electrode of the access transistor, that is, on the word line, is easy to manufacture because the conventional Brenna cell technology can be applied as is, although the capacitance of the capacitive element can be increased. Therefore, it is becoming the mainstream of DRAM (for example,
Nikkei Microdevice Bessatsu Ko 1” Nikkei McGraw-Hill (
1987.5) p. 117-130).

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

ところが、上記文献に記載されている様な最も基本的な
スタックトキャバシタセルでは、DRAMの微細化に伴
って所望容量の確保が難しくなってきている。
However, with the most basic stacked capacitor cell as described in the above-mentioned document, it is becoming difficult to secure a desired capacity as DRAMs become finer.

これを解決するために、容量素子を立体的な構造にする
ことが必然的に要求されている。しかしこの様な構造は
、製造過程で破損し易かったりして、従来は容易には製
造することができなかった。
In order to solve this problem, it is inevitably required that the capacitive element has a three-dimensional structure. However, such a structure could not be easily manufactured in the past because it was easily damaged during the manufacturing process.

〔課題を解決するための手段〕[Means to solve the problem]

本発明によるメモリ装置の製造方法は、アクセストラン
ジスタの一方のソース・ドレイン領域16bに接続する
様に第1の導電層2lを形戒する工程と、各々が前記一
方のソース・ドレイン領域16b上及びその近傍で側壁
を有し互いの前記側壁に接する層状体22、24と第2
の導電層23、25〜27とを、前記第1の導電層21
上において前記一方のソース・ドレイン領域16bの広
がる方向へ順次に複数回ずつ形戒する工程と、前記層状
体22、24を除去する工程と、前記除去後の前記第1
及び第2の導電層2l、23、25〜27の表面に誘電
体膜32を形成する工程と、前記誘電体膜32を覆って
第3の導電層33を形成する工程とを夫々具備し、前記
第1及び第2の導電層21、23〜27を容量素子の一
方の電極とし、前記第3の導電JiI33を前記容量素
子の他方の電極とする様にしている。
The method for manufacturing a memory device according to the present invention includes the steps of forming the first conductive layer 2l so as to be connected to one source/drain region 16b of the access transistor, and forming the first conductive layer 2l on the one source/drain region 16b and Layered bodies 22, 24 and a second layered body having side walls in the vicinity thereof and touching each other's side walls
conductive layers 23, 25 to 27, and the first conductive layer 21.
a step of sequentially reshaping the one source/drain region 16b a plurality of times in the direction in which the one source/drain region 16b spreads; a step of removing the layered bodies 22 and 24;
and a step of forming a dielectric film 32 on the surfaces of the second conductive layers 2l, 23, 25 to 27, and a step of forming a third conductive layer 33 covering the dielectric film 32, respectively, The first and second conductive layers 21, 23 to 27 serve as one electrode of the capacitive element, and the third conductive layer 33 serves as the other electrode of the capacitive element.

〔作用〕[Effect]

本発明によるメモリ装置の製造方法では、層状体22、
24と第2の導電層23、25〜27とを順次に形成す
ることを繰り返すだけで、容量素子の一方の電極と他方
の電極との対向面積が増加する。
In the method for manufacturing a memory device according to the present invention, the layered body 22,
By simply repeating the sequential formation of 24 and the second conductive layers 23, 25 to 27, the opposing area between one electrode and the other electrode of the capacitive element increases.

また、第2の導電層23、25〜27を層状体22、2
4の側壁に接する様に形成しているので、第2の導電層
23、25〜27は塀状に形戒され、庇状等に形成され
る場合に比べて第2の導電層23、25〜27が製造過
程で破損しにくい。
Further, the second conductive layers 23, 25 to 27 are applied to the layered bodies 22, 2.
Since the second conductive layers 23, 25 to 27 are formed so as to be in contact with the side walls of 4, the second conductive layers 23, 25 to 27 are shaped like a fence, and the second conductive layers 23, 25 are formed in the shape of an eave. ~27 is less likely to be damaged during the manufacturing process.

〔実施例〕〔Example〕

以下、本発明の第1〜第5実施例を、第1図〜第8図を
参照しながら説明する。
Hereinafter, first to fifth embodiments of the present invention will be described with reference to FIGS. 1 to 8.

第1図及び第2図が、第1実施例を示している。1 and 2 show a first embodiment.

この第1実施例では、第IA図に示す様に、LOCOS
法等によってSt基板11に素子分離用のSi?.膜1
2をまず形成し、ワード線つまりアクセストランジスタ
のゲート電極のゲート絶縁膜になるSiO■膜13をそ
の後に形成す.る。
In this first embodiment, as shown in FIG.
Si? .. Membrane 1
2 is first formed, and then an SiO2 film 13, which becomes the gate insulating film of the word line, that is, the gate electrode of the access transistor, is formed. Ru.

そして、ポリサイド層14をアクセストランジスタのゲ
ート電極のパターンにパターニングし、アクセストラン
ジスタのLDD構造のソース・ドレイン領域になるN一
領域15a、15b及びN+領域16a、16bをポリ
サイド層14等に対して自己整合的に形戒する。なお、
ポリサイド層l4の代りに多結晶St膜等を用いてもよ
い。
Then, the polycide layer 14 is patterned in the pattern of the gate electrode of the access transistor, and the N- regions 15a, 15b and the N+ regions 16a, 16b, which will become the source/drain regions of the LDD structure of the access transistor, are self-contained with respect to the polycide layer 14, etc. Administer the precepts in a consistent manner. In addition,
A polycrystalline St film or the like may be used instead of the polycide layer l4.

その後、N S C (Non Doped Sili
cate Glass)膜やPSG膜等である眉間絶縁
膜17を堆積させ、N+6I域16bに達するコンタク
ト窓18を眉間絶縁11117に開口する。そして、2
000〜4000人程度の厚い多結晶SilIj!21
を、N9領域16bとコンタクトする様に堆積させる。
After that, NSC (Non Doped Sili
A glabellar insulating film 17 such as a Cate Glass film or a PSG film is deposited, and a contact window 18 reaching the N+6I region 16b is opened in the glabellar insulating film 11117. And 2
000 to 4000 thick polycrystalline SilIj! 21
is deposited so as to be in contact with the N9 region 16b.

その後、NSC膜22を厚く堆積させ、このNSC膜2
2のうちで容量素子を形成すべき部分をRIEで除去す
る。なお、NSC膜22の代りにSOG膜等を用いても
よい。そして更に、多結晶Si膜23を、多結晶Si膜
21とコンタクトする様に堆積させる。
After that, a thick NSC film 22 is deposited, and this NSC film 2
2, a portion where a capacitive element is to be formed is removed by RIE. Note that an SOG film or the like may be used instead of the NSC film 22. Further, a polycrystalline Si film 23 is deposited so as to be in contact with the polycrystalline Si film 21.

次に、多結晶Si膜23を全面RIELて、第IB図に
示す様に、NSC膜22の側壁にのみ多結晶St膜23
を残す。なお、多結晶Si膜23をエソチングしても、
多結晶St膜21は十分な厚さで残る様にする。そして
更に、NSC膜24を堆積させる。
Next, the entire surface of the polycrystalline Si film 23 is subjected to RIEL, and as shown in FIG.
leave. Note that even if the polycrystalline Si film 23 is etched,
The polycrystalline St film 21 is made to remain with a sufficient thickness. Then, an NSC film 24 is further deposited.

次に、NSC膜24を全面RIELて、第IC図に示す
様に、多結晶St膜23の側壁にのみNSC膜24を残
す。そして更に、多結晶Si膜25を、多結晶Si膜2
1とコンタクトする様に堆積させる。
Next, the entire surface of the NSC film 24 is subjected to RIEL, leaving the NSC film 24 only on the side walls of the polycrystalline St film 23, as shown in FIG. Further, the polycrystalline Si film 25 is
Deposit it so that it is in contact with 1.

次に、多結晶Si膜23の場合と同様に、多結晶Si膜
25を全面RIELてNSG膜24の側壁にのみ多結晶
Si膜25を残す。そして、以後、上述の様な工程を何
回か繰り返して、第lD図に示す様に、多結晶Si膜2
6、27を更に塀状に形戒する。
Next, as in the case of the polycrystalline Si film 23, the entire surface of the polycrystalline Si film 25 is subjected to RIEL, leaving the polycrystalline Si film 25 only on the side walls of the NSG film 24. Then, by repeating the above-mentioned process several times, the polycrystalline Si film 2 is formed as shown in FIG.
6 and 27 are further shaped into a fence.

その後、NSC膜22、24等をフン化水素酸等で除去
し、容量素子を形成すべき領域にレジスト28をパター
ニングする。
Thereafter, the NSC films 22, 24, etc. are removed using hydrofluoric acid or the like, and a resist 28 is patterned in a region where a capacitive element is to be formed.

そして、レジスト28を用いて多結晶Si膜2lをメモ
リセル毎に分離し、レジスト28を除去すると、第2図
に示す様に、同軸角筒状の多結晶Si膜23、25〜2
7が得られる。従って、多結晶Si膜21、23、25
〜27が、N″領域16bに接続されている容量素子の
一方の電極つまり記憶ノードになる。
Then, when the polycrystalline Si film 2l is separated into memory cells using a resist 28 and the resist 28 is removed, coaxial rectangular cylindrical polycrystalline Si films 23, 25 to 2 are formed as shown in FIG.
7 is obtained. Therefore, polycrystalline Si films 21, 23, 25
27 becomes one electrode of the capacitive element connected to the N'' region 16b, that is, a storage node.

その後、多結晶Si膜21、23、25〜27の表面等
に誘電体膜を形成し、この誘電体膜を覆う多結晶Si膜
で容量素子の他方の電極を形成し、N゛領域16aにコ
ンタクトするビット線を形成して、DRAMのメモリセ
ルを完威させる。
Thereafter, a dielectric film is formed on the surfaces of the polycrystalline Si films 21, 23, 25 to 27, etc., and the other electrode of the capacitive element is formed with the polycrystalline Si film covering this dielectric film, and the N' region 16a is A contacting bit line is formed to complete the DRAM memory cell.

第3図及び第4図は、第2実施例を示しており、上述の
第1実施例の夫々第1図及び第2図に対応している。
3 and 4 show a second embodiment, and correspond to FIGS. 1 and 2, respectively, of the first embodiment described above.

第1実施例がNSC膜22の開口の内周に多結晶Si膜
23等を順次に形成しているのに対して、この第2実施
例はNSC膜22の外周に多結晶St膜23等を順次に
形戒しているが、その他の点ではこの第2実施例は上述
の第1実施例と実質的に同様の工程を有している。
While the first embodiment sequentially forms the polycrystalline Si film 23 and the like on the inner periphery of the opening of the NSC film 22, the second embodiment sequentially forms the polycrystalline St film 23 and the like on the outer periphery of the NSC film 22. are explained in order, but in other respects this second embodiment has substantially the same steps as the first embodiment described above.

第5図及び第6図は、第3実施例を示している。5 and 6 show a third embodiment.

この第3実施例でも、第5A図に示す様に、多結晶S1
膜21の形成までは上述の第1及び第2実施例と同様に
行う。
In this third embodiment as well, as shown in FIG. 5A, polycrystalline S1
The steps up to the formation of the film 21 are carried out in the same manner as in the first and second embodiments described above.

その後、数千人程度の厚さのNSC膜22を堆積させ、
N″領域16b上を通過し且つ第6図に示す様にポリサ
イド層14同士の間を延びる様に、NSC膜22をパタ
ーニングする。なお、上述の第1及び第2実施例と同様
に、NSC膜220代りにSOG膜等を用いてもよい。
After that, an NSC film 22 with a thickness of several thousand layers is deposited,
The NSC film 22 is patterned so as to pass over the N'' region 16b and extend between the polycide layers 14 as shown in FIG. An SOG film or the like may be used instead of the film 220.

次に、第5B図に示す様に、数百〜数千人程度の厚さの
多結晶St膜23の堆積及び全面RIEと、数百人程度
の厚さのNSC膜24の堆積及び全面RIEとを順次に
操り返して、NSC膜22の両側方へ多結晶St膜23
、25〜27とNSC膜24等とを塀状に形成する。
Next, as shown in FIG. 5B, a polycrystalline St film 23 with a thickness of several hundred to several thousand layers is deposited and the entire surface is subjected to RIE, and an NSC film 24 is deposited with a thickness of several hundred layers and the entire surface is subjected to RIE. The polycrystalline St film 23 is sequentially manipulated to both sides of the NSC film 22.
, 25 to 27, the NSC film 24, etc. are formed into a wall shape.

次に、第5C図に示す様に、多結晶Si膜21、23、
25〜27にコンタクトする様に多結晶Si膜31を堆
積させ、更に、この多結晶St膜31のうちで容量素子
を形成すべき部分のみを覆う様にレジスト28をパター
ニングする。
Next, as shown in FIG. 5C, polycrystalline Si films 21, 23,
A polycrystalline Si film 31 is deposited so as to be in contact with 25 to 27, and a resist 28 is further patterned to cover only the portion of this polycrystalline St film 31 where a capacitive element is to be formed.

そして、レジスト28をマスクにして多結晶Si膜31
をRIEするが、このとき幾分オーバエッチングを行う
。すると、レジスト28で覆われていない領域では、多
結晶St膜21、23、25〜27と共にNSC膜22
、24等が露出する。
Then, using the resist 28 as a mask, the polycrystalline Si film 31 is
RIE is performed, but at this time some overetching is performed. Then, in the region not covered with the resist 28, the NSC film 22 is removed together with the polycrystalline St films 21, 23, 25-27.
, 24 etc. are exposed.

そこで、NSC膜22、24等をフッ化水素酸等で除去
するが、これによって、レジスト28で覆われている領
域のNSC膜22、24等も除去される。従って、レジ
スト28下には、NSC膜22、24等が存在していた
部分にトンネル状の空洞が形成される。
Therefore, the NSC films 22, 24, etc. are removed using hydrofluoric acid or the like, and as a result, the NSC films 22, 24, etc. in the regions covered with the resist 28 are also removed. Therefore, a tunnel-like cavity is formed under the resist 28 in the portion where the NSC films 22, 24, etc. were present.

次に、レジスト28を残存させたままで多結晶Si膜2
1をRIEt,て、第5D図に示す様に、この多結晶S
illl21をメモリセル毎に分離する。これによって
、多結晶Si膜21、23、25〜27、31から或る
記憶ノードが得られる。
Next, with the resist 28 remaining, the polycrystalline Si film 2 is
1 to RIEt, and as shown in FIG. 5D, this polycrystalline S
ill21 is separated for each memory cell. As a result, a certain storage node is obtained from the polycrystalline Si films 21, 23, 25-27, and 31.

その後、レジスト28を除去し、多結晶Si膜21、2
3、25〜27、31の表面等に誘電体膜32を形成す
るが、この誘電体膜32はNSC膜22、24等が存在
していた空洞の内面にも形戒される。
After that, the resist 28 is removed and the polycrystalline Si films 21, 2
A dielectric film 32 is formed on the surfaces of 3, 25 to 27, 31, etc., and this dielectric film 32 is also formed on the inner surface of the cavity where the NSC films 22, 24, etc. were present.

そして、誘電体膜32を覆う多結晶Si膜33で容量素
子の他方の電極を形戒するが、この多結晶Si膜33は
NSC膜22、24等が存在していた空洞をも埋める。
A polycrystalline Si film 33 covering the dielectric film 32 forms the other electrode of the capacitive element, but this polycrystalline Si film 33 also fills the cavities where the NSC films 22, 24, etc. were present.

そして更に、N9領域16aにコンタクトするビット線
を形成して、DRAMのメモリセルを完威させる。
Further, a bit line contacting the N9 region 16a is formed to complete the DRAM memory cell.

以上の様な第3実施例で製造したDRAMでは、塀状の
多結晶Si膜23、25〜27の先端同士を多結晶St
膜31で連結しているので、上述の第1及び第2実施例
で製造したDRAMよりも記憶ノード全体の強度が高く
、記憶ノードが製造過程で破損しにくい。
In the DRAM manufactured in the third embodiment as described above, the tips of the wall-shaped polycrystalline Si films 23, 25 to 27 are connected to each other by polycrystalline St.
Since they are connected by the film 31, the strength of the entire storage node is higher than that of the DRAMs manufactured in the first and second embodiments described above, and the storage node is less likely to be damaged during the manufacturing process.

第7図は、第4実施例を示している。この第4実施例で
も、第7A図に示す様に、層間絶縁膜17の形成までは
上述の第1〜第3実施例と同様に行う。但し、この第4
実施例では、層間絶縁膜17としてNSC膜を用いる。
FIG. 7 shows a fourth embodiment. In this fourth embodiment as well, as shown in FIG. 7A, the steps up to the formation of the interlayer insulating film 17 are carried out in the same manner as in the above-described first to third embodiments. However, this fourth
In the embodiment, an NSC film is used as the interlayer insulating film 17.

次に、第7B図に示す様に、容量素子を形成すべき領域
のみが開口する様にレジスト34をパターニングし、こ
のレジスト34をマスクにして、P+イオン35をI 
X 1 0 I6cm−z程度だけ眉間絶縁膜17の表
面にイオン注入する。
Next, as shown in FIG. 7B, the resist 34 is patterned so that only the region where the capacitive element is to be formed is opened, and using this resist 34 as a mask, the P+ ions 35 are
Ions are implanted into the surface of the glabella insulating film 17 by approximately X 10 I6 cm-z.

次に、第7C図に示す様に、レジスト34を除去し、N
”fiJl域16bに達するコンタクト窓18を層間絶
縁膜17に開口し、N″領域16bとコンタクトする様
に多結晶Si膜21を堆積させる。
Next, as shown in FIG. 7C, the resist 34 is removed and the N
A contact window 18 reaching the "fiJl region 16b" is opened in the interlayer insulating film 17, and a polycrystalline Si film 21 is deposited so as to be in contact with the "N" region 16b.

すると、眉間絶縁膜17のうちで上述の様にP゛イオン
35を高濃度にドーピングした部分に接している多結晶
Si膜2lが異常成長し、多結晶Si膜21の突起は数
千人〜1μm程度にも達する。
Then, the polycrystalline Si film 2l that is in contact with the part of the glabella insulating film 17 doped with P' ions 35 at a high concentration as described above grows abnormally, and the protrusions of the polycrystalline Si film 21 grow in the order of thousands. It reaches about 1 μm.

なお、リンを4〜10重量%程度と高濃度にドーピング
したPSG膜を眉間絶縁膜17として用いてもよく、そ
の場合はP+イオン35のイオン注入が不要である。但
し、その場合は多結晶St膜21の全面が異常戒長し、
加工がやや難しくなる。
Note that a PSG film doped with phosphorus at a high concentration of about 4 to 10% by weight may be used as the glabellar insulating film 17, and in that case, ion implantation of the P+ ions 35 is not necessary. However, in that case, the entire surface of the polycrystalline St film 21 becomes abnormally long,
Processing becomes a little more difficult.

その後、容量素子を形成すべき領域にレジスト28をバ
ターニングする。
After that, the resist 28 is patterned in the region where the capacitive element is to be formed.

次に、第7D図に示す様に、レジスト28を用い多結晶
St膜21をメモリセル毎に分離して記憶ノードを形成
し、レジスト28を除去する。
Next, as shown in FIG. 7D, the polycrystalline St film 21 is separated into memory cells using a resist 28 to form storage nodes, and the resist 28 is removed.

その後、多結晶Si膜21の表面等に誘電体膜32を形
成し、この誘電体膜32を覆う多結晶Si膜33で容量
素子の他方の電極を形成し、N″領域16aにコンタク
トするビット線を形成して、DRAMのメモリセルを完
威させる。
Thereafter, a dielectric film 32 is formed on the surface of the polycrystalline Si film 21, etc., and the other electrode of the capacitive element is formed with the polycrystalline Si film 33 covering the dielectric film 32, and the bit contacting the N'' region 16a is formed. A line is formed to complete the DRAM memory cell.

以上の様な第4実施例で製造したDRAMでは、多結晶
Si膜2lが異常戒長して突起が形成されているので、
この多結晶Si膜21で構威されている記憶ノードの実
効面積が大きい。
In the DRAM manufactured in the fourth embodiment as described above, the polycrystalline Si film 2l is abnormally lengthened and protrusions are formed.
The effective area of the storage node constituted by this polycrystalline Si film 21 is large.

第8図は、第5実施例を示している。この第5実施例は
、眉間絶縁膜l7の表面にP゛イオン36をイオン注入
するのではなく、第8A図に示す様に層間絶縁膜l7上
等に多結晶St膜36を堆積させてこの多結晶Si膜3
6の表面にP9イオン35のイオンを注入し、第8B図
に示す様に多結晶Si膜36上に更に多結晶Si膜21
を堆積させることを除いて、上述の第4実施例と実質的
に同様の工程を有している。
FIG. 8 shows a fifth embodiment. In this fifth embodiment, instead of implanting P ions 36 into the surface of the glabellar insulating film 17, a polycrystalline St film 36 is deposited on the interlayer insulating film 17 as shown in FIG. 8A. Polycrystalline Si film 3
P9 ions 35 are implanted into the surface of the polycrystalline Si film 21 on the polycrystalline Si film 36 as shown in FIG. 8B.
The process is substantially similar to that of the fourth embodiment described above, except for depositing.

〔発明の効果〕〔Effect of the invention〕

本発明によるメモリ装置の製造方法では、層状体と第2
の導電層とを順次に形戒することを繰り返すだけで容量
素子の一方の電極と他方の電極との対向面積が増加し、
しかも第2の導電層が製造過程で破損しにくいので、容
量素子の容量が大きいメモリ装置を容易に製造すること
ができる。
In the method for manufacturing a memory device according to the present invention, a layered body and a second
The opposing area between one electrode and the other electrode of the capacitive element increases by simply repeating the formation of the conductive layer in sequence.
Moreover, since the second conductive layer is less likely to be damaged during the manufacturing process, it is possible to easily manufacture a memory device in which the capacitive element has a large capacity.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の第1実施例を順次に示す側断面図、第
2図は第1実施例の途中の工程を示す平面図、第3図は
第2実施例を順次に示す側断面図、第4図は第2実施例
の途中の工程を示す平面図、第5図は第3実施例を順次
に示す側断面図、第6図は第3実施例の途中の工程を示
す平面図、第7図は第4実施例を順次に示す側断面図、
第8図は第5実施例の途中の工程を示す側断面図である
。 なお図面に用いた符号において、 16b−・−・−一−−−−・・−・−N1領域21,
23,25.26,27.33 一・−−一−−・−・・・・一多結晶Si膜22.24
・−・・・・−−−−−一・・・NSG膜32・・−・
・・−・−・−−−−−−・一誘電体膜である。
1 is a side sectional view sequentially showing a first embodiment of the present invention, FIG. 2 is a plan view showing intermediate steps in the first embodiment, and FIG. 3 is a side sectional view sequentially showing a second embodiment. 4 is a plan view showing an intermediate step in the second embodiment, FIG. 5 is a side sectional view sequentially showing the third embodiment, and FIG. 6 is a plan view showing an intermediate step in the third embodiment. 7 are side sectional views sequentially showing the fourth embodiment,
FIG. 8 is a side sectional view showing an intermediate step in the fifth embodiment. In addition, in the symbols used in the drawings, 16b-・---1-----...-N1 area 21,
23, 25.26, 27.33 1.--1--..--1 polycrystalline Si film 22.24
・−・・−−−−−1・NSG film 32・・−・
・・−・−・−−−−−−・One dielectric film.

Claims (1)

【特許請求の範囲】 容量素子とアクセストランジスタとでメモリセルが構成
されているメモリ装置の製造方法において、 前記アクセストランジスタの一方のソース・ドレイン領
域に接続する様に第1の導電層を形成する工程と、 各々が前記一方のソース・ドレイン領域上及びその近傍
で側壁を有し互いの前記側壁に接する層状体と第2の導
電層とを、前記第1の導電層上において前記一方のソー
ス・ドレイン領域の広がる方向へ順次に複数回ずつ形成
する工程と、 前記層状体を除去する工程と、 前記除去後の前記第1及び第2の導電層の表面に誘電体
膜を形成する工程と、 前記誘電体膜を覆って第3の導電層を形成する工程とを
夫々具備し、 前記第1及び第2の導電層を前記容量素子の一方の電極
とし、前記第3の導電層を前記容量素子の他方の電極と
する様にしたメモリ装置の製造方法。
[Claims] A method for manufacturing a memory device in which a memory cell is configured of a capacitive element and an access transistor, comprising: forming a first conductive layer so as to be connected to one source/drain region of the access transistor. a layered body and a second conductive layer each having a sidewall on and near the one source/drain region and in contact with each other's sidewall; and a second conductive layer on the first conductive layer.・Sequentially forming the drain region multiple times in the direction in which it spreads; removing the layered body; and forming a dielectric film on the surfaces of the first and second conductive layers after the removal. , forming a third conductive layer covering the dielectric film, the first and second conductive layers being one electrode of the capacitive element, and the third conductive layer being the A method for manufacturing a memory device in which the other electrode of a capacitive element is used as the other electrode.
JP1228618A 1989-09-04 1989-09-04 Manufacture of memory device Pending JPH0391957A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1228618A JPH0391957A (en) 1989-09-04 1989-09-04 Manufacture of memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1228618A JPH0391957A (en) 1989-09-04 1989-09-04 Manufacture of memory device

Publications (1)

Publication Number Publication Date
JPH0391957A true JPH0391957A (en) 1991-04-17

Family

ID=16879170

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1228618A Pending JPH0391957A (en) 1989-09-04 1989-09-04 Manufacture of memory device

Country Status (1)

Country Link
JP (1) JPH0391957A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03296264A (en) * 1990-04-16 1991-12-26 Nec Corp Semiconductor memory cell and its manufacture
JPH04350965A (en) * 1991-05-23 1992-12-04 Samsung Electron Co Ltd Manufacture of capacitor used for memory cell of semiconductor memory device and structure thereof
US5231044A (en) * 1991-09-13 1993-07-27 Goldstar Electron Co., Ltd. Method of making semiconductor memory elements
US5278091A (en) * 1993-05-04 1994-01-11 Micron Semiconductor, Inc. Process to manufacture crown stacked capacitor structures with HSG-rugged polysilicon on all sides of the storage node
EP0595360A1 (en) * 1992-10-30 1994-05-04 Nec Corporation Method of manufacturing a semiconductor device having a cylindrical electrode
JPH06188382A (en) * 1991-12-31 1994-07-08 Hyundai Electron Ind Co Ltd Preparation of electric charge storage of electrode semiconductor memory
US5436187A (en) * 1994-02-22 1995-07-25 Nec Corporation Process for fabricating a semiconductor memory device including a capacitor having a cylindrical storage node electrode
US5480824A (en) * 1992-06-18 1996-01-02 Goldstar Electron Co., Ltd. Semiconductor memory cell capacitor and fabrication method thereof
US5677225A (en) * 1994-04-12 1997-10-14 Lg Semicon, Co. Ltd. Process for forming a semiconductor memory cell

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03296264A (en) * 1990-04-16 1991-12-26 Nec Corp Semiconductor memory cell and its manufacture
JPH04350965A (en) * 1991-05-23 1992-12-04 Samsung Electron Co Ltd Manufacture of capacitor used for memory cell of semiconductor memory device and structure thereof
US5231044A (en) * 1991-09-13 1993-07-27 Goldstar Electron Co., Ltd. Method of making semiconductor memory elements
JPH06188382A (en) * 1991-12-31 1994-07-08 Hyundai Electron Ind Co Ltd Preparation of electric charge storage of electrode semiconductor memory
US5403767A (en) * 1991-12-31 1995-04-04 Hyundai Electronics Industries Co., Ltd. Methods for manufacturing a storage electrode of DRAM cells
US5480824A (en) * 1992-06-18 1996-01-02 Goldstar Electron Co., Ltd. Semiconductor memory cell capacitor and fabrication method thereof
EP0595360A1 (en) * 1992-10-30 1994-05-04 Nec Corporation Method of manufacturing a semiconductor device having a cylindrical electrode
US5278091A (en) * 1993-05-04 1994-01-11 Micron Semiconductor, Inc. Process to manufacture crown stacked capacitor structures with HSG-rugged polysilicon on all sides of the storage node
USRE36786E (en) * 1993-05-04 2000-07-18 Micron Technology, Inc. Process to manufacture crown stacked capacitor structures with HSG-rugged polysilicon on all sides of the storage node
US5436187A (en) * 1994-02-22 1995-07-25 Nec Corporation Process for fabricating a semiconductor memory device including a capacitor having a cylindrical storage node electrode
US5677225A (en) * 1994-04-12 1997-10-14 Lg Semicon, Co. Ltd. Process for forming a semiconductor memory cell

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