JPH0389535A - Semiconductor verifying device - Google Patents

Abstract

PURPOSE:To verify the electric characteristics of LSIs in detail by setting identifying information on a wiring net with reference to a library for storing identifying information and verifying the electric restriction to the wiring net on the basis of the set information. CONSTITUTION:Line type information set on an external signal pin is read from an input data disk 20 and the line type generated at a specific gate output pin and the priority information of the line type are read from a library 21. Then the line type is propagated from the external signal pin on the basis of the line type information set on the pin, and the line type is automatically generated and propagated from the specific gate output pin on the basis of the line type information set on the gate output pin and the priority information of the line type. Thereafter, the line type information set on each wiring net is written on an output data disk 22, and thus, one cycle of processes is completed.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Application Fields Prior Art (Fig. 8) Means and Action Embodiment 1 for Solving the Problems to be Solved by the Invention (1st Embodiment) -3) Second first embodiment (Figure 4.5) Second embodiment (Figure 6) Third embodiment (Figure 7) Effects of the invention [Summary] Electrical characteristics of semiconductors in detail Regarding a semiconductor verification device that can be verified, it is an object of the present invention to provide a semiconductor verification device that can set detailed identification information for identifying a circuit in a wiring net, and can perform detailed verification of the electrical characteristics of an LSI. In a semiconductor verification device for verifying electrical constraints of a wiring net between gates arranged on a logic circuit board, a library is provided for storing identification information for identifying a circuit in the wiring net, and the library is referred to. identification information is set in the wiring net, and electrical constraints of the wiring net are verified based on the identification information set in the wiring net.

Furthermore, in a semiconductor verification device that verifies the electrical constraints of a wiring net between gates arranged on a logic circuit board, identification information for identifying the circuit in the wiring net, and conditions that cause changes to the electrical constraints. and a library that stores identification information corresponding to the conditions, sets identification information for the wiring net by referring to the library, and verifies the electrical constraints of the wiring net based on the identification information set for the wiring net. Configure it as follows.

[Industrial application field]

The present invention relates to a semiconductor verification device, and more particularly, to a semiconductor verification device that can verify in detail the electrical characteristics of a semiconductor after placement and wiring when automatically arranging and wiring a semiconductor cell pattern.

After the placement of the broncs placed on the LSI chip is determined, the purpose of wiring processing is to correctly connect the terminals of the broncs according to the given electrical connections, maintaining insulation between the wiring nets and improving the electrical characteristics. The wiring pattern can be selected arbitrarily as long as the deterioration is within the standard.

-C, if the wiring is too long, the resistance will increase and the electrical characteristics will deteriorate. Therefore, signal lines that are likely to have a delay problem should be connected preferentially and should be provided with a wiring pattern as short as possible. Particularly, when two-layer wiring of metal and polysilicon is performed in an MO3 integrated circuit, it is important to shorten the wiring section passing through the polysilicon layer. Also, it must be noted that the resistance value increases as the number of passes through the through hole increases. Furthermore, in high-speed circuits, in order to reduce parasitic capacitance, the length of interconnects running in parallel may be limited.

By the way, in stage I of circuit design before layout design, circuit simulation is performed using standard transistor model parameters on the premise that the area occupied by the wiring net is uniformly at the same potential. However, the actual parameter values are determined by the dimensions of the figure that realizes the transistor, and parasitic resistance and capacitance intervene depending on the wiring pattern. Therefore, it is necessary to check whether the circuit characteristics intended by the designer have been deteriorated due to inappropriate layout design. To test such electrical characteristics, first calculate the values of transistor parameters and parasitic elements that depend on the layout pattern, and then check the circuit characteristics again using a circuit simulation program. Procedures are carried out. However, due to the limited processing power of circuit simulation programs, it is impractical to test the entire chip using this method, so the chip is usually divided into several functional blocks to examine the influence of circuit characteristics on performance. A method is used in which only the parts with high values are verified.

[Conventional technology]

Conventional element placement methods for arranging elements on this type of logic circuit board include arranging the elements so that the total length of signal lines connecting the elements is minimized. However, since this method does not take into account the signal propagation delay time between elements at the stage of arranging the elements, changes in the arrangement of the elements may occur later.

For example, there is a method described in Japanese Patent Publication No. 64-821 that attempts to deal with the above-mentioned problems. In a system for automatically arranging elements on a logic circuit board, this system assigns a weight to each signal line between elements arranged on the logic circuit board, and adjusts the length of the signal line and the weight given to the signal line. Based on this, the arrangement of elements on the logic circuit board is determined, and element arrangement is performed in consideration of signal propagation delay time between elements.

[Problem to be solved by the invention]

However, in such conventional semiconductor verification equipment, weights (hereinafter referred to as line types) are simply given to signal lines (nets) between elements from the outside, so each signal line is individually weighted. Since the line type must be given,
In addition to being very time-consuming, it is difficult to subdivide or change the line type according to the arrangement of cells, etc. In particular, it is practically impossible to assign line types to all internal nets from the outside due to the large number of nets.

For example, in a conventional semiconductor verification device, as shown in FIG. 8, a signal line 7 is connected to an external signal pin 1 and cells 2 to 6, and a line type "A" is applied to the signal line 7 from the outside. ing. Therefore, since the mode is simply to give data of line type A to a specific external signal pin l, not only the specific external signal pin l, but also internal nets etc. that require a different line type due to their characteristics. If so, you will need to specify the line type again there. Such work is expected to be extremely difficult considering the huge number of nets in reality. Therefore, the above line type information is
It is difficult to use it to check the electrical characteristics of

In order to improve the performance of LSIs, it is necessary to check the electrical characteristics of LSIs with even higher precision, and it is desired to set more detailed classifications (constraint conditions) for wiring nets.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor verification device that can set detailed identification information for identifying a circuit in a wiring net and can perform detailed verification of the electrical characteristics of an LSI. .

[Means to solve the problem]

In order to achieve the above object, a semiconductor verification device according to a first aspect of the invention is a semiconductor verification device for verifying electrical constraints of a wiring net between gates arranged on a logic circuit board, and includes an identification device for identifying a circuit in the wiring net. A library for storing information is provided, identification information is set in the wiring net by referring to the library, and electrical constraints of the wiring net are verified based on the identification information set in the wiring net.

Further, in order to achieve the above object, a semiconductor verification device according to a second invention is a semiconductor verification device for verifying electrical constraints of a wiring net between gates arranged on a logic circuit board, and a method for identifying a circuit in the wiring net. A library is provided that stores identification information, conditions that cause changes to the electrical constraints, and identification information corresponding to the conditions, and the library is referenced to set identification information in the wiring net, and the The configuration is configured to verify the electrical constraints of the wiring net based on the identified identification information.

[Effect]

In the first invention, identification information for identifying a circuit in a wiring net is registered in a library, and the identification information is set in the wiring net with reference to the library. Then, the electrical constraints of the wiring net are verified based on the identification information set for the wiring net.

In the second aspect of the invention, conditions that cause changes in the electrical constraints and identification information corresponding to the conditions are further registered in the library.

Therefore, without giving identification information to each wiring net from the outside, the identification information of the wiring net is automatically generated from the automatic generation source and propagated appropriately. As a result, a detailed check becomes possible. In addition, in the second invention, even if the identification information has the same standard value, when the factors that change the electrical constraints, such as the number of pull-down resistors and the number of output DOTs, are different, the conditions that cause the electrical constraints to change are changed. Based on this, appropriate identification information is automatically generated and propagated. As a result, the electrical characteristics of the LSI can be checked in more detail.

〔Example〕

Hereinafter, the present invention will be explained based on the drawings.

1 to 3 are diagrams showing an embodiment of a semiconductor verification device according to the first invention. First, the positioning of the present invention in semiconductor manufacturing will be explained using the process flow shown in FIG.

In the figure, Pn (n=1. 2...) indicates each step of the flow. In this figure, a logic simulation is performed in which the circuit operation is simulated by giving an external input signal (test pattern) that indicates the operation of the logic circuit at Pl, and the result is output as a signal sequence for each time such as a time chart. Automatically or manually perform placement and wiring processing. Next, set net information in P, and check each electrical characteristic based on the net identification information set in P in P4, that is, wire length check, parallel wire length check, voltage drop check, and wire capacitance check. Perform a check. Here, steps P3 and P4 are called design rule checks or characteristic checks, and the data after this check is passed to the mask manufacturing process from step P5 onwards as mask creation data (see figure 1).
, ps.

The present invention relates to a process for performing a detailed electrical constraint check of an LSI shown in steps P to P4 above, and a verification apparatus therefor.

In order to improve the performance of LSI, when checking wiring length, parallel wiring length, voltage drop, wiring capacitance, etc., it is necessary to change the standard values depending on the configuration of the circuit serving as a load, even if the gate output is the same. These electrical constraint checks are likely to increase more and more in the future, and in order to check each check in detail, it is essential to have a function to set identification information for each wiring net in advance. In this embodiment, this identification information is called a line type.Among the line types, those that affect the entire circuit with respect to signal propagation, such as clock systems and reset systems, pose a particular problem. In order to improve accuracy, the key is how detailed limit values can be set for the wiring net, including the clock system.

In the conventional example, a vA type is given from the outside and how far into the internal cell it is propagated is set for each function. Therefore, due to the configuration in which the line type is provided externally, it is difficult to provide a detailed line type for each wiring net, making it impossible to achieve high accuracy in checking.

The present invention stores line type information and line type priority information generated at specific gate output pins in a predetermined library, and reads data from the library, thereby achieving high accuracy without providing line types from outside. This is used to check electrical characteristics.

Therefore, if the convention value for a net connected to a specific external signal pin or a specific gate output pin is different from the general net, the line type can be propagated from the specific external signal bin/specific gate output bin to the internal net. become.

Bicuspid marking An embodiment of the semiconductor verification device according to the first invention will be specifically described below with reference to FIG. 2.3.

In FIG. 2, 11 is an external signal bin, 12 to 18 are cells, and 19 is a net. In the figure, ASB, C indicates a line type (identification information), and Δ, dan, and dan indicate a line type generation source.

By reading the line type information set in the external signal bin 11 from the manual data disk 20 shown in FIG. It propagates to the stop cell 15. In addition, by reading the library 21 that stores line type information and line type priority information generated at specific gate output pins, line types B and C can be set to specific gate output bins (cell 15 and cell 17 in this case). Automatically generated and propagated from. Here, when a plurality of line types are propagated from cells 16 and 17 as shown in cell 18, line type C having a higher priority is propagated. The direction of propagation is, in principle, from the external input pin to the external output pin, but there may be cases where it is desired to manually restore the original state from the input, such as when there is an internal reset cell. In such a case, the library 21 also stores a propagation information source for the reverse route from the inside to the outside. Having this source of information also makes it possible to return propagated line types to cancel them.

Therefore, in this embodiment, line type A is set for all nets connected to external signal pin 11, as shown in FIG. Therefore, all nets to which line type A is set are checked with the same standard value.

Next, the effect will be explained.

FIG. 3 is a processing flow showing a program for checking electrical characteristic constraints based on net identification information setting.

When the program starts, first, P reads the line type information set to the external signal pin from the input data disk 20, and PI2 reads the line type and line type priority information generated at the specific gate output pin from the library 21. Load.

Next, the line type is propagated from the external signal pin based on the line type information set to the external signal pin in PI3, and the line type is propagated based on the line type information and line type priority set to the specific gate output bin in P. Automatically generate and propagate line types from specific gate output pins. Next, the line type information set for each wiring net is written to the output data disk 22 using PUS, and the process is completed.

As described above, in this embodiment, a library 21 is provided in which line type data and line type priority data generated at a specific gate output pin are stored. Therefore, without giving line types to each net from the outside, the library 21
The line type will be automatically generated and propagated from the automatic source of the specific gate output pin based on the data from. As a result, detailed checks can be made without inputting any data from the outside, greatly improving work efficiency and making it possible to perform electrically severe checks.

In this example, as shown in FIG.
This is an example in which the check is applied to setting the net identification information and checking the set line type in ,P, but since the important point is the information for the net, the application is not limited to the above check only, but can be applied to any place where the net information is used. are all usable. For example, step PH1 shown in FIG.
If placed before , it can be used to control the logic simulation of P2, and can also be used to control placement and wiring. Furthermore, although not shown, it is applicable to all general circuit simulations, general layouts, and verification systems. It goes without saying that this is exactly the same in the second embodiment of the second invention described later.

By the way, the number of pull-down resistors attached to the net and the output DO
There has been a request to change the standard value due to factors such as the number of T, but in the first embodiment, checks can only be made with the same standard value. In other words, there is a difference in the amount of current flowing through the pull-down resistors between when one pull-down resistor is attached to the output and when two pull-down resistors are attached, so the number of gates that can drive the gates connected to the subsequent stage changes ( The same applies to the number of output DOTs that combine the blade side), and in the embodiment of the first invention, it is possible to check only the same standard value.
It may be necessary to perform a more detailed electrical constraint check.

FIG. 4.5 is a diagram showing the first embodiment of the semiconductor verification device according to the second invention, and is an example where line type identification cannot be performed using external pins.

In Fig. 4, 3L 32 is an external signal pin, 33-4
0 is a cell, 4■, 42 is a net, and A, B, C in the figure
indicates the line type, Δ, dan, and dan indicate the line type generation source. In this embodiment, as shown in FIG. 5, in addition to the line type information and line type priority information generated in a specific gate output bin in the library 42, the library 42 also contains the conditions that cause the standard value to be changed and their Line type information corresponding to the conditions, specifically, the line type generated at a specific gate input pin and its propagation conditions are registered. Therefore, as shown in FIG. 4, when multiple line types A and B are propagated from the external pins 31 and 32 to the same net 42, the line type with the highest priority among line types A and B is propagated. I will do it. If the priority is A>B, net 4
2 is set to line type A. This is registered in the library 42 as line type C is generated for the net connected to a specific gate manual pin, and as a propagation condition, processing is performed only for nets in which line type A and line type B are propagated. library 42
Generate line type C from a specific gate input pin by referring to
By propagation, the line type is identified by an internal gate.

In other words, in the embodiment of the first invention, the order of priority is based on whether A has priority over B, or whether B has priority over A, but in this embodiment, when A and (and) B. is characterized by the introduction of an arithmetic method that generates C. In other words, an arithmetic function for generating line type C based on line types A and B has been added.

In the above configuration, FIG. 5 is a processing flow showing a program for checking electrical characteristic constraints by setting net identification information. In explaining this flow, steps that perform the same processing as the program in FIG. 3 of the embodiment of the first invention are given the same numbers and their explanations are omitted, and steps that are different are marked with step numbers. The contents will be explained with .

In the flow shown in FIG. 5, the line type information set to the external signal pin is read at P, and the line type, line type priority, and specific gate input generated at a specific gate output pin are read from the library 42 at P21. Load the line type that occurs on the pin and the propagation conditions for that line type. If P,4 automatically generates and propagates from a specific gate output, PZg automatically generates and propagates from a specific gate input. Next, subdivided line types are set by automatically generating new line types using the arithmetic function described above in PX3.

Therefore, according to this embodiment, it is also possible to say "D" when A.(AND)C. In other words, for automatically generated items, other more detailed rules (classifications) can be made based on external conditions. Being able to perform detailed classification means that it is possible to check characteristics with higher precision.For example, it is possible to generate line types such as A+B=C1A+C=D, C+D=E, and to distinguish between those automatically generated by setting conditions and those automatically generated. You can create new rules with . Even in the conventional example, it seems possible to specify a line type such as C or D from the outside to the internal net, but in reality, it is not possible to specify line types one by one like this. On the other hand, it is not realistic to have as many networks as there are. In contrast, in this embodiment, if predetermined conditions are set, extremely detailed line types can be reliably specified without human intervention, which greatly contributes to improving the performance of semiconductor verification equipment.

FIG. 6 is a diagram showing a second embodiment of the semiconductor verification device according to the second invention, and is an example in which the standard values differ depending on the number of pull-down resistors.

In FIG. 6, 51 is an external signal bin, 52 to 54 are cells, and 55 is a net. As shown in FIG. 6, line type A is propagated from the external pin 51. If line type A has different convention values depending on the number of pull-down resistors RPO, the library 42 has line type A when RP=1, line type ARPI, when RP=2,
Register the line type as ARP2. And library 4
2, the line type is subdivided.

Therefore, even if the number of pull-down resistors has the same standard value, the wire type can be changed according to the number of pull-down resistors, and the electrical characteristics of the LSI can be checked in detail as in the first embodiment. can.

FIG. 7 is a diagram showing a third embodiment of the semiconductor verification apparatus according to the second invention, and is an example in which the standard value differs depending on the number of output DOTs.

In FIG. 7, 61 is an external signal bin, 62 to 64 are cells, and 65 is a net. As shown in FIG. 7, line type A is propagated from the external pin 61. If line type A has different convention values depending on the number of output DOTs, line type A is registered in the library 42 as line type ADOT2 when output DOT=2.

Then, the line type is subdivided by referring to the library 42.

Therefore, even if the factors such as the number of DOTs have the same standard values, the same effects as in the second embodiment can be obtained.

〔Effect of the invention〕

According to the present invention, identification information for identifying a circuit can be set in detail in a wiring net, and electrical characteristics of an LSI can be verified in detail.

[Brief explanation of drawings]

1 to 3 are diagrams showing an embodiment of a semiconductor verification device according to the first invention, FIG. 1 is a flow chart for explaining the position of the present invention in semiconductor manufacturing, and FIG. FIG. 3 is a flowchart showing the electrical characteristic constraint check program; FIG. 4.5 is a diagram showing the first embodiment of the semiconductor verification device according to the second invention; Figure 4 is a diagram showing the propagation of a line type when the line type cannot be identified using an external pin, Figure 5 is a flowchart showing a program for checking electrical characteristic constraints, and Figure 6 is related to the second invention. A diagram showing line type propagation when the convention value differs depending on the number of pull-down resistors, showing a second embodiment of the semiconductor verification device, and FIG. 7 is an output showing a third embodiment of the semiconductor verification device according to the second invention. FIG. 8 is a diagram showing the propagation of line types when the standard values differ depending on the number of DOTs. FIG. 8 is a diagram showing the propagation of line types in a conventional semiconductor verification device. 11.31.32.51.61...External signal pin, 12~18.33~40.52~54.62~64
...Cell, 19.41.42.55.65...
...Net, 20...Input data disk, 21, 42...Library, 22...Output data disk, A, B, C...
... Line type (identification information), person, person, person... Line type source. Agent: Patent Attorney Sada Igeta - H, J,
, ', / ° (Return Figure Figure Figure 5 Figure Figure Figure Figure

Claims (2)

[Claims] (1) In a semiconductor verification device that verifies the electrical constraints of a wiring net between gates arranged on a logic circuit board, a library is provided to store identification information for identifying circuits in the wiring net, and the library is referred to. What is claimed is: 1. A semiconductor verification device, wherein identification information is set in a wiring net, and electrical constraints of the wiring net are verified based on the identification information set in the wiring net. (2) In a semiconductor verification device that verifies the electrical constraints of a wiring net between gates arranged on a logic circuit board, identification information for identifying the circuit in the wiring net, which becomes a factor for changing the electrical constraints. Create a library that stores conditions and identification information corresponding to the conditions, set identification information for the wiring net by referring to the library, and verify the electrical constraints of the wiring net based on the identification information set for the wiring net. A semiconductor verification device characterized by: