JPH0388050A - Multilevel lru control system - Google Patents

Abstract

PURPOSE:To attain clear discrimination based upon priority by executing LRU control corresponding to priority allocated to a block to be cached during the existence of the block in a cache. CONSTITUTION:The least recently used (LRU) control using a LRU control table 11 is executed in accordance with the cache hit/miss state of the block to be cached in a target range from the bank level indicated by one of the 1st pointers 14-0 to 14-(n-1) up to the minimum bank level. When the bank level indicated by the 1st pointer 14 corresponding to a priority level lower than that of the block to be cached is higher than the minimum guarantee level indicated by the 2nd printers 15 - 0 to 15-(n-1) corresponding to the 1st pointer at the occurrence of a cache miss, the 1st pointers 14-0 to 14-(n-1) are updated to reduce the bank levels.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) This invention provides a hierarchical L R U (Least R
Multi-layer LR suitable for recently Used control
Regarding U control method.

(Prior Art) In a disk cache system, a block (cache block) in a cache memory to which disk data is written (staged) is an LR.
It is generally determined according to the U algorithm.

In particular, in recent disk cache systems, a hierarchical LRU algorithm has been applied that sets a priority for each block (with respect to the same column) and determines blocks to be staged according to this priority. Several means for realizing this layered LRU algorithm have been conventionally known.

One is to provide a bit that indicates priority, and items with higher priority indicated by the same bit are always placed at a higher level than those with lower priority (this is done in the first (referred to as the conventional method).

In this first conventional method, once a block is given a high priority, it cannot be evicted unless it is intentionally cleared or all blocks of lower priority are completely eliminated. . The second method is to set the initial priority by intentionally changing the level at which the target block is staged when it misses (Mlss) without limiting it to the highest level. (referred to as the second conventional method). However, this initial priority is valid only once while it exists in the cache.
Thereafter, if any block is hit, it will be upgraded to the highest level regardless of its initial priority.

(Problems to be Solved by the Invention) In the conventional Ill system described above, blocks with high priority have a very high degree of residency and are not easily evicted.

However, on the other hand, even if it is not used at all, it occupies the cache memory forever. Furthermore, when the number of high-priority items increases, the area for low-priority items becomes smaller, resulting in a problem that cache efficiency decreases. On the other hand, in the second conventional method, once a block is hit, the block becomes the highest level, so the degree of residence of a block with a high priority is ambiguous, and the effect of the priority is weak.

This invention was made in view of the above circumstances, and its purpose is to perform LRU control according to the priority (PRY) assigned to the block while the block to be cached exists in the cache. The object of the present invention is to provide a multilayer LRU control method that allows clear differentiation.

Another invention of the present invention is that the cache occupancy capacity and cache residency degree for each priority can be flexibly set.
An object of the present invention is to provide a multi-layer LRU control method that can improve cache efficiency.

[Structure of the Invention] (Means for Solving the Problems) This invention provides means for assigning one of n types of priority to each block to be cached, and means for assigning one of n types of priority to each block to be cached, and A first pointer is provided for each of the above n types of priorities and indicates the current highest bank level for the corresponding priority; a second pointer for which a minimum guarantee level at the highest bank level can be arbitrarily set; a selection means for selecting a corresponding first pointer according to the priority of the block to be cached; and a second pointer selected by the selection means. The target range is from the bank level indicated by pointer 1 to the lowest bank level, and the LRU is
LRU control means that performs LRU control using a management table; and pointer update means that controls updating of the first pointer, the first pointer corresponding to a lower priority than the block to be cached when a cache miss occurs. Pointer updating means configured to update the first pointer to lower the bank level when the bank level indicated by the pointer is higher than the minimum guaranteed level indicated by the second pointer corresponding to the same pointer. It is characterized by having the following. The present invention further provides that, among the first pointers, a first pointer indicating a bank level lower than the minimum guaranteed level indicated by the corresponding second pointer has its contents matched with the minimum guaranteed level. I am trying to update it to .

(Operation) According to the above configuration, LRU control is performed with the target range from the bank level indicated by the first pointer (Pi) corresponding to the priority (PRY-i) assigned to the target block to the lowest bank level. As a result, the hit or missed target block is positioned at the highest level according to its priority. Furthermore, in the case of a cash hit, each block from the highest level to the level one level higher than the level where the target block was located up to that point is downgraded to the level one level lower. In addition, in the case of a cache miss, each block located one level above the lowest level from the top level is downgraded to the next level, and the block located at the lowest level is is expelled. In addition, at the time of a cache miss, only if the bank level indicated by the first pointer (Pl) corresponding to a lower priority than the target block is higher than the minimum guaranteed level indicated by the second pointer (A1) corresponding to the same pointer, this The first pointer (Pl) is updated to point to the next lower level, thereby expanding the area for blocks with a higher priority than the target block. Now, by the above LRU control, the block with priority PRY-i is transferred to the second pointer A I+1
PR whose lower limit is one level higher than the level indicated by
When the block is evicted from the effective area in the cache memory (LRU management table) of Y-i, unless it is hit, it is treated as the same as the next lower priority PRY-i+1, and is further evicted from the effective area of PRY=i+1. If the user is also kicked out, the level is sequentially lowered to priority PRY-i+2. Therefore, by changing the value of the second pointer (minimum guaranteed level), the corresponding priority (PRY)
It becomes possible to expand/shrink the area and adjust the block resident period within the same area.

(Embodiment) FIG. 1 is a block diagram showing an embodiment of an LRU control device to which the present invention is applied. The LRU control device in FIG. 1 performs LRU control of the disk cache system, and H is the bank level of each block (cache block), and more specifically, each column of the cache (cache memory). This is a well-known LRU management table for storing bank levels indicating priorities for each bank for each block forming the column.

12 is L that rearranges blocks based on LRU logic.
The RU control circuit 13 is a tag data control circuit that searches a directory (not shown) and determines hits/misses (cash hits/misses) using disk addresses. In this embodiment, apart from the tag data of the block to be cached, a bit indicating the priority (PRY) of the block is prepared, and the tag data control circuit 13 also detects this priority bit. The value of PRY above is 1
(PRY-i) is 0.1 in the case of n-tier LRU.
- One of n-1, the smaller the number 1, the higher the priority.

14-0.14-l-14-(n-1) are each PR
Y-0゜PRY-1...The current highest level for the block of PRY-n-1 is the pointer value PO, PL.
... P n-1 is a pointer specifying the target range of LRU, 15-0.15-l-15-(n-1) is for PRY-0, PRY-1-PRY-n-1, respectively. The minimum guaranteed level is the pointer value AO, AI...An-
This is a pointer indicated by 1. Pointer 14-0 to 14-(
n-1) is prepared for each column of the cache. Further, the pointer values AO, Al...A n-1 can be arbitrarily set by software processing of a host device (not shown). 1B selects PRY-i detected by the tag data control circuit 13 from among pointer values PO to P n-1 indicated by pointers 14-0 to 14-(n-1) specific to the column to which the block to be cached belongs. The pointer value Pi of the corresponding pointer 14-1 is selected and the LRU control circuit 1
2, a selector (SEL) for outputting; 17, PRY detected by the tag data control circuit 13;

Pointer Pi (i-1
.about.n-1) is a pointer update circuit that updates the points.

Ll is a block information line used for transmitting and receiving block numbers (addresses) between the LRU control circuit 12 and the tag data control circuit 13, and L2 is used for transmitting hit/miss determination results by the tag data control circuit 13. Judgment line, L
Reference numeral 3 denotes a PRY line used for transmitting PRY of a block determined as a hit/miss by the tag data control circuit 13.

Next, the operation of the configuration shown in FIG. 1 will be explained when the number of banks of the cache memory is 8 (that is, the bank levels are from the highest level 1 to the lowest level 8) and a two-layer LRU algorithm is applied (that is, n-2 (case) will be explained with reference to FIGS. 2 and 3 as an example.

Note that FIG. 2 shows the contents (part) of the LRU management table 11 of FIG. 1 as pointer values PO, Pi, and AO.

FIG. 3, which is a diagram chronologically shown in correspondence with AI, is a flowchart for explaining the operation. In FIG. 2, the contents of the LRU management table are arranged in order of level. The first character in parentheses (0 or 1 here) indicates the PTY of the corresponding block, and the second character (here A, B, etc.) in the parentheses indicates the PTY of the corresponding block.
・K) indicates the name of the corresponding block.

■ First, for a certain column, until a block of PRY-〇 is staged for the first time, PRY-0, PRY
-1 pointers 14-0 .
The contents of the pointer value PO9Pi of 14-1 match (there is no area for PRY-0). After that, PR
Only after the block Y-0 is staged, the pointer value PI goes down by one level, and one area for PRY-0 is secured. This state is represented by the symbol 2 in Figure 2.
The construction is shown in the diagram. Hereinafter, a detailed explanation of the operation will be started from this state.

(2) In the state indicated by reference numeral 21 in FIG. 2, it is assumed that the host device issues an access request (1, I) to block I to which PRY-1 is allocated (by software processing or the like). The tag data control circuit 13 searches the directory in response to the above request and determines whether the cache is hit or missed. If (1, I) is a cache miss, the tag data control circuit 13 outputs a hit/miss signal indicating this on the determination line L2, and P
Outputs 1, which is the PRY (priority) of block (2), onto the RY line L3. Also, tag data control circuit 1
3 outputs the block number (address) of block I on block information line LL.

PRY (-1) on PRY line L3 is selector 1B
transmitted to. The input of this selector 1B contains pointers 14-0 to 14-(
Pointer values PO to Pn-1 of n-D (in this example of n-2, pointer values PO, P of pointer 14-0.14-1
i) is supplied. Selector 1B is the pointer value P
Of O and Pl, PRY (-1
) is selected (in this case, Pi).

The pointer value (Pl) selected by the selector 1B is transmitted to the LRU control circuit 12.

The LRU control circuit 12 controls the LRU according to the hit/miss signal on the input L2 which is determined and determined, with the target range being the block from the block at the level indicated by the pointer value (Pl) selected by the selector 16 to the lowest level. Execute logic. Here, since the hit/miss signal indicates a cache miss, the LRU control circuit I2 sets block I to the pointer value pt selected by the selector 16 (pointer 14-1 corresponding to PRY-1 of block Stage it to the level (bank level) 2 indicated by the Boink value PL), and lower the (1.0) to (1,8) that were in levels 2 to 7 by one to levels 3 to 8. . As a result, (1.A) at the lowest level is evicted from the cache memory (LRU management table 11). As a result, the state of the LRU management table 11 indicated by reference numeral 21 in FIG. 2 changes to the state indicated by reference numeral 22 in the figure. In the above-described operation of the LRU control circuit 12, the target range with the pointer value P1 (-PI) as the highest level is taken into consideration without being aware of PRY-i (-1) of the target block (I). It is sufficient to execute the LRU logic using

Therefore, it is possible to use a conventional LRU control circuit as it is for the LRU control circuit 12.

PRY (-1) on PRY line L3 is also transmitted to pointer update circuit 17. This pointer update circuit 17 includes a hit/miss signal on the decision line L2, a block I
Pointer values PO, PI of pointer 14-0.14-1 and pointer 15-0.15- specific to the column to which it belongs
A pointer value AO,At of 1 is also conveyed. Based on this information, the pointer update circuit 17 executes the update operation of PO and PL in accordance with the flowchart of FIG. 3 as follows.

The pointer update circuit 17 first updates the pointer 14-
A variable i for specifying 1 is initialized to O (step SI). Then, the pointer update circuit 17 determines that the variable i is n
(in this case, n-2) (step S2), and as in this embodiment where i-Q, n-2, inn
In this case, it is further checked whether or not there is a cache miss based on the hit/miss signal on the determination line L2 (step S3).

In the case of a cache miss as in this example, the pointer update circuit 17 checks whether i is larger than PRY on PRY line L3 (step S4) i-〇, PRY-
1, if i>PRY is not the case, as in this embodiment,
Furthermore, it is checked whether Pl is larger than A+ (step S
5). This step S5 is performed in consideration of the case where, for example, the value of A+ set by the host device at the time of system startup is changed, and if Pi > AI, Pl becomes the same value as AI. updated (step S
After [l) and L, i is incremented by 1 (step S7).

On the other hand, when Pi > AI (PO > AO) is not the case as in this embodiment where Pi -PO-1 and AI-AO-1 (refer to the state indicated by reference numeral 21 in FIG. 2),
Step S7 is performed by skipping step S6, ie, without updating the PI-PO. As a result, in this embodiment, it becomes i-1.

After step S7 is performed, the process returns to step S2. Here, since i-1, 11m 2, PRY-1, cache miss occurred, PI-PL-2, AI-AI-3, steps 82 to S
Step S7 is performed via Step 5. For this reason, Pl
(-Pi) is not updated, and only i is incremented to 2.

In this cycle i-2, ja in step S2
The condition n no longer holds true. In this case, the operation of the pointer update circuit 17 ends.

■Next, in the state indicated by reference numeral 22 in Fig. 2,
The host device issues an access request (0, j) to block J to which PRY-0 is allocated, and the request (0, j
) has become a cache miss. In this case, a hit/miss signal indicating a cache miss is output on the judgment line L2, a PRY of block J is output on the PRY line L3, and the block number of block J is output on the block information line LL. . When PRY on the PRY line L3 is 0, the selector 16 selects the corresponding pointer 14.
-0 pointer value PO is selected.

The LRU control circuit 12 executes LRU logic in accordance with the hit/miss signal on the determination line L2, targeting blocks from the block at the level indicated by the pointer value (PO) selected by the selector 1B to the lowest level. do. Here, since the hit/miss signal indicates a cache miss, the LRU control circuit 12 sets the block J to the pointer value PO selected by the selector 16.
(Pointer 14-o corresponding to PRY-0 of block J
It is staged to the level (bank level) 1 indicated by the pointer value PO), and the data that was at this level 1 to level 7 (0
．． H) ~ (1, C) 1 each for level 2 ~ level 8
Go down one by one. As a result, the cache memory (LRU management table 1) which was at the lowest level (1.8) is
1) be kicked out. As a result, in Fig. 2, the number 2
The state of the LRU management table 11 indicated by 2 changes to the state indicated by 23 in the figure.

On the other hand, the pointer update circuit 17 updates the pointer P according to the flowchart of FIG.
1 update operation is performed. First, in i-0, step S7 is performed via steps 82 to S5 (since there is a cache miss, imPRY=0, and Pi-Ai). Therefore, at i-0, Pi (-PO) is not updated, and only i is incremented to 1. i-1
In this case, since PRY-0, the condition of i>PRY in step S4 is satisfied. In this case, the pointer update circuit 17 checks whether Pl is smaller than AI (step S8). Then, the pointer update circuit 17
-PI-21,1-As in this example (see the state indicated by reference numeral 22 in FIG. 2), which is Al ceramic 3, Pi < AI
If (PL < Al), that is, if the level of pt is higher than the level of A1, which indicates the minimum guaranteed level for PRY-i, the number of blocks of PRY-i-1 (-0) increases by one. Therefore, Pl (-Pi) is increased by +1 in order to secure the area for that amount (step S9). That is, the pointer update circuit 17 lowers the level of Pl (-Pi) by one (see P1 in the state 23 in FIG. 2). When step S9 is completed, step S7 is executed and becomes i-2. When it becomes i-2, the condition of i<n in step S2 no longer holds, and the operation of the pointer update circuit 17 ends.

■Next, in the state indicated by reference numeral 23 in Fig. 2,
The host device issues an access request (0, K) to the block to which PRY-0 is allocated, and
) has become a cache miss. In this case, a hit/miss signal indicating a cache miss is output on the judgment line L2, a PRY of 0 for the block is output on the PRY line L3, and a block number for the block is output on the block information line L1. . When PRY on the PRY line L3 is 0, the selector 16 selects the corresponding pointer 14.
- Select pointer value PO.

The LRU control circuit 12 executes LRU logic in accordance with the hit/miss signal on the determination line L2, targeting blocks from the block at the level indicated by the pointer value (PO) selected by the selector 16 to the lowest level. do. Here, since the hit/miss signal indicates a cache miss, the LRU control circuit 12 sets the block K to the pointer value PO selected by the selector 16.
(Pointer 14-0 corresponding to PRY-0 in block
It is staged to the level (bank level) 1 indicated by the pointer value PO), and the data that was at this level 1 to level 7 (0
．． J) ~ (1, D) 1 each for level 2 ~ level 8
Go down one by one. As a result, the cache memory (LRU management table 1) that was at the lowest level (1.C) is
1) be kicked out. As a result, in Fig. 2, the number 2
The state of the LRU management table 11 indicated by 3 changes to the state indicated by 24 in the figure.

On the other hand, the pointer update circuit 17 performs the update operation of the pointer PI according to the flowchart shown in FIG.

First, in i-0, (cache miss, 1-PRY
-〇, since it is Pi-AI) Steps 82 to S5
Step S7 is performed via .

Therefore, at i-0, PI (-Pal) is not updated, and only i is incremented to 1. In i-1, since PRY-0, the condition of i>PRY in step S4 is satisfied. In this case, the pointer update circuit 17 checks whether Pl is smaller than AI (step S8). Then, the pointer update circuit 17 outputs Pl −
As in this example (see the state indicated by the reference numeral 23 in FIG. 2) where PL-3 and AI -Al-3, PI < AI
If (PL < At) is not the case, that is, if the level of Pl is less than the level of AI indicating the minimum guaranteed level for PRYmi (here, l - PI - AI - AI, the level of Pi is equal to the level of AI). ), in order not to secure any more area for PRY -i-1 (=O), the process does not proceed to step S9, and the process proceeds to step S5.
Proceed to. In other words, the level of Pl is not lowered (second
(See PL in the state 24 in the figure). Kono result, P
(0.H) out of the area for RY-i-1 (=0) (range from the level indicated by PRY-i = 1 to the level one level above the level indicated by PRY-i), i.e. When the level falls below the level indicated by Pl (0.H), it will remain PRY-1 until it is hit as described later.
be treated equally. Therefore, if it is not used for a long period of time, even PRY-0 may be evicted from the cache memory (LRU management table 11). In other words, according to this embodiment, even if the number of high-priority items increases, the effective area (area for high-priority items) is set to one level higher than the minimum guaranteed level of the next priority. Therefore, the area for items with low priority is not compressed, and a decrease in efficiency can be prevented. In addition, step S
5 and subsequent steps, step S7. The operation of the pointer update circuit 17 ends after S2.

■Next, in the state indicated by reference numeral 24 in FIG.
The host device issues an access request (1, F) to block F to which PRY-1 is allocated, and
) has become Catschhit. in this case,
On the judgment line L2, there is a hit /
The miss signal is on the PRY line L3 as PR of block F.
1, which is Y, and the block number of block F is output on the block information line Ll. The selector 16 is PR
When PRY on the Y line L3 is 1, the pointer value PI of the corresponding pointer 14-1 is selected.

The LRU control circuit 12 executes LRU logic in accordance with the hit/miss signal on the determination line L2, targeting blocks from the block at the level indicated by the pointer value (PI) selected by the selector 16 to the lowest level. do. Here, since the hit/miss signal indicates a cash hit, the LRU control circuit 12 selects the block F from the pointer value PI selected by the selector 16 (of the pointer 14-L corresponding to PRY-1 of block F). It is positioned at the level (bank level) 3 indicated by the pointer value PI), and the level 3 to level 5 (the level to which the hit block F was assigned until then is 1.
(0.H) to (1°G) that were at the next higher level) are lowered by one each to levels 4 to 6. As a result, the state of the LRU management table 11 indicated by reference numeral 24 in FIG. 2 changes to the state indicated by reference numeral 25 in the figure.

On the other hand, the pointer update circuit 17 performs the update operation of the pointer Pl according to the flowchart of FIG.

First, at i-0, the determination process of step S3 is performed via step S2, and in the case of a cash hit as in this example, the process proceeds to the determination process of step S5. i
Since Pl(-PO)-AI (-An) at -0, the condition of Pi>AI in step S5 is not satisfied. In this case, Pl (-PO) is not updated and only i is incremented to 1. next i
-1, Pl (-PL) -Ai (-AI), and therefore Pi (-Pi) is not updated.

■Next, in the state indicated by reference numeral 25 in Fig. 2,
The host device issues an access request (0, H) to block H to which PRY-0 is allocated, and
) has become Catschhit. in this case,
On the judgment line L2, there is a hit /
The miss signal is on the PRY line L3 as PR of block H.
The block number of the block H is outputted on the block information line Ll. The selector 16 is PR
If PRY on the Y line L3 is 0, the pointer value PO of the corresponding pointer 14-0 is selected.

The LRU control circuit 12 performs LRU logic in accordance with the hit/miss signal on the determination line L2, with the target range being blocks from the block at the level indicated by the pointer value (PO) selected by the selector (6) to the lowest level. Here, since the hit/miss signal indicates a cash hit, the LRU control circuit 12 sets the block H to the pointer value P selected by the selector 16.
O(pointer corresponding to PRY-0 of block H (4-
Level (bank level) 1 indicated by pointer value PO of 0
and move the (0.K) to (1°F) that were at levels 1 to 3 (one level higher than the level to which hit block H was previously assigned) to levels 2 to 4. Go down one by one. As a result, the second
LRU management table 11 indicated by reference numeral 25 in the figure
The state changes to the state indicated by reference numeral 26 in the figure. As is clear, by changing the value of pointer value AI, that is, the minimum guaranteed level of pointer P1, PRY
It is possible to expand/reduce the area for -0 and further adjust the residence period of (0, H) in the cache memory (LRU management table 11).

On the other hand, the pointer update circuit 17 performs the update operation of the pointer P1 according to the flowchart of FIG.

First, at i-0, the determination process of step S3 is performed via step S2, and in the case of a cash hit as in this example, the process proceeds to the determination process of step S5. i
At -0, PI (-PO)-AI (-AO), so the condition of Pi > AI in step s5 is not satisfied. In this case, Pi (-PO) is not updated and only i is incremented to 1. Even in the next i-1, Pl (-PL') -AI (-Al
), and therefore Pl (-PL) is not updated.

In addition, although the said Example demonstrated the case of n-2, this invention is also applicable to n layer LRU control of n-3 or more. The present invention is also applicable to n-tier LRU control other than disk cache systems.

[Effects of the Invention] As detailed above, according to the present invention, while a block to be cached exists in the cache, LRU control can be performed according to the priority (PRY) assigned to the block. Clear differentiation can be achieved, and effective multi-layer LRU management based on priorities is possible. In addition, by changing the value of pointer AI (second pointer) that guarantees (the lowest level of) the effective range of priority (PRY-i), the cache occupancy capacity for each corresponding priority and the effect of priority (Cache residency degree) can be set flexibly, so cache efficiency can be improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of an LRU control device to which the present invention is applied, and FIG. 2 is a time series of the contents (part) of the LRU management table 11 shown in FIG. 1 in correspondence with each pointer value. FIG. 3 is a flowchart for explaining the operation. 11...LRU management table, 12...LRU control circuit, 13...tag data control circuit, 14-0 to 14
-(n-1)...Pointer (first pointer) 1
5-0 to 15-(n-1)...Pointer (second pointer), 16...Selector (SEL), 17...Pointer update circuit.

Claims (2)

[Claims] (1) In a system equipped with an LRU management table for storing, for each column of the cache, the bank level indicating the priority of each bank for each block constituting that column, for each block to be cached, the means for assigning one of n types of priorities as a priority, and a first bank level provided for each column and for each of the n types of priorities and indicating the highest bank level at the present time for the corresponding priority. A second pointer that is provided for each of the above n priorities and can arbitrarily set the minimum guarantee level of the highest bank level for the corresponding priority, and selection means for selecting the corresponding first pointer; and cache hit/cache target block for the cache target block, with the target range from the bank level indicated by the first pointer selected by the selection means to the lowest bank level. LRU control means for performing LRU control using the LRU management table according to a miss state; and pointer update means for updating the first pointer; If the bank level indicated by the first pointer corresponding to a lower priority than the cache target block is higher than the minimum guaranteed level indicated by the second pointer corresponding to the same pointer, this first pointer is updated. A multi-layered LRU control system, characterized in that the multi-layered LRU control system is configured to lower the bank level. (2) The pointer updating means updates a first pointer of each of the first pointers that indicates a bank level lower than the minimum guaranteed level indicated by the corresponding second pointer, and changes the bank level to the above level. The multi-layered LRU control system according to claim 1, wherein the multi-layered LRU control system is configured to match a minimum guarantee level.