JPH0387986A - Integrator - Google Patents

Abstract

PURPOSE:To minimize an error after integration by feeding back a sampling error part to an input. CONSTITUTION:Instead of a noise generator in the conventional integrator, a delay device 4 provided on the output of an adder 1, a D/A converter 5 provided on the output of an A/D converter 2, and a differentiator 6 which subtrates the output of the D/A converter from the output of the delay device 4 and inputs it to an adder 1, are provided. And, the delay device 4 has the delay time from the A/D converter 2 to the output of the D/A converter 5, only the difference error part of the sampling error at the A/D converter 2 is taken out by the differentiator 6, and is fed back through the adder 1 to the input. This, the error after the integration is made smaller, and the integration time is shortened to obtain the necessary accuracy.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an integrator, and particularly to an integrator that performs integration after converting an analog signal into dills.

[Prior Art] Conventionally, this type of integrator, as shown in the block diagram in FIG. , an A/D converter 2 that A/D converts the output of the adder 1, and a digital integrator 3 that integrates the output of the A/D converter 2.

In Fig. 2, let the input analog signal 7 be X, the output of the A/D converter 2 be The starting point, b is the integration time, x,
is a natural number, X m =x−−Δx, -0.5<ΔX,
<0.5, X is an integer.

Although it has an error of ΣΔX1, the sampling error becomes a fairly biased value depending on the input, and when taking the average of X by the output of the integrator, the accuracy does not improve much compared to Xl.

this is It is from.

However, since Δx, , is diffused when noise N, is introduced,
N',=N,+ΔXfi-a1 Number, -0,5<N',<0.5゜a is any integer, and if the integration time is made large, that is, if the number of samples is made large, it becomes b, which increases accuracy. be able to.

[Problem to be solved by the invention]

The above-mentioned conventional integrator using an A/D converter has a drawback in that the accuracy during calculation cannot be improved unless noise is added and the number of samples is considerably large.

[Means to solve the problem]

The integrator of the present invention is an integrator that digitally integrates data that has been digitally converted by an A/D converter.
a converter, a differentiator that detects a difference between an output signal of this D/A converter and an input signal when this output signal becomes an input to the A/D converter, and an output of this differentiator. and an adder that feeds back to the input of the A/D converter.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, in which a delay device 4 provided at the output of an adder 1 and an A/D converter are used instead of the noise generator 9 in the conventional integrator shown in FIG. D/A converter 5 provided at the output of D/A converter 2, and D/A converter 5 provided from the output of delay device 4.
A subtractor 6 is provided which inputs the output of the subtraction adder 1 to the subtraction adder 1. The delay device 4 has a delay time from the A/D converter 2 to the output of the D/A converter 5.
The sampling error that occurs is extracted by the difference unit 6 and fed back to the input via the adder 1.

If the sampling error generated in the A/D converter 2 is ΔX, and the input analog signal 7 is X, then the output of the adder l is
. is x 1l = xll + ΔXl1-1 If the output of A/D converter 2 is =Σ X,,=Σ (x' −ΔX++)=Σ
(xll+Δ)C++-1-Δx, )=Σ x7+(Δ
x, -1-ΔXa+J. Here -1 ΔXa-+
<ΔX a+b < 1. Therefore, regardless of the number of samples, the error of Za is always less than 1, so that the maximum accuracy can be obtained with the minimum number of samples.

〔Effect of the invention〕

As described above, the present invention has the effect of minimizing the error after integration by feeding back the sampling error to the input. Further, by reducing the error, there is an effect that the integration time can be shortened in order to obtain the necessary accuracy.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention, and FIG. 2 is a diagram of a conventional A.
FIG. 2 is a configuration diagram of an integrator using a /D converter. 1...Adder, 2...A/D converter,
3...Digital integrator, 4...Delay unit, 5...D/A converter, 6...Differentiator.

Claims (1)

[Claims] In an integrator that digitally integrates data converted digitally by an A/D converter, there is a D/A converter that converts the digitally converted data into analog again, and this D/A converter.
a difference device that detects a difference between the output signal of the converter and the input signal when this output signal is input to the A/D converter; An integrator characterized by having an adder that feeds back to the integrator.