JPH0385761A - Manufacture of semiconductor storage device - Google Patents

Abstract

PURPOSE:To form an embedded contact without using a mask and to do the coupling between the embedded contact and a switching transistor in a self- alignment manner by removing the part formed between a specified position and the surface of an epitaxial layer out of an insulating film, and embedding a second conductivity type of electrode material therein, and then diffusing impurities into an epitaxial layer through a part from which the insulating film is removed from here. CONSTITUTION:A hole is opened in an Si3N4 film, and a trench 15 is digged, and an insulating film 16 is formed at the surface of the trench 15. Next, polysilicon doped into N<+> is deposited in the trench 15, and is etched back so as to form an embedded electrode lower part 17. Next, the part, lying above the surface of the polysilicon, of the insulating film 16 is eliminated, and polysilicon doped into N<+> is deposited again and is etched back so as to flatten the surface, whereby an embedded electrode upper part 19 is formed. Impurities diffuse sideward from on the embedded electrode, and an embedded contact 18 is formed.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a method for manufacturing a semiconductor memory device.

[Prior Art] HO3 [1RAH (Metal Oxide 7 Trillion Conductor Dynamic Random Access Memory) is being miniaturized year by year, so that the integration density is said to quadruple every three years. However, it is difficult to reduce the area occupied by the memory cell below a certain level because it is necessary to provide a sufficient margin for the accumulated charges in the memory cell against noise such as alpha rays. To address this problem, memory cells have been made three-dimensional, and trench capacitor cell and stacked capacitor cell structures have been developed. The trench capacitor cell structure has the disadvantage that it is more susceptible to soft errors caused by alpha rays than conventional two-dimensional structure memory cells with the same capacity. A BSE (Buried Storage Electrode) cell designed to store data is described in IEDH1985. Third
Figure (a) is a plan view of this BSE cell, and Figure 3 (b) is a plan view of this BSE cell.
) is a BB sectional view of FIG. 3(a). In the figure, 50 is r
) + substrate, 52 is an I) - epitaxial layer, 53 is an active region, 56 is an insulating film, 57 is a buried electrode made of N+ polysilicon, 58 is a buried contact, 62 is a transfer gate electrode of a switching transistor, 63 is a switching transistor , 68 is the source of the transistor, 64 is an insulating film between the eyebrows, 65 is a contact pole, and 66 is a bit line made of AI (aluminum).

[Problem to be Solved by the Invention J] When manufacturing the above BSE cell, the buried contact 58 for connecting the buried electrode 57 and the source 68 of the switching transistor is connected to the N+
It is formed by diffusion of impurities from polysilicon below the P+ substrate 50. However, for this purpose, it is necessary to remove the oxide film above the buried contact 58 using a mask. Therefore, there is a problem in that it is not possible to reduce the size of the memory cell in order to provide mask alignment margin.

An object of the present invention is to provide a method for manufacturing a semiconductor memory device, which is characterized in that a buried contact can be formed without using a mask, and that coupling between the buried contact and a switching transistor can be performed in a self-aligned manner. Our goal is to provide the following.

1. Means for Solving the Problem] The object of the present invention is to form a groove reaching the inside of the substrate on the surface of the epitaxial layer of the first conductivity type formed on the surface of the substrate of the first conductivity type. and after forming an insulating film on the inner surface of the eraser, burying an electrode material of the second conductivity type from the bottom of the groove to a predetermined position between the surface of the substrate and the surface of the epitaxial layer, The epitaxial layer is removed from the predetermined position after removing a portion of the insulating film that is formed between the predetermined position and the surface of the epitaxial layer so that a region of the second conductivity type is formed around the predetermined position. further embed the second conductive type electrode material up to the surface of the second conductive type electrode material, diffuse impurities into the epitaxial layer through the portion where the insulating film is removed from the second conductive type electrode material, and diffuse impurities into the epitaxial layer around the groove. This is achieved by a method of manufacturing a semiconductor memory device characterized by forming a region of the second conductivity type.

[Example] Next, examples of the present invention will be described.

FIG. 1(a) is a plan view of a memory cell of a semiconductor memory device according to the present invention, and FIG. 1(b) is a cross-sectional view of the memory cell of FIG. 1(a), without showing the ^A cross section. In the figure, 10 is the P1 substrate, 1
2 is a P- epitaxial layer, 13 is an active region, 16 is an oxide film, 17 is an upper part of a buried electrode made of N+ polysilicon, 18 is a buried contact, 19 is an upper part of a buried electrode made of N1 polysilicon, 20 is an oxide film, 22 is a transfer gate electrode, 23 is a drain, 28 is a source, 25
is a contact pole, and 26 is a bit line consisting of A1. Since the P+ substrate 10 is also used as an electrode,
An impurity concentration of about 19 lXlO cm' is required.

The impurity concentration of the epitaxial layer 12 is about 1×10 15 impurities (c)13, which is the bulk concentration for forming a normal LSI (Large Scale Integrated Circuit), and its thickness is as small as possible as long as it does not interfere with the operation of the device. The thinner the better, usually 1.5
~2°0 micron.

Next, the procedure for manufacturing this semiconductor memory device is shown in FIG.
) to FIG. 2(g).

First, the surface of the epitaxial layer 12 is selectively oxidized.
An active region 13 is formed, and a Si3N4 film 14 is deposited thereon by, for example, TPCVO (low pressure chemical vapor deposition) (FIG. 2(a)). Subsequently, a hole is opened in this Si3N4 film to form a trough 15, and an insulating film 16 is formed on the surface of the trough 15 by, for example, oxidation. The depth inside the clear P+ substrate 10 is set to about 3 microns in order to obtain an appropriate capacitance between the substrate and the substrate (FIG. 2(b)). Next, N+ doped polysilicon is buried in the well 15 and etched back to form a buried electrode lower part 17. At this time, the polysilicon is over-etched so that the surface of the polysilicon is slightly lower than the active region 13 (FIG. 2C). Next, a portion of the insulating film 16 above the surface of the polysilicon 17 is removed, and polysilicon doped with N+ is buried again and etched back to flatten the surface and form a buried electrode upper part 19. The impurity diffuses laterally from the buried electrode upper part 19 to form a buried contact 18 (see FIG. 2(d)).
)). Next, oxidation is performed using Si3N4M as a mask.
After forming the oxide film 20 on the surface of the buried electrode soil portion 19,
Si3N4 film and S 102 forming the active region 13
The film is removed (FIG. 2(O)). Next, a gate oxide film 21 is formed by oxidation, polysilicon is deposited, phosphorus is diffused, and then patterned to form a transfer gate electrode 22. At this time, transistors for peripheral circuits (not shown) are also fabricated at the same time (FIG. 2(f)). Next, a source 28 and a drain 23 are formed by ion implantation, and an interlayer insulating film 24 is deposited. Then, a contact hole 25 is opened, a bit line 26 made of AI and wiring (not shown) are formed, and a passivation film 27 is deposited (FIG. 2(g)).

In the above embodiment, an oxide film (SiO film) is used as the insulating film 16.
was used, but this was converted into S i O2/ S i N /5
A multilayer structure of 502 or a high dielectric constant insulating film may be used. In addition, as a transfer gate electrode, WSi
It is possible to use high melting point metal silicides such as or M o Si2, polycides thereof, and the like.

[Effects of the Invention] In the method for manufacturing a semiconductor memory device of the present invention, it is possible to form a buried contact without using a patterning mask, and the connection between the buried contact and the switching transistor is formed in a self-aligned manner. Therefore, it is possible to reduce the size of the memory cell, and the manufacturing process is shortened, thereby reducing costs.

Further, since the buried electrode does not protrude from the epitaxial layer and is flat, word lines can be easily formed.

[Brief explanation of drawings]

FIGS. 1(a) and (b) are a plan view and a cross-sectional view of a memory cell of a semiconductor memory device according to the present invention, and FIGS. 10.50...P+ substrate, 12.52...P- epitaxial layer. , 13.53...active region, 14...
Si3N4 film, 15... erase, 16, 20.56...
Oxide film, 17... Buried electrode lower part, 19... Buried electrode upper part, 18.58... Buried contact, 57.
...Buried electrode, 21...Gate oxide film, 22', 6
2...1~lanspher gate electrode, 23.63...
Drain, 28,68... Source, 24.64...
Interlayer insulating film, 25.65... Contact hole, 26
．． 66... Bit line, 27... Passivation film.

Claims (1)

[Claims] A groove reaching the inside of the substrate is formed on the surface of the epitaxial layer of the first conductivity type formed on the surface of the substrate of the first conductivity type, and an insulating film is formed on the inner surface of the groove. burying an electrode material of a second conductivity type from the bottom of the groove to a predetermined position between the surface of the substrate and the surface of the epitaxial layer so that a region of the second conductivity type is formed around the bottom of the groove; , after removing a portion of the insulating film between the predetermined position and the surface of the epitaxial layer, further embedding the second conductivity type electrode material from the predetermined position to the surface of the epitaxial layer; , an impurity is diffused into the epitaxial layer through a portion where the insulating film is removed from the electrode material of the second conductivity type to form a region of the second conductivity type around the groove. A method for manufacturing a semiconductor memory device.