JPH0385646U - - Google Patents

Info

Publication number
JPH0385646U
JPH0385646U JP14800389U JP14800389U JPH0385646U JP H0385646 U JPH0385646 U JP H0385646U JP 14800389 U JP14800389 U JP 14800389U JP 14800389 U JP14800389 U JP 14800389U JP H0385646 U JPH0385646 U JP H0385646U
Authority
JP
Japan
Prior art keywords
package body
semiconductor chip
semiconductor device
electrode
pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14800389U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP14800389U priority Critical patent/JPH0385646U/ja
Publication of JPH0385646U publication Critical patent/JPH0385646U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched

Landscapes

  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【図面の簡単な説明】
第1図a,bは本考案の一実施例を示す斜視図
及びA−A′線断面図である。 1……半導体チツプ、2……パツケージ本体、
3……内部リード、4……外部リード、5……電
極パツド。

Claims (1)

    【実用新案登録請求の範囲】
  1. パツケージ本体の側面又は下面に導出した外部
    リードを有する半導体装置において、半導体チツ
    プを搭載した前記パツケージ本体と、前記パツケ
    ージ本体の上面に露出させて設け且つ前記半導体
    チツプの電極と電気的に接続した電極パツドとを
    備えたことを特徴とする半導体装置。
JP14800389U 1989-12-21 1989-12-21 Pending JPH0385646U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14800389U JPH0385646U (ja) 1989-12-21 1989-12-21

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14800389U JPH0385646U (ja) 1989-12-21 1989-12-21

Publications (1)

Publication Number Publication Date
JPH0385646U true JPH0385646U (ja) 1991-08-29

Family

ID=31694471

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14800389U Pending JPH0385646U (ja) 1989-12-21 1989-12-21

Country Status (1)

Country Link
JP (1) JPH0385646U (ja)

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